MPQ9840
The Future of Analog IC Technology
36V, 3.5A, Low IQ,
Synchronous Step-Down Converter
AEC-Q100 Qualified
DESCRIPTION
FEATURES
The
MPQ9840
is
a
high-frequency,
synchronous, rectified, step-down, switch-mode
converter with built-in power MOSFETs. It
offers a very compact solution that achieves
3.5A of continuous output current with excellent
load and line regulation over a wide 3.3V to 36V
input supply range. The switching frequency
can be programmed or synchronized to an
external clock in the range of 350kHz to
2.5MHz. The synchronous operation and ultralow 14μA sleep mode quiescent current provide
high efficiency over the output current load
range, allowing the MPQ9840 to be used in a
variety of step-down applications in automotive
input environments and battery-powered
applications.
Peak-current-mode operation provides fast
transient response and eases loop stabilization.
The excellent low dropout performance allows
the MPQ9840 to be used in high duty cycle
applications.
2μA Low Shutdown Supply Current
14μA No-Load Quiescent Current
Internal 125mΩ High-Side and 55mΩ LowSide MOSFET
350kHz to 2.5MHz Programmable Switching
Frequency
Power Good (PG) Output
External Soft Start (SS)
80ns Minimum On Time
Selectable Forced CCM and AAM
Hiccup Over-Current Protection (OCP)
AEC-Q100 Grade-1
Available in a QFN-16 (3mmx4mm)
Package
APPLICATIONS
Automotive Systems
Industrial Power Systems
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS” and “The Future of Analog IC Technology” are
registered trademarks of Monolithic Power Systems, Inc.
Full protection features include over-current
protection (OCP), short-circuit protection (SCP),
and thermal shutdown. An open-drain power
good (PG) signal indicates when the output is
within 10% of its nominal voltage.
The MPQ9840 is available in a space-saving
QFN-16 (3mmx4mm) package.
TYPICAL APPLICATION
100
90
80
70
60
50
Output Adjustable Version
MPQ9840 Rev. 1.02
7/1/2020
Output Fixed Version
40
10
100
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1000
10000
1
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
ORDERING INFORMATION
Part Number*
Package
Top Marking
QFN-16 (3mmx4mm)
See Below
MPQ9840GL
MPQ9840GL-AEC1
MPQ9840GLE-AEC1**
MPQ9840GLE-33-AEC1***
MPQ9840GLE-5-AEC1***
* For Tape & Reel, add suffix –Z (e.g. MPQ9840GL–Z)
** Wettable flank
***Under Qualification, wettable flank
TOP MARKING (MPQ9840GL & MPQ9840GL-AEC1)
MP: MPS prefix
Y: Year code
W: Week code
9840: First four digits of the part number
LLL: Lot number
TOP MARKING (MPQ9840GLE-AEC1)
MP: MPS prefix
Y: Year code
W: Week code
9840: First four digits of the part number
LLL: Lot number
E: Wettable lead flank
MPQ9840 Rev. 1.02
7/1/2020
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2
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TOP MARKING (MPQ9840GLE-33-AEC1)
MP: MPS prefix
Y: Year code
W: Week code
9840: First four digits of the part number
LLL: Lot number
E: Wettable lead flank
33: 3.3V fixed output
TOP MARKING (MPQ9840GLE-5-AEC1)
MP: MPS prefix
Y: Year code
W: Week code
9840: First four digits of the part number
LLL: Lot number
E: Wettable lead flank
5: 5V fixed output
MPQ9840 Rev. 1.02
7/1/2020
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© 2020 MPS. All Rights Reserved.
3
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
PACKAGE REFERENCE
TOP VIEW
QFN-16 (3mmx4mm)
ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage (VIN) ....................... -0.3V to 40V
Switch voltage (VSW) .....-0.3V to VIN (MAX) + 0.3V
BST voltage (VBST) ..................... VSW (MAX) + 6.5V
EN voltage (VEN) ............................. -0.3V to 40V
PG voltage ...................................... -0.3V to 40V
BIAS voltage ................................... -0.3V to 20V
All other pins ..................................... -0.3V to 6V
Continuous power dissipation (TA = +25°C) (2)
QFN-16 (3mmx4mm) .................................. 2.6W
Junction temperature ................................ 150°C
Lead temperature...................................... 260°C
Storage temperature ................... -65°C to 150°C
Recommended Operating Conditions
Supply voltage (VIN) ........................ 3.3V to 36V
Operating junction temp. (TJ) (3)
…………………………………..-40°C to +125°C
MPQ9840 Rev. 1.02
7/1/2020
Thermal Resistance (4)
θJA
θJC
QFN-16 (3mmx4mm)
JESD51-7 ............................... 48 ...... 11 ... °C/W
Thermal Characterization Parameter (5)
QFN-16 (3mmx4mm)
ΨJT
EV9840-L-00A ……….....….....5.................°C/W
NOTES:
1) Absolute maximum ratings are rated under room temperature
unless otherwise noted. Exceeding these ratings may
damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation
produces an excessive die temperature, causing the regulator
to go into thermal shutdown. Internal thermal shutdown
circuitry protects the device from permanent damage.
3) Mission profiles requiring operation above 125°C TJ may be
supported; contact MPS for details.
4) Measured on JESD51-7, 4-layer PCB.
5) Measured on EV9840-L-00A, 6.35cm*6.35cm size, 2oz, 4layer PCB.
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4
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
ELECTRICAL CHARACTERISTICS
VIN = 12V, VEN = 2V, TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TJ =
+25°C.
Parameter
Symbol
VIN quiescent current
VIN shutdown current
VIN under-voltage lockout
threshold rising
VIN under-voltage lockout
threshold hysteresis
EN rising threshold
IQ
ISHDN
Feedback reference voltage
2.4
0.9
VEN_HYS
RON_HS
LS switch on resistance
RON_LS
FSW
SYNC input low voltage
VSYNC_LOW
SYNC input high voltage
VSYNC_HIGH
14
21
TJ = 25°C
Units
µA
2
6
µA
2.8
3.2
V
mV
1.05
1.2
120
V
mV
784
800
816
mV
792
800
808
mV
125
165
mΩ
55
85
mΩ
VBST - VSW = 5V
RFREQ = 180kΩ or from sync clock
400
475
550
kHz
RFREQ = 82kΩ or from sync clock
850
1000
1150
kHz
RFREQ = 27kΩ or from sync clock
2250
2500
2750
kHz
TON_MIN
(6)
Max
150
INUVHYS
VREF
Typ
29
VEN = 0V
INUVRISING
HS switch on resistance
Switching frequency
Min
VFB = 0.85V, no load, no
switching, TJ = +25°C
VFB = 0.85V, no load, no switching
VEN_RISING
EN threshold hysteresis
Minimum on time
Condition
80
ns
0.4
1.8
V
V
Current limit
ILIMIT_HS
Duty cycle = 40%
4.6
5.6
7.4
A
Low-side valley current limit
ILIMIT_LS
VOUT = 3.3V, L = 4.7µH
3.1
4.4
5.7
A
ZCD current
Reverse current limit
Switch leakage current
IZCD
0.1
A
ILIMIT_REVERSE
3
A
ISW_LKG
0.01
1
µA
10
15
µA
Soft-start current
ISS
VCC regulator
VCC
VCC load regulation
5
5
ICC = 5mA
Thermal shutdown (6)
Thermal shutdown hysteresis (6)
MPQ9840 Rev. 1.02
7/1/2020
VSS = 0.8V
V
3.5
%
TSD
170
°C
TSD_HYS
20
°C
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5
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
ELECTRICAL CHARACTERISTICS
VIN = 12V, VEN = 2V, TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TJ =
+25°C.
Parameter
Symbol
PG rising threshold (VFB/VREF)
PGRISING
PG falling threshold (VFB/VREF)
PG deglitch timer
PGFALLING
TPG_DEGLITCH
PG output voltage low
VPG_LOW
Condition
Min
Typ
Max
Units
VFB rising
85
90
95
%
VFB falling
105
110
115
VFB falling
79
84
89
VFB rising
%
113.5 118.5 123.5
%
PG from low to high
30
µs
PG from high to low
50
µs
ISINK = 2mA
0.2
0.4
V
NOTE:
6) Not tested in production, guaranteed by design and characterization.
MPQ9840 Rev. 1.02
7/1/2020
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6
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL CHARACTERISTICS
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.
170
75
160
70
150
10.2
65
140
60
9.9
55
9.8
110
50
9.7
100
45
9.6
40
-50 -30 -10 10 30 50 70 90110130
9.5
-50 -30 -10 10 30 50 70 90 110130
130
120
90
-50 -30 -10 10 30 50 70 90 110130
5.8
1050
5.7
1030
3.1
3.0
5.6
1010
5.5
990
5.4
970
5.3
950
-50 -30 -10 10 30 50 70 90 110 130
5.2
-50 -30 -10 10 30 50 70 90 110 130
4.5
150
4.4
130
4.3
110
4.2
90
4.1
70
4.0
-50 -30 -10 10 30 50 70 90 110 130
50
-50 -30 -10 10 30 50 70 90 110 130
MPQ9840 Rev. 1.02
7/1/2020
2.9
2.8
2.7
-50 -30 -10 10 30 50 70 90 110 130
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7
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL CHARACTERISTICS (continued)
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.
MPQ9840 Rev. 1.02
7/1/2020
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8
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 5V, Io= 3.5A, L = 4.7μH, FSW = 450kHz, with EMI filters, TA = +25°C, unless
otherwise noted. (7)
CISPR25 Class 5 Average Conducted
Emissions
150kHz -108MHz
150kHz - 108MHz
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
-5
-10
-15
-20
CISPR25 CLASS 5 LIMITS
AVERAGE CONDUCTED EMI (dBuV)
PEAK CONDUCTED EMI (dBuV)
CISPR25 Class 5 Peak Conducted
Emissions
NOISE FLOOR
Frequency (MHz)
1
0.1
10
108
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
-5
-10
-15
-20
CISPR25 CLASS 5 LIMITS
NOISE FLOOR
Frequency (MHz)
1
0.1
10
108
CISPR25 Class 5 Peak Radiated
Emissions
CISPR25 Class 5 Average Radiated
Emissions
150kHz-30MHz
150kHz-30MHz
60
60
55
55
CISPR25 CLASS 5 LIMITS
50
AVERAGE RADIATED EMI (dBuV/m)
PEAK RADIATED EMI (dBuV/m)
50
45
40
35
30
25
20
15
10
NOISE FLOOR
5
0
-5
-10
45
40
35
CISPR25 CLASS 5 LIMITS
30
25
20
15
10
5
0
NOISE FLOOR
-5
-10
1
0.1
Frequency (MHz)
30
1
0.1
Frequency (MHz)
30
CISPR25 Class 5 Peak Radiated
Emissions
CISPR25 Class 5 Average Radiated
Emissions
Horizontal, 30MHz-200MHz
Horizontal, 30MHz-200MHz
55
55
HORIZONTAL POLARIZATION
50
45
CISPR25 CLASS 5 LIMITS
AVERAGE RADIATED EMI (dBuV/m)
PEAK RADIATED EMI (dBuV/m)
45
HORIZONTAL POLARIZATION
50
40
35
30
25
20
15
10
NOISE FLOOR
5
0
-5
30
40
50
60
70
80
90
100
110
120
130
Frequency (MHz)
MPQ9840 Rev. 1.02
7/1/2020
140
150
160
170
180
190
200
40
35
30
25
CISPR25 CLASS 5 LIMITS
20
15
10
5
0
-5
NOISE FLOOR
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
190
200
Frequency (MHz)
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MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 5V, Io= 3.5A, L = 4.7μH, FSW = 450kHz, with EMI filters, TA = +25°C, unless
otherwise noted. (7)
CISPR25 Class 5 Peak Radiated
Emissions
CISPR25 Class 5 Average Radiated
Emissions
Vertical, 30MHz-200MHz
Vertical, 30MHz-200MHz
55
55
VERTICAL POLARIZATION
50
45
CISPR25 CLASS 5 LIMITS
AVERAGE RADIATED EMI (dBuV/m)
PEAK RADIATED EMI (dBuV/m)
45
40
35
30
25
20
15
10
NOISE FLOOR
5
0
-5
30
40
50
60
VERTICAL POLARIZATION
50
70
80
90
100
110
120
130
140
150
160
170
180
190
40
35
30
25
CISPR25 CLASS 5 LIMITS
20
15
10
5
0
NOISE FLOOR
-5
200
30
Frequency (MHz)
40
50
60
70
80
90
100
110
120
130
140
150
160
170
CISPR25 Class 5 Peak Radiated
Emissions
CISPR25 Class 5 Average Radiated
Emissions
Horizontal, 200MHz-1GHz
Horizontal,200MHz-1GHz
55
55
HORIZONTAL POLARIZATION
50
200
45
CISPR25 CLASS 5 LIMITS
AVERAGE RADIATED EMI (dBuV/m)
PEAK RADIATED EMI (dBuV/m)
190
HORIZONTAL POLARIZATION
50
45
40
35
30
25
20
15
10
NOISE FLOOR
5
0
-5
200
300
400
500
600
700
800
900
40
35
30
25
CISPR25 CLASS 5 LIMITS
20
15
10
5
0
NOISE FLOOR
-5
1000
200
Frequency (MHz)
300
400
500
600
700
800
CISPR25 Class 5 Average Radiated
Emissions
Vertical, 200MHz-1GHz
Vertical,200MHz-1GHz
55
55
VERTICAL POLARIZATION
50
AVERAGE RADIATED EMI (dBuV/m)
CISPR25 CLASS 5 LIMITS
40
35
30
25
20
15
NOISE FLOOR
5
0
-5
200
300
400
500
600
Frequency (MHz)
1000
VERTICAL POLARIZATION
50
45
10
900
Frequency (MHz)
CISPR25 Class 5 Peak Radiated
Emissions
PEAK RADIATED EMI (dBuV/m)
180
Frequency (MHz)
700
800
900
1000
45
40
35
30
25
CISPR25 CLASS 5 LIMITS
20
15
10
5
0
NOISE FLOOR
-5
200
300
400
500
600
700
800
900
1000
Frequency (MHz)
NOTE:
7) The EMC test results are based on the application circuit with EMI filters as shown in Figure14.
MPQ9840 Rev. 1.02
7/1/2020
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10
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL PERFORMANCE CHARACTERISTICS(continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
6.5
3,000
5.0
6.0
2,500
4.5
2,000
4.0
1,500
3.5
1,000
3.0
500
2.5
5.5
5.0
4.5
4.0
0 10 20 30 40 50 60 70 80 90 100
0
0
0.06
0.5
0.04
0.4
400
600
800
1000
2.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
3.5
0.3
0.02
0.2
0.00
0.1
-0.02
0.0
-0.04
-0.1
-0.2
-0.06
-0.3
-0.08
-0.10
200
-0.4
0
5
10 15 20 25 30 35 40
MPQ9840 Rev. 1.02
7/1/2020
-0.5
0
0.5
1
1.5
2
2.5
3 3.5
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MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MPQ9840 Rev. 1.02
7/1/2020
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12
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MPQ9840 Rev. 1.02
7/1/2020
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13
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
50
80
45
70
40
60
50
60
35
30
50
25
40
20
30
15
40
30
20
20
10
5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
50
90
80
45
80
40
70
70
35
60
30
50
25
40
20
15
10
5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
MPQ9840 Rev. 1.02
7/1/2020
60
50
40
30
30
20
20
10
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
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14
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MPQ9840 Rev. 1.02
7/1/2020
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15
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
VEN
2V/div.
VOUT
2V/div.
VSW
5V/div.
IL
500mA/div.
VOUT
2V/div.
VPG
5V/div.
IL
5A/div.
VEN
2V/div.
VOUT
2V/div.
IL
5A/div.
VSW
10V/div.
VSW
10V/div.
VEN
2V/div.
VOUT
2V/div.
VOUT
2V/div.
IL
5A/div.
VSW
5V/div.
VOUT
2V/div.
VSYNC
2V/div.
IL
5A/div.
VSW
20V/div.
MPQ9840 Rev. 1.02
7/1/2020
VPG
5V/div.
IL
2A/div.
VSW
20V/div.
VPG
5V/div.
VOUT
2V/div.
IL
2A/div.
VPG
5V/div.
IL
5A/div.
VSW
10V/div.
IL
2A/div.
VOUT
1V/div.
VSYNC
2V/div.
VSW
5V/div.
VSW
5V/div.
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MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MPQ9840 Rev. 1.02
7/1/2020
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17
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MPQ9840 Rev. 1.02
7/1/2020
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MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
PIN FUNCTIONS
Pin #
QFN-16
(3mmx4mm)
Name
1
PHASE
2
VIN
3, 10
SW
4, 9
PGND
5
EN
6
SYNC
7
PG
8
BIAS
11
BST
12
VCC
13
AGND
14
SS
15
FB
16
FREQ
MPQ9840 Rev. 1.02
7/1/2020
Description
Selectable in-phase or 180° out-of-phase of SYNC input. Pull PHASE high to be
in-phase. Pull PHASE low to be 180° out-of-phase. Recommend to connect this pin
to GND if not used.
Input supply. VIN supplies power to all of the internal control circuitries and the
power switch connected to SW. Place a decoupling capacitor to ground close to VIN
to minimize switching spikes.
Switch node. SW is the output of the internal power switch. Pin 3 and Pin 10 are
internally connected.
Power ground. PGND is the reference ground of the power device and requires
careful consideration during PCB layout. For best results, connect PGND with
copper pours and vias.
Enable. Pull EN below the specified threshold to shut the chip down. Pull EN above
the specified threshold to enable the chip.
Synchronize. Apply a 350kHz to 2.5MHz clock signal to SYNC to synchronize the
internal oscillator frequency to the external clock. The external clock should be at
least 250kHz larger than the RFREQ set frequency. SYNC can also be used to select
forced continuous conduction mode (CCM) or advanced asynchronous mode (AAM).
Before the chip starts up, drive SYNC low or leave SYNC floating to choose AAM,
and drive SYNC high to external power source or pull up SYNC to VCC directly to
set the part forced CCM mode.
Power good output. The output of PG is an open drain. Float PG if not used.
Bias input. Connect BIAS to an external power supply (5V ≤ VBIAS ≤ 18V) to reduce
power dissipation and increase efficiency. If not in use, float BIAS or connect BIAS
to ground.
Bootstrap. BST is the positive power supply for the high-side MOSFET driver
connected to SW. Connect a bypass capacitor between BST and SW.
Bias supply. VCC supplies power to the internal control circuit and gate drivers. A
decoupling capacitor (≥1µF) to ground is required close to VCC.
Analog ground. AGND is the reference ground of the logic circuit.
Optional external soft-start time setting. Connect an external capacitor between
this pin and GND to set soft-start time externally. The MPQ9840 sources 10µA from
SS to the soft-start capacitor during start-up. As the SS voltage rises, the feedback
threshold voltage increases to limit inrush current during start-up. Floating the pin
will activate the internal 0.7ms soft-start setting.
Feedback input. For adjustable output version, connect FB to the center point of the
external resistor divider. The feedback threshold voltage is 0.8V. Place the resistor
divider as close to FB as possible. Avoid placing vias on the FB traces. For fixed
output version, connect FB pin to the output directly.
Switching frequency program. Connect a resistor from FREQ to ground to set the
switching frequency.
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MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
BLOCK DIAGRAM
Figure 1-1: Functional Block Diagram of Output Adjustable Version
BIAS
VCC
VCC
VCC
Regulator
VIN
VCC
EN
VREF
Reference
FREQ
BST
Oscillator
PLL
SYNC
ISW
PHASE
+
-
PG
Logic
+
-
VFB
110%xVREF
90%xVREF
VFB
Error Amplifier
SS
FB
SSI
VREF
+
VSSI
R2
AGND
R3
360kΩ
+
VFB -
Control Logic,
OCP,
OTP,
BST Refresh
SW
VCC
VCOMP
R1
460kΩ
C1
52pF
C2
0.2pF
IREVERSE
PGND
Figure 1-2: Functional Block Diagram of Fixed Output Version
MPQ9840 Rev. 1.02
7/1/2020
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MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
OPERATION
The MPQ9840 is a synchronous, step-down,
switching regulator with integrated, internal,
high-side and low-side power MOSFETs. The
MPQ9840 provides 3.5A of highly efficient
output current with current mode control.
The MPQ9840 features a wide input voltage
range, switching frequency programmable from
350kHz to 2.5MHz, external soft start, and
precision current limit. Its very low operational
quiescent current makes it suitable for batterypowered applications.
Pulse-Width Modulation (PWM) Control
At moderate-to-high output currents, the
MPQ9840 operates in a fixed-frequency, peakcurrent-control mode to regulate the output
voltage. A pulse-width modulation (PWM) cycle
is initiated by the internal clock. At the rising
edge of the clock, the high-side power
MOSFET (HS-FET) is turned on and remains
on until its current reaches the value set by the
COMP voltage (VCOMP). If the current in the HSFET does not reach VCOMP in one PWM period,
the HS-FET remains on, saving a turn-off
operation.
When the high-side power switch is off, the lowside MOSFET (LS-FET) is turned on
immediately and remains on until the next cycle
begins.
For each turn-on and -off in a switching cycle,
the HS-FET turns on and off with a minimum on
and off time limit.
Advanced Asynchronous Mode (AAM)
The
MPQ9840
employs
advanced
asynchronous mode (AAM) functionality to
optimize efficiency during light-load or no-load
conditions. AAM can be enabled by connecting
SYNC to a low level (1.8V) before start-up. SYNC can be
used to synchronize switching again after startup.
If continuous conduction mode (CCM) is
enabled, the device is forced to work with a
fixed frequency regardless of the output load
current. The advantage of CCM is the
controllable frequency and smaller output ripple,
MPQ9840 Rev. 1.02
7/1/2020
but it also has low efficiency at light load (see
Figure 2).
If AAM is enabled, the MPQ9840 first enters
non-synchronous operation for as long as the
inductor current is approaching zero at light
load. If the load is further decreased or is at no
load, VCOMP drops below the AAM voltage
(VAAM), making the MPQ9840 enter power-save
mode (PSM). This puts the chip into sleep
mode, which consumes very low quiescent
current to further improve light-load efficiency.
In PSM, the internal clock is reset whenever
VCOMP crosses over VAAM, and the crossover
time is taken as the benchmark of the next
clock. When the load increases, and the DC
value of VCOMP is higher than VAAM, the
operation mode is discontinuous conduction
mode (DCM) or CCM, which have a constant
switching frequency.
Inductor
Current
AAM
(SYNC = Low)
Inductor
Current
Forced CCM
(SYNC = High)
t
Load
Decreased
t
Load
t Decreased
t
t
t
Figure 2 : AAM and Forced CCM
Error Amplifier (EA)
The error amplifier (EA) compares the FB
voltage with the internal reference (0.8V) and
outputs a current proportional to the difference
between the two. This output current is used to
charge or discharge the internal compensation
network to form VCOMP, which is used to control
the power MOSFET current. The optimized
internal compensation network minimizes the
external component count and simplifies the
control loop design.
Bootstrap Charging
The bootstrap capacitor (0.1µF to 1µF) is
charged and regulated to about 5V by the
dedicated internal bootstrap regulator. When
the voltage between the BST and SW nodes is
lower than its regulation, a PMOS pass
transistor connected from VIN to BST is turned
on. The charging current path is from VIN to
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MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
BST to SW. An external circuit should provide
enough voltage headroom to facilitate charging.
When the HS-FET is on, VIN is about equal to
SW, so the bootstrap capacitor cannot be
charged.
At a higher duty cycle operation condition, the
time period available to the bootstrap charging
is less, so the bootstrap capacitor may not be
charged sufficiently. In case the external circuit
does not have sufficient voltage or time to
charge the bootstrap capacitor, extra external
circuitry can be used to ensure that the
bootstrap voltage is in the normal operation
region.
Low Dropout Operation (BST Refresh)
To improve dropout, the MPQ9840 is designed
to operate at close to 100% duty cycle for as
long as the BST to SW voltage is greater than
2.5V. When the voltage from BST to SW drops
below 2.5V, the HS-FET is turned off using an
under-voltage lockout (UVLO) circuit, which
allows the LS-FET to conduct and refresh the
charge on the BST capacitor. In DCM or PSM,
the LS-FET is forced on to refresh the BST
voltage.
Since the supply current sourced from the BST
capacitor is low, the HS-FET can remain on for
more switching cycles than are required to
refresh the capacitor, making the effective duty
cycle of the switching regulator high.
The effective duty cycle during the dropout of
the regulator is mainly influenced by the voltage
drops across the power MOSFET, inductor
resistance, low-side diode and printed circuit
board resistance.
Internal Regulator
Most of the internal circuitry is powered on by
the 5V internal regulator. This regulator takes
the VIN input and operates in the full VIN range.
When VIN is greater than 5V, the output of the
regulator is in full regulation. When VIN is lower
than 5V, the output degrades.
For better thermal performance, connect BIAS
to an external 5V source. VCC and the internal
circuit are powered by BIAS. Since there is an
internal diode between BIAS and the internal
circuit, float BIAS or connect BIAS to GND if it
is not being used.
MPQ9840 Rev. 1.02
7/1/2020
Enable (EN) Control
EN is a digital control pin that turns the
regulator on and off. When EN is pulled below
its threshold voltage, the chip is put into the
lowest shutdown current mode. Pulling EN
above its threshold voltage turns on the part.
Do not float EN.
Programmable Frequency (FREQ)
The MPQ9840 oscillating frequency is
programmed either by an external resistor
(RFREQ) from FREQ to ground or by a logic level
SYNC signal. The value of RFREQ can be
calculated with Equation (1):
RFREQ (kΩ)
170000
fs1.11(kHz)
(1)
The chip can be synchronized to an external
clock ranging from 350kHz up to 2.5MHz
through FREQ/SYNC.
SYNC and PHASE
The internal oscillator frequency can be
synchronized to an external clock ranging from
350kHz up to 2.5MHz through SYNC. The
external clock should be at least 250kHz larger
than the RFREQ set frequency. Ensure that the
high amplitude of the SYNC clock is higher than
1.8V and the low amplitude is lower than 0.4V.
There is no pulse width requirement, but there
is always parasitic capacitance of the pad, so if
the pulse width is too short, a clear rising and
falling edge may not be seen due to the
parasitic capacitance. A pulse longer than
100ns is recommended in application.
PHASE is used when two or more MPQ9840
devices are in parallel with the same SYNC
clock. Pulling PHASE high forces the MPQ9840
to operate in-phase of the SYNC clock. Pulling
PHASE low forces the device to be 180° out-ofphase of the SYNC clock. By setting different
voltages for PHASE, two devices can operate
180° out-of-phase to reduce the total input
current ripple, so a smaller input bypass
capacitor can be used (see Figure 3). The
PHASE rising threshold is about 2.5V with a
400mV hysteresis.
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MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
silicon die temperature is higher than its upper
threshold, the power MOSFETs are shut down.
When the temperature is lower than its lower
threshold, thermal shutdown is removed and
the chip is enabled again.
Figure 3: In-Phase and 180° Out-of-Phase
Soft Start (SS)
Soft start (SS) is implemented to prevent the
converter output voltage from overshooting
during start-up. When the chip starts up, an
internal current source begins charging the
external soft-start capacitor. The internal SS
voltage (VSSI) rises with the soft-start voltage
(VSS), but VSSI is a little different with VSS due to
a 0.5V offset and some delay. When VSS is
lower than 0.5V, VSSI is 0V. VSSI rises from 0V to
0.8V during the period of VSS rising from 0.5V to
1.6V. At this time the error amplifier uses VSSI
as the reference, so the output voltage ramps
up from 0V to the regulated value following VSSI
rising. When VSS reaches 1.6V, VSSI is 0.8V and
overrides the internal VREF, so the error
amplifier uses the internal VREF as the reference.
The soft-start time (tSS) set by the external SS
capacitor can be calculated with Equation (2):
t SS (ms)
CSS (nF) 1.1V
ISS (A)
(2)
Where CSS is the external SS capacitor, and ISS
is the internal 10μA SS charge current.
There is also an internal fixed 700us soft start.
The final SS time is determined by the longer
time between 700us and the external SS setting
time.
SS can be used for tracking and sequencing.
Pre-Bias Start-Up
During start-up, if VFB > VSSI-150mV, then the
output has a pre-bias voltage, and neither the
HS-FET or LS-FET turn on until VSSI-150mV is
higher than FB.
Thermal Shutdown
Thermal shutdown is implemented to prevent
the chip from running away thermally. When the
MPQ9840 Rev. 1.02
7/1/2020
Current Comparator and Current Limit
The power MOSFET current is accurately
sensed via a current sense MOSFET. The
current is then fed to the high-speed current
comparator for current-mode control purposes.
The current comparator takes this sensed
current as one of its inputs. When the HS-FET
is turned on, the comparator is first blanked
until the end of the turn-on transition to avoid
noise. Then the comparator compares the
power switch current with VCOMP. When the
sensed current is higher than VCOMP, the
comparator outputs low to turn off the HS-FET.
The maximum current of the internal power
MOSFET is limited cycle-by-cycle internally.
Hiccup Protection
When the output is shorted to ground, causing
the output voltage to drop below 55% of its
nominal output, the IC is shut down
momentarily and begins discharging the softstart capacitor. The IC restarts with a full soft
start when the soft-start capacitor is fully
discharged. This hiccup process is repeated
until the fault is removed.
Start-Up and Shutdown
If both VIN and EN are higher than their
appropriate thresholds, the chip starts up. The
reference block starts first, generating a stable
reference voltage and current, and then the
internal regulator is enabled. The regulator
provides a stable supply for the rest of the
circuitries.
While the internal supply rail is up, an internal
timer holds the power MOSFET off for about
50µs to blank any start-up glitches. When the
soft-start block is enabled, the SS output is held
low to ensure that the rest of the circuitries are
ready before slowly ramping up.
Three events can shut down the chip: EN low,
VIN low, and thermal shutdown. In the
shutdown procedure, the signaling path is
blocked first to avoid any fault triggering. VCOMP
and the internal supply rail are then pulled down.
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MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
The floating driver is not subject to this
shutdown command, but its charging path is
disabled.
Power Good (PG) Output
The MPQ9840 includes an open-drain power
good (PG) output that indicates whether the
regulator output is within ±10% of its nominal
output range. When the output voltage moves
outside of this range, the PG output is pulled to
ground.
MPQ9840 Rev. 1.0
7/1/2020
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MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
APPLICATION INFORMATION
Setting the Output Voltage
The external resistor divider connected to FB
sets the output voltage (see Figure 4).
Where ∆IL is the peak-to-peak inductor ripple
current.
Choose the inductor ripple current to be
approximately 30% of the maximum load
current. The maximum inductor peak current
can be calculated with Equation (5):
ILP ILOAD
Figure 4: Feedback Network
Choose RFB1 first, RFB2 can then be calculated
with Equation (3):
R FB2
R FB1
VOUT
1
0.8V
(3)
Table 1 lists the recommended feedback
resistor values for common output voltages.
For fixed output version, connect FB pin to the
output directly.
Table 1: Resistor Selection for Common Output
Voltages
VOUT (V)
3.3
5
RFB1 (kΩ)
41.2 (1%)
68.1 (1%)
RFB2 (kΩ)
13 (1%)
13 (1%)
MPQ9840 Rev. 1.02
7/1/2020
VOUT
V
(1 OUT )
fSW IL
VIN
(4)
(5)
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous and therefore requires a
capacitor to supply AC current to the converter
while maintaining the DC input voltage. For the
best performance, use low ESR capacitors.
Ceramic capacitors with X5R or X7R dielectrics
are highly recommended because of their low
ESR and small temperature coefficients.
For most applications, use a 4.7µF to 10µF
capacitor. It is strongly recommended to use
another lower-value capacitor (e.g.: 0.1µF) with
a small package size (0603) to absorb highfrequency switching noise. Place the smaller
capacitor as close to VIN and GND as possible.
Since CIN absorbs the input switching current, it
requires an adequate ripple current rating. The
RMS current in the input capacitor can be
estimated with Equation (6):
ICIN ILOAD
Selecting the Inductor
A 1µH to 10µH inductor with a DC current rating
at least 25% higher than the maximum load
current is recommended for most applications.
For higher efficiency, choose an inductor with a
lower DC resistance. A larger-value inductor
results in less ripple current and a lower output
ripple voltage, but also has a larger physical
size, higher series resistance, and lower
saturation current. A good rule for determining
the inductor value is to allow the inductor ripple
current to be approximately 30% of the
maximum load current. The inductance value
can then be calculated with Equation (4):
L
VOUT
V
(1 OUT )
2fSW L
VIN
VOUT
V
(1 OUT )
VIN
VIN
(6)
The worst-case condition occurs at VIN = 2VOUT,
shown in Equation (7):
ICIN
ILOAD
2
(7)
For simplification, choose an input capacitor
with an RMS current rating greater than half of
the maximum load current.
The input capacitor can be electrolytic, tantalum,
or ceramic. When using electrolytic or tantalum
capacitors, add a small, high-quality ceramic
capacitor (e.g.: 0.1μF) as close to the IC as
possible. When using ceramic capacitors,
ensure that they have enough capacitance to
provide a sufficient charge to prevent excessive
voltage ripple at the input.
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MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
The input voltage ripple caused by the
capacitance can be estimated with Equation (8):
I
V
V
VIN LOAD OUT (1 OUT )
fSW CIN VIN
VIN
VIN
VIN
RUP
EN
(8)
RDOWN
Selecting the Output Capacitor
The output capacitor maintains the DC output
voltage. Ceramic, tantalum, or low ESR
electrolytic capacitors are recommended. For
best results, use low ESR capacitors to keep
the output voltage ripple low. The output
voltage ripple can be estimated with Equation
(9):
V
V
1
) (9)
VOUT OUT (1 OUT ) (RESR
fSW L
VIN
8fSW COUT
Figure 5: Adjustable UVLO Using EN Divider
The UVLO threshold can be calculated with
Equation (12) and Equation (13):
INUVRISING (1
R UP
) VEN_RISING
R DOWN
(12)
INUVFALLING (1
R UP
) VEN_FALLING
R DOWN
(13)
Where L is the inductor value, and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
Where VEN_RISING is 1.05V, and VEN_FALLING is
0.93V.
For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency and causes the majority of the output
voltage ripple. For simplification, the output
voltage ripple can be estimated with Equation
(10):
External BST Diode and Resistor
An external BST diode can enhance the
efficiency of the regulator when the duty cycle is
high. A power supply between 2.5V and 5V can
be used to power the external bootstrap diode.
VCC or VOUT is recommended to be the power
supply in the circuit (see Figure 6).
VOUT
VOUT
V
(1 OUT )
8 fSW L COUT
VIN
2
(10)
For tantalum or electrolytic capacitors, the ESR
dominates the impedance at the switching
frequency. For simplification, the output ripple
can be approximated with Equation (11):
VOUT
VOUT
V
(1 OUT ) RESR
fSW L
VIN
(11)
Figure 6: Optional External Bootstrap Diode to
Enhance Efficiency
The characteristics of the output capacitor also
affect the stability of the regulation system. The
MPQ9840 can be optimized for a wide range of
capacitance and ESR values.
The recommended external BST diode is
IN4148, and the recommended BST capacitor
value is 0.1µF to 1μF.
VIN UVLO Setting
The MPQ9840 has an internal, fixed, UVLO
threshold. The rising threshold is 2.8V, while
the falling threshold is about 2.65V. For
applications that require a higher UVLO point,
an external resistor divider between VIN and
EN can be used to achieve a higher equivalent
UVLO threshold (see Figure 5).
A resistor in series with the BST capacitor (RBST)
can reduce the SW rising rate and voltage
spikes. This helps enhance EMI performance
and reduce the voltage stress at a high VIN. A
higher resistance is better for SW spike
reduction but compromises efficiency. To make
a tradeoff between EMI and efficiency, a ≤20Ω
RBST is recommended.
MPQ9840 Rev. 1.02
7/1/2020
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MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
PCB Layout Guidelines (8)
Efficient PCB layout, is critical for stable
operation, especially for the input capacitor
placement. A four-layer layout is strongly
recommended to achieve better thermal
performance. For best results, refer to Figure 7
and follow the guidelines below.
1.
Place the symmetric input capacitors as
close to VIN and GND as possible.
Recommend to connect pin1 to GND for
symmetric input structure if in-phase not
used. Pin3 and pin10 are internally
connected. Connecting together on layout or
not are both OK. Recommend to leave pin3
floating for shorter pin4 and pin1 trace and
smaller input hot loop.
2.
Use a large ground plane to connect to
PGND directly.
3.
Add vias near PGND if the bottom layer is a
ground plane.
4.
Ensure that the high-current paths at GND
and VIN have short, direct, and wide traces.
5.
Place the ceramic input capacitors,
especially the small package size (0603)
input bypass capacitor, as close to VIN and
PGND as possible to minimize highfrequency noise.
6.
Keep the connection of the input capacitor
and VIN as short and wide as possible.
7.
Place the VCC capacitor as close to VCC
and GND as possible.
8.
Route SW and BST away from sensitive
analog areas such as FB.
9.
Place the feedback resistors close to the
chip to ensure that the trace connecting to
FB is as short as possible.
Top Layer
Inner Layer 1
Inner Layer 2
10. Use multiple vias to connect the power
planes to the internal layers.
NOTE:
8) The recommended PCB layout is based on Figure 8.
Bottom Layer
Figure 7: Recommended PCB Layout
MPQ9840 Rev. 1.02
7/1/2020
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MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
13
4, 9
TYPICAL APPLICATION CIRCUITS
13
4, 9
Figure 8: VOUT = 3.3V, FSW = 500kHz
Figure 9: VOUT = 5V, FSW = 500kHz
MPQ9840 Rev. 1.02
7/1/2020
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MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL APPLICATION CIRCUITS (continued)
Figure 10: VOUT = 3.3V, FSW = 2.2MHz
U1
VIN
3.3V-36V
GND
2
C1A
10μF
R1
100kΩ
C1B
10μF
C1C C1D
0.1μF 0.1μF
5
EN
VIN
BST
EN
SW
11
C5
0.1μF
L1
3, 10
R3
68.1kΩ
12
R5
100kΩ
PG
VCC
FB
C4
1μF
C6
10pF
C2A C2B
22μF 22μF
VOUT
GND
15
R4
13kΩ
7
PG
SS
14
C3
4.7nF
SYNC
5V/3.5A
2.2μH
6
SYNC
FREQ
R6
10Ω
16
R2
33kΩ
PHASE
BIAS
PGND
AGND
13
1
4, 9
PHASE
8
C7
0.1uF
Figure 11: VOUT = 5V, FSW = 2.2MHz
MPQ9840 Rev. 1.02
7/1/2020
www.MonolithicPower.com
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© 2020 MPS. All Rights Reserved.
29
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL APPLICATION CIRCUITS (continued)
Figure 12: VOUT = 3.3V, FSW = 500kHz for Big FB Resistor Divider Application
Figure 13: VOUT = 3.3V, FSW = 2.2MHz for Big FB Resistor Divider Application
MPQ9840 Rev. 1.02
7/1/2020
www.MonolithicPower.com
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© 2020 MPS. All Rights Reserved.
30
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
Figure 14: Application Circuit with EMI Filter @VOUT = 5V/3.5A, FSW = 450kHz
U1
VIN
3.3V-36V
GND
2
C1A
10μF
R1
100kΩ
C1B
10μF
C1C C1D
0.1μF 0.1μF
5
EN
12
R5
100kΩ
PG
VIN
BST
C5
0.1μF
L1
MPQ9840
EN
SW
3, 10
FB
6
C2A C2B
22μF 22μF
VOUT
PG
SS
15
14
C3
4.7nF
SYNC
3.3V/3.5A
10μH
GND
VCC
C4
1μF
7
11
SYNC
FREQ
R6
NS
16
R2
169kΩ
PHASE
BIAS
PGND
AGND
13
1
4, 9
PHASE
8
C7
NS
Figure 15: 3.3V Fixed Output, FSW = 500kHz
MPQ9840 Rev. 1.02
7/1/2020
www.MonolithicPower.com
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31
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
Figure 16: 5V Fixed Output, FSW = 500kHz
MPQ9840 Rev. 1.02
7/1/2020
www.MonolithicPower.com
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32
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
PACKAGE INFORMATION
QFN-16 (3mmx4mm)
Non-Wettable Flank
MPQ9840 Rev. 1.02
7/1/2020
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33
MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
PACKAGE INFORMATION (continued)
QFN-16 (3mmx4mm)
Wettable Flank
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MPQ9840 Rev. 1.02
7/1/2020
www.MonolithicPower.com
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© 2020 MPS. All Rights Reserved.
34
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