MPQ9841
36V, 1A, Low IQ,
Synchronous Step-Down Converter
AEC-Q100 Qualified
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The
MPQ9841
is
a
high-frequency,
synchronous, rectified, step-down, switch-mode
converter with built-in power MOSFETs. It
offers a very compact solution that achieves 1A
of continuous output current with excellent load
and line regulation over a wide 3.3V to 36V
input supply range. The switching frequency
can be programmed or synchronized to an
external clock in the range of 350kHz to
2.5MHz. The synchronous operation and ultralow 14μA sleep mode quiescent current provide
high efficiency over the output current load
range, allowing the MPQ9841 to be used in a
variety of step-down applications in automotive
input environments and battery-powered
applications.
Peak-current-mode operation provides fast
transient response and eases loop stabilization.
The excellent low dropout performance allows
the MPQ9841 to be used in high duty cycle
applications.
Full protection features include over-current
protection (OCP), short-circuit protection (SCP),
and thermal shutdown. An open-drain power
good (PG) signal indicates when the output is
within 10% of its nominal voltage.
2μA Low Shutdown Supply Current
14μA No-Load Quiescent Current
Internal 125mΩ High-Side and 115mΩ LowSide MOSFET
350kHz to 2.5MHz Programmable Switching
Frequency
Power Good (PG) Output
External Soft Start (SS)
80ns Minimum On Time
Selectable Forced CCM and AAM
Low Dropout Mode
Hiccup Over-Current Protection (OCP)
AEC-Q100 Grade 1
Available in a QFN-16 (3mmx4mm)
Package
APPLICATIONS
Automotive Systems
Industrial Power Systems
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS” and “The Future of Analog IC Technology” are
registered trademarks of Monolithic Power Systems, Inc.
The MPQ9841 is available in a space-saving
QFN-16 (3mmx4mm) package.
TYPICAL APPLICATION
100
90
80
70
AGND
PGND
60
50
40
10
Output Adjustable Version
MPQ9841 Rev.1.02
5/10/2019
100
1000
Output Fixed Version
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© 2019 MPS. All Rights Reserved.
1
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
ORDERING INFORMATION
Part Number*
MPQ9841GL
MPQ9841GL-AEC1
MPQ9841GLE-AEC1**
MPQ9841GLE-33-AEC1-Z***
MPQ9841GLE-5-AEC1-Z***
Package
Top Marking
QFN-16 (3mmx4mm)
See Below
* For Tape & Reel, add suffix –Z (e.g. MPQ9841GL–Z)
** Wettable flank
***Under Qualification, wettable flank
TOP MARKING (MPQ9841GL & MPQ9841GL-AEC1)
MP: MPS prefix
Y: Year code
W: Week code
9841: First four digits of the part number
LLL: Lot number
TOP MARKING (MPQ9841GLE-AEC1)
MP: MPS prefix
Y: Year code
W: Week code
9841: First four digits of the part number
LLL: Lot number
E: Wettable lead flank
MPQ9841 Rev.1.02
5/10/2019
www.MonolithicPower.com
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© 2019 MPS. All Rights Reserved.
2
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TOP MARKING (MPQ9841GLE-33-AEC1)
MP: MPS prefix
Y: Year code
W: Week code
9841: First four digits of the part number
LLL: Lot number
E: Wettable lead flank
33: 3.3V fixed output
TOP MARKING (MPQ9841GLE-5-AEC1)
MP: MPS prefix
Y: Year code
W: Week code
9841: First four digits of the part number
LLL: Lot number
E: Wettable lead flank
5: 5V fixed output
MPQ9841 Rev.1.02
5/10/2019
www.MonolithicPower.com
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© 2019 MPS. All Rights Reserved.
3
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
PACKAGE REFERENCE
TOP VIEW
(MPQ9841GL & MPQ9841GL-AEC1
& MPQ9841GLE-AEC1)
TOP VIEW
(MPQ9841GLE-33-AEC1
& MPQ9841GLE-5-AEC1)
QFN-16 (3mmx4mm)
QFN-16 (3mmx4mm)
ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage (VIN) ....................... -0.3V to 40V
Switch voltage (VSW) .....-0.3V to VIN (MAX) + 0.3V
BST voltage (VBST) ..................... VSW (MAX) + 6.5V
EN voltage (VEN) ............................. -0.3V to 40V
PG voltage ...................................... -0.3V to 40V
BIAS voltage ................................... -0.3V to 20V
All other pins ..................................... -0.3V to 6V
Continuous power dissipation (TA = +25°C) (2)
QFN-16 (3mmx4mm) .................................. 2.6W
Junction temperature ................................ 150°C
Lead temperature...................................... 260°C
Storage temperature ................... -65°C to 150°C
Recommended Operating Conditions
Supply voltage (VIN) ........................ 3.3V to 36V
Operating junction temp. (TJ) (3)
…………………………………...-40°C to +125°C
MPQ9841 Rev.1.02
5/10/2019
Thermal Resistance (4)
θJA
θJC
QFN-16 (3mmx4mm)
JESD51-7 ............................... 48 ...... 11 ... °C/W
Thermal Characterization Parameter (5)
QFN-16 (3mmx4mm)
ΨJT
EV9841-L-00A ………....…......5.................°C/W
NOTES:
1) Absolute maximum ratings are rated under room temperature
unless otherwise noted. Exceeding these ratings may
damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation
produces an excessive die temperature, causing the regulator
to go into thermal shutdown. Internal thermal shutdown
circuitry protects the device from permanent damage.
3) Mission profiles requiring operation above 125°C TJ may be
supported; contact MPS for details.
4) Measured on JESD51-7, 4-layer PCB.
5) Measured on EV9841-L-00A, 6.35cm* 6.35cm size, 2oz, 4layer PCB.
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4
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
ELECTRICAL CHARACTERISTICS
VIN = 12V, VEN = 2V, TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TJ =
+25°C.
Parameter
Symbol
VIN quiescent current
IQ
VIN shutdown current
VIN under-voltage lockout
threshold rising
VIN under-voltage lockout
threshold hysteresis
EN rising threshold
EN threshold hysteresis
ISHDN
2.4
VEN_RISING
VEN_HYS
VREF
RON_HS
RON_LS
Switching frequency
FSW
Minimum on time (6)
SYNC input low voltage
SYNC input high voltage
Current limit
Low-side valley current limit
ZCD current
Reverse current limit
Switch leakage current
Soft-start current
VCC regulator
VCC load regulation
0.9
TJ = 25°C
VBST - VSW = 5V
RFREQ = 180kΩ or from sync clock
RFREQ = 82kΩ or from sync clock
RFREQ = 27kΩ or from sync clock
Duty cycle = 40%
VOUT = 3.3V, L = 4.7µH
TSD
(6)
PGRISING
PG falling threshold (VFB/VREF)
PGFALLING
TPG_DEGLITCH
PG output voltage low
VPG_LOW
Units
14
21
µA
2
29
6
µA
2.8
3.2
V
400
850
2250
1.05
120
800
800
125
115
475
1000
2500
80
mV
1.2
816
808
165
155
550
1150
2750
1.8
2.1
1.1
5
2.5
1.35
0.05
1.5
0.01
10
5
2.9
1.6
1
15
3.5
170
TSD_HYS
PG rising threshold (VFB/VREF)
Max
0.4
ILIMIT_REVERSE
ISW_LKG
ISS
VSS = 0.8V
VCC
ICC = 5mA
(6)
PG deglitch timer
784
792
tON_MIN
VSYNC_LOW
VSYNC_HIGH
ILIMIT_HS
ILIMIT_LS
IZCD
Typ
150
INUVHYS
HS switch on resistance
LS switch on resistance
Thermal shutdown hysteresis
Min
VFB = 0.85V, no load, no
switching, TJ = +25°C
VFB = 0.85V, no load, no switching
VEN = 0V
INUVRISING
Feedback reference voltage
Thermal shutdown
Condition
VFB rising
VFB falling
VFB falling
VFB rising
PG from low to high
PG from high to low
ISINK = 2mA
20
85
90
95
105
110
115
79
84
89
113.5 118.5 123.5
30
50
0.2
0.4
V
mV
mV
mV
mΩ
mΩ
kHz
kHz
kHz
ns
V
V
A
A
A
A
µA
µA
V
%
C
°C
%
%
%
µs
µs
V
NOTE:
6) Not tested in production, guaranteed by design and characterization.
MPQ9841 Rev.1.02
5/10/2019
www.MonolithicPower.com
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© 2019 MPS. All Rights Reserved.
5
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL CHARACTERISTICS
VIN=12V, TJ=-40oC to +125oC, unless otherwise noted.
170
150
160
140
150
130
140
10.2
10.1
10.0
9.9
130
120
120
110
9.7
100
9.6
110
100
90
-50 -30 -10 10 30 50 70 90 110130
1050
90
-50 -30 -10 10 30 50 70 90110130
9.5
-50 -30 -10 10 30 50 70 90 110130
2.8
1.7
2.7
1030
9.8
1.6
2.6
1.5
1010
2.5
990
2.4
1.4
970
2.3
1.3
950
-50 -30 -10 10 30 50 70 90 110 130
2.2
-50 -30 -10 10 30 50 70 90 110 130
1.2
-50 -30 -10 10 30 50 70 90 110 130
1.5
100
1.4
80
1.3
60
1.2
40
1.1
20
1.0
-50 -30 -10 10 30 50 70 90 110 130
0
-50 -30 -10 10 30 50 70 90 110 130
MPQ9841 Rev.1.02
5/10/2019
www.MonolithicPower.com
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© 2019 MPS. All Rights Reserved.
6
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL CHARACTERISTICS (continued)
VIN=12V, TJ=-40oC to +125oC, unless otherwise noted.
16.0
2.5
15.5
2.4
15.0
2.3
14.5
2.2
14.0
2.1
13.5
2.0
13.0
1.9
12.5
1.8
12.0
1.7
11.5
11.0
-50 -30 -10 10 30 50 70 90 110 130
1.6
1.5
-50 -30 -10 10 30 50 70 90 110 130
3.0
2.9
Rising
2.8
2.7
2.6
2.5
Falling
2.4
-50 -30 -10 10 30 50 70 90 110 130
91.0%
112%
1.05
90.5%
111%
1.00
90.0%
110%
89.5%
109%
89.0%
-50 -30 -10 10 30 50 70 90110130
108%
-50 -30 -10 10 30 50 70 90110130
85.0%
120%
801.0
84.5%
119%
1.10
Rising
0.95
Falling
0.90
-50 -30 -10 10 30 50 70 90 110130
800.5
800.0
799.5
84.0%
118%
83.5%
117%
83.0%
-50 -30 -10 10 30 50 70 90110130
116%
-50 -30 -10 10 30 50 70 90 110130
799.0
798.5
798.0
797.5
MPQ9841 Rev.1.02
5/10/2019
797.0
-50 -30 -10 10 30 50 70 90 110 130
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7
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 5V, Io=1A, L = 4.7μH, FSW = 450kHz, with EMI filters, TA = +25°C, unless
otherwise noted. (7)
CISPR25 Class 5 Peak Conducted Emissions CISPR25 Class 5 Average Conducted Emissions
150kHz -108MHz
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
-5
-10
-15
-20
150kHz - 108MHz
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
-5
-10
-15
-20
CISPR25 CLASS 5 LIMITS
PEAK CONDUCTED EMI (dBuV)
AVERAGE CONDUCTED EMI (dBuV)
CISPR25 CLASS 5 LIMITS
NOISE FLOOR
Frequency (MHz)
1
0.1
10
108
NOISE FLOOR
Frequency (MHz)
1
0.1
10
108
CISPR25 Class 5 Peak Radiated Emissions
CISPR25 Class 5 Average Radiated Emissions
150kHz-30MHz
150kHz-30MHz
60
60
55
55
CISPR25 CLASS 5 LIMITS
50
AVERAGE RADIATED EMI (dBuV/m)
PEAK RADIATED EMI (dBuV/m)
50
45
40
35
30
25
20
15
10
NOISE FLOOR
5
45
40
35
CISPR25 CLASS 5 LIMITS
30
25
20
15
10
5
0
0
-5
-5
-10
-10
1
0.1
Frequency (MHz)
10
30
NOISE FLOOR
1
0.1
Frequency (MHz)
10
30
CISPR25 Class 5 Peak Radiated Emissions
CISPR25 Class 5 Average Radiated Emissions
Horizontal, 30MHz-200MHz
Horizontal, 30MHz-200MHz
55
55
HORIZONTAL POLARIZATION
PEAK RADIATED EMI (dBuV/m)
45
CISPR25 CLASS 5 LIMITS
40
35
30
25
20
15
10
5
HORIZONTAL POLARIZATION
50
AVERAGE RADIATED EMI (dBuV/m)
50
NOISE FLOOR
45
40
35
30
25
CISPR25 CLASS 5 LIMITS
20
15
10
5
0
0
-5
30
40
50
60
MPQ9841 Rev.1.02
5/10/2019
70
80
90
100 110 120
Frequency (MHz)
130
140
150
160
170
180
190
200
-5
NOISE FLOOR
30
40
50
60
70
80
90
100 110 120
Frequency (MHz)
130
140
150
160
170
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180
190
200
8
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 5V, Io=1A, L = 4.7μH, FSW = 450kHz, with EMI filters, TA = +25°C, unless
otherwise noted. (7)
CISPR25 Class 5 Peak Radiated Emissions
CISPR25 Class 5 Average Radiated Emissions
Vertical, 30MHz-200MHz
55
CISPR25 CLASS 5 LIMITS
40
35
30
25
20
15
10
5
VERTICAL POLARIZATION
50
45
AVERAGE RADIATED EMI (dBuV/m)
PEAK RADIATED EMI (dBuV/m)
55
VERTICAL POLARIZATION
50
45
Vertical, 30MHz-200MHz
40
35
30
25
CISPR25 CLASS 5 LIMITS
20
15
10
NOISE FLOOR
5
0
0
-5
30
40
50
60
70
80
90
100 110 120
Frequency (MHz)
130
140
150
160
170
180
190
NOISE FLOOR
-5
200
30
40
50
60
70
80
90
100 110 120
Frequency (MHz)
130
140
150
160
170
180
190
200
CISPR25 Class 5 Peak Radiated Emissions
CISPR25 Class 5 Average Radiated Emissions
Horizontal, 200MHz-1GHz
Horizontal,200MHz-1GHz
55
55
HORIZONTAL POLARIZATION
50
AVERAGE RADIATED EMI (dBuV/m)
PEAK RADIATED EMI (dBuV/m)
45
40
CISPR25 CLASS 5 LIMITS
35
30
25
20
15
10
NOISE FLOOR
5
HORIZONTAL POLARIZATION
50
45
40
35
30
25
CISPR25 CLASS 5 LIMITS
20
15
10
5
0
0
-5
200
300
400
500
600
Frequency (MHz)
700
800
900
NOISE FLOOR
-5
1000
200
300
400
500
600
Frequency (MHz)
700
800
900
1000
CISPR25 Class 5 Peak Radiated Emissions
CISPR25 Class 5 Average Radiated Emissions
Vertical, 200MHz-1GHz
Vertical,200MHz-1GHz
55
55
VERTICAL POLARIZATION
50
AVERAGE RADIATED EMI (dBuV/m)
PEAK RADIATED EMI (dBuV/m)
45
CISPR25 CLASS 5 LIMITS
40
35
30
25
20
15
10
NOISE FLOOR
5
VERTICAL POLARIZATION
50
45
40
35
30
25
CISPR25 CLASS 5 LIMITS
20
15
10
5
0
0
-5
200
300
400
500
600
Frequency (MHz)
700
800
900
1000
NOISE FLOOR
-5
200
300
400
500
600
Frequency (MHz)
700
800
900
1000
NOTE:
7) The EMC test results are based on the application circuit with EMI filters as shown in Figure14.
MPQ9841 Rev.1.02
5/10/2019
www.MonolithicPower.com
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© 2019 MPS. All Rights Reserved.
9
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL PERFORMANCE CHARACTERISTICS(continued)
VIN=12V, VOUT=3.3V, L=10µH, FSW=500kHz, AAM, TA=+25oC, unless otherwise noted.
3.5
3,000
5.0
3.0
2,500
4.5
2,000
4.0
1,500
3.5
1,000
3.0
500
2.5
2.5
2.0
1.5
1.0
0 10 20 30 40 50 60 70 80 90 100
0.05
0.04
0
0
200
400
600
800
1,000
0.2
0.4
0.6
0.8
1
2.0
0.0
0.2
0.4
0.6
0.8
1.0
0.10
0.03
0.05
0.02
0.01
0.00
0.00
-0.01
-0.02
-0.05
-0.03
-0.04
-0.05
0
5
10 15 20 25 30 35 40
MPQ9841 Rev.1.02
5/10/2019
-0.10
0
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10
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=12V, VOUT=3.3V, L=10µH, FSW=500kHz, AAM, TA=+25oC, unless otherwise noted.
MPQ9841 Rev.1.02
5/10/2019
www.MonolithicPower.com
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© 2019 MPS. All Rights Reserved.
11
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=12V, VOUT=3.3V, L=10µH, FSW=500kHz, AAM, TA=+25oC, unless otherwise noted.
30
30
25
25
20
20
15
15
10
10
5
5
0
0.0
0.2
0.4
0.6
0.8
1.0
0
5
0.0
0.2
0.4
0.6
0.8
1.0
0
0.0
30
30
30
25
25
25
20
20
20
15
15
15
10
10
10
5
5
5
0
0.0
0.2
MPQ9841 Rev.1.02
5/10/2019
0.4
0.6
0.8
1.0
0
0.0
0.2
0.4
0.6
0.8
1.0
0
0.0
0.2
0.4
0.6
0.8
1.0
0.2
0.4
0.6
0.8
1.0
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12
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=12V, VOUT=3.3V, L=10µH, FSW=500kHz, AAM, TA=+25oC, unless otherwise noted.
VOUT/AC
10mV/div.
VOUT/AC
50mV/div.
VSW
10V/div.
VOUT/AC
5mV/div.
IL
200mA/div.
IL
500mA/div.
IL
500mA/div.
VSW
5V/div.
VIN
VSW
5V/div.
VIN
VIN
VIN
5V/div.
VIN
5V/div.
VIN
5V/div.
VOUT
2V/div.
IL
1A/div.
VOUT
2V/div.
VSW
5V/div.
IL
200mA/div.
VOUT
2V/di v.
IL
500mA/div.
VSW
5V/div.
VSW
10V/div.
VEN
2V/div.
VOUT
2V/div.
VEN
2V/div.
VOUT
2V/div.
VIN
VIN
5V/div.
VOUT
2V/div.
IL
1A/div.
VSW
5V/div.
MPQ9841 Rev.1.02
5/10/2019
IL
200mA/div.
VSW
10V/div.
IL
1A/div.
VSW
10V/div.
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13
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=12V, VOUT=3.3V, L=10µH, FSW=500kHz, AAM, TA=+25oC, unless otherwise noted.
MPQ9841 Rev.1.02
5/10/2019
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14
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=12V, VOUT=3.3V, L=10µH, FSW=500kHz, AAM, TA=+25oC, unless otherwise noted.
3.3V
4V
VSW
20V/div.
MPQ9841 Rev.1.02
5/10/2019
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MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
PIN FUNCTIONS
Pin #
Name
1
PHASE
2
VIN
3, 10
SW
4, 9
PGND
5
EN
6
SYNC
7
PG
8
BIAS
11
BST
12
VCC
13
AGND
14
15
16
Description
Selectable in-phase or 180° out-of-phase of SYNC input. Drive PHASE high to be inphase. Drive PHASE low to be 180° out-of-phase. Recommend to connect this pin
to GND if not used.
Input supply. VIN supplies power to all of the internal control circuitries and the power
switch connected to SW. A decoupling capacitor to ground must be placed close to VIN to
minimize switching spikes.
Switch node. SW is the output of the internal power switch. Pin 3 and Pin 10 are
internally connected.
Power ground. PGND is the reference ground of the power device and requires careful
consideration during PCB layout. For best results, connect PGND with copper pours and
vias.
Enable. Pull EN below the specified threshold to shut the chip down. Pull EN above the
specified threshold to enable the chip.
Synchronize. Apply a 350kHz to 2.5MHz clock signal to SYNC to synchronize the internal
oscillator frequency to the external clock. The external clock should be at least 250kHz
larger than the RFREQ set frequency. SYNC can also be used to select forced continuous
conduction mode (CCM) or advanced asynchronous mode (AAM). Before the chip starts
up, drive SYNC low or leave SYNC floating to choose AAM, and drive SYNC high to
external power source or pull up SYNC to VCC directly to set the part forced CCM mode.
Power good indicator. The output of PG is an open drain and goes high if the output
voltage is within ±10% of the nominal voltage. Float PG if not used.
External power supply for the internal regulator. Connect BIAS to an external power
supply (5V ≤ VBIAS ≤ 18V) to reduce power dissipation and increase efficiency. Float BIAS
or connect BIAS to ground if not used.
Bootstrap. BST is the positive power supply for the high-side MOSFET driver connected
to SW. Connect a bypass capacitor between BST and SW.
Internal bias supply. VCC supplies power to the internal control circuit and gate drivers.
A ≥1µF decoupling capacitor to ground is required close to VCC.
Analog ground. AGND is the reference ground of the logic circuit.
Optional external soft-start time setting. Connect an external capacitor between this pin
and GND to set soft-start time externally. The MPQ9841 sources 10µA from SS to the
SS
soft-start capacitor during start-up. As the SS voltage rises, the feedback threshold voltage
increases to limit inrush current during start-up. Floating the pin will activate the internal
0.7ms soft-start setting.
Feedback input for output adjustable version. Connect FB to the tap of an external
resistor divider from the output to AGND to set the output voltage. The feedback threshold
voltage is 0.8V. Place the resistor divider as close to FB as possible. Avoid placing vias on
FB VOUT
the FB traces.
Regulated output voltage for fixed output version. Connect VOUT pin to the output
directly.
Switching frequency program. Connect a resistor from FREQ to ground to set the
FREQ
switching frequency.
MPQ9841 Rev.1.02
5/10/2019
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MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
BLOCK DIAGRAM
Figure 1-1: Functional Block Diagram of Output Adjustable Version
BIAS
VCC
VCC
VCC
Regulator
VIN
VCC
EN
VREF
Reference
FREQ
BST
Oscillator
PLL
SYNC
ISW
PHASE
+
-
PG
Logic
+
-
VFB
110%xVREF
90%xVREF
VFB
Error Amplifier
SS
VOUT
AGND
SSI
VREF
+
VSSI
R2
R3
360kΩ
+
VFB -
Control Logic,
OCP,
OTP,
BST Refresh
SW
VCC
VCOMP
R1
460kΩ
C1
52pF
C2
0.2pF
IREVERSE
PGND
Figure 1-2: Functional Block Diagram of Fixed Output Version
MPQ9841 Rev.1.02
5/10/2019
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MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
OPERATION
The MPQ9841 is a synchronous, step-down,
switching regulator with integrated, internal,
high-side and low-side power MOSFETs. The
MPQ9841 provides 1A of highly efficient output
current with current mode control.
The MPQ9841 features a wide input voltage
range, switching frequency programmable from
350kHz to 2.5MHz, external soft start, and
precision current limit. Its very low operational
quiescent current makes it suitable for batterypowered applications.
Pulse-Width Modulation (PWM) Control
At moderate-to-high output currents, the
MPQ9841 operates in a fixed-frequency, peakcurrent-control mode to regulate the output
voltage. A pulse-width modulation (PWM) cycle
is initiated by the internal clock. At the rising
edge of the clock, the high-side power
MOSFET (HS-FET) is turned on and remains
on until its current reaches the value set by the
COMP voltage (VCOMP). If the current in the HSFET does not reach VCOMP in one PWM period,
the HS-FET remains on, saving a turn-off
operation.
When the high-side power switch is off, the lowside MOSFET (LS-FET) is turned on
immediately and remains on until the next cycle
begins.
For each turn-on and -off in a switching cycle,
the HS-FET turns on and off with a minimum on
and off time limit.
Advanced Asynchronous Mode (AAM)
The
MPQ9841
employs
advanced
asynchronous mode (AAM) functionality to
optimize efficiency during light-load or no-load
conditions. AAM can be enabled by connecting
SYNC to a low level (1.8V) before start-up. SYNC can be
used to synchronize switching again after startup.
If continuous conduction mode (CCM) is
enabled, the device is forced to work with a
fixed frequency regardless of the output load
current. The advantage of CCM is the
controllable frequency and smaller output ripple,
MPQ9841 Rev.1.02
5/10/2019
but it also has low efficiency at light load (see
Figure 2).
If AAM is enabled, the MPQ9841 first enters
non-synchronous operation for as long as the
inductor current is approaching zero at light
load. If the load is further decreased or is at no
load, VCOMP drops below the AAM voltage
(VAAM), making the MPQ9841 enter power-save
mode (PSM). This puts the chip into sleep
mode, which consumes very low quiescent
current to further improve light-load efficiency.
In PSM, the internal clock is reset whenever
VCOMP crosses over VAAM, and the crossover
time is taken as the benchmark of the next
clock. When the load increases, and the DC
value of VCOMP is higher than VAAM, the
operation mode is discontinuous conduction
mode (DCM) or CCM, which have a constant
switching frequency.
Figure 2 : AAM and Forced CCM
Error Amplifier (EA)
The error amplifier (EA) compares the FB
voltage with the internal reference (0.8V) and
outputs a current proportional to the difference
between the two. This output current is used to
charge or discharge the internal compensation
network to form VCOMP, which is used to control
the power MOSFET current. The optimized
internal compensation network minimizes the
external component count and simplifies the
control loop design.
Bootstrap Charging
The bootstrap capacitor (0.1µF to 1µF) is
charged and regulated to about 5V by the
dedicated internal bootstrap regulator. When
the voltage between the BST and SW nodes is
lower than its regulation, a PMOS pass
transistor connected from VIN to BST is turned
on. The charging current path is from VIN to
BST to SW. An external circuit should provide
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MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
enough voltage headroom to facilitate charging.
When the HS-FET is on, VIN is about equal to
SW, so the bootstrap capacitor cannot be
charged.
At a higher duty cycle operation condition, the
time period available to the bootstrap charging
is less, so the bootstrap capacitor may not be
charged sufficiently. In case the external circuit
does not have sufficient voltage or time to
charge the bootstrap capacitor, extra external
circuitry can be used to ensure that the
bootstrap voltage is in the normal operation
region.
Low Dropout Operation (BST Refresh)
To improve drop out, the MPQ9841 is designed
to operate at close to 100% duty cycle for as
long as the BST to SW voltage is greater than
2.5V. When the voltage from BST to SW drops
below 2.5V, the HS-FET is turned off using an
under-voltage lockout (UVLO) circuit, which
allows the LS-FET to conduct and refresh the
charge on the BST capacitor. In DCM or PSM,
the LS-FET is forced on to refresh the BST
voltage.
Since the supply current sourced from the BST
capacitor is low, the HS-FET can remain on for
more switching cycles than are required to
refresh the capacitor, making the effective duty
cycle of the switching regulator high.
The effective duty cycle during the dropout of
the regulator is mainly influenced by the voltage
drops across the power MOSFET, inductor
resistance, low-side diode, and printed circuit
board resistance.
Internal Regulator
Most of the internal circuitry is powered on by
the 5V internal regulator. This regulator takes
the VIN input and operates in the full VIN range.
When VIN is greater than 5V, the output of the
regulator is in full regulation. When VIN is lower
than 5V, the output degrades.
For better thermal performance, connect BIAS
to an external 5V source. VCC and the internal
circuit are powered by BIAS. Since there is an
internal diode between BIAS and the internal
circuit, float BIAS or connect BIAS to GND if it
is not being used.
MPQ9841 Rev.1.02
5/10/2019
Enable Control (EN)
EN is a digital control pin that turns the
regulator on and off. When EN is pulled below
its threshold voltage, the chip is put into the
lowest shutdown current mode. Pulling EN
above its threshold voltage turns on the part.
Do not float EN.
Frequency Programmable (FREQ)
The MPQ9841 oscillating frequency can be
programmed either by an external resistor
(RFREQ) from FREQ to ground or by a logic level
SYNC signal. The value of (RFREQ) can be
calculated with Equation (1):
R FREQ (kΩ )
170000
fs
1.11
(1)
(kHz )
The chip can be synchronized to an external
clock ranging from 350kHz up to 2.5MHz
through FREQ/SYNC.
SYNC and PHASE
The internal oscillator frequency can be
synchronized to an external clock ranging from
350kHz up to 2.5MHz through SYNC. The
external clock should be at least 250kHz larger
than the RFREQ set frequency. Ensure that the
high amplitude of the SYNC clock is higher than
1.8V, and the low amplitude is lower than 0.4V.
There is no pulse width requirement, but there
is always parasitic capacitance of the pad, so if
the pulse width is too short, a clear rising and
falling edge may not be seen due to the
parasitic capacitance. A pulse longer than
100ns is recommended in application.
PHASE is used when two or more MPQ9841
devices are in parallel with the same SYNC
clock. Pulling PHASE high forces the MPQ9841
to operate in-phase of the SYNC clock. Pulling
PHASE low forces the device to be 180° out-ofphase of the SYNC clock. By setting different
voltages for PHASE, two devices can operate
180° out-of-phase to reduce the total input
current ripple, so a smaller input bypass
capacitor can be used (see Figure 3). The
PHASE rising threshold is about 2.5V with a
400mV hysteresis.
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MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
silicon die temperature is higher than its upper
threshold, the power MOSFETs are shut down.
When the temperature is lower than its lower
threshold, thermal shutdown is removed and
the chip is enabled again.
Figure 3: In-Phase and 180° Out-of-Phase
Soft Start (SS)
Soft start (SS) is implemented to prevent the
converter output voltage from overshooting
during start-up. When the chip starts up, an
internal current source begins charging the
external soft-start capacitor. The internal SS
voltage (VSSI) rises with the soft-start voltage
(VSS), but VSSI is a little different with VSS due to
a 0.5V offset and some delay. When VSS is
lower than 0.5V, VSSI is 0V. VSSI rises from 0V to
0.8V during the period of VSS rising from 0.5V to
1.6V. At this time the error amplifier uses VSSI
as the reference, so the output voltage ramps
up from 0V to the regulated value following VSSI
rising. When VSS reaches 1.6V, VSSI is 0.8V and
overrides the internal VREF, so the error
amplifier uses the internal VREF as the reference.
The soft-start time (tSS) set by the external SS
capacitor can be calculated with Equation (2):
t SS (ms)
CSS (nF) 1.1V
ISS (A)
(2)
Where CSS is the external SS capacitor, and ISS
is the internal 10μA SS charge current.
There is also an internal fixed 700us soft start.
The final SS time is determined by the longer
time between 700us and the external SS setting
time.
SS can be used for tracking and sequencing.
Pre-Bias Start-Up
At start-up, if VFB is higher than VSSI-150mV,
which means the output has a pre-bias voltage,
neither the HS-FET nor the LS-FET are turned
on until VSSI-150mV is higher than VFB.
Thermal Shutdown
Thermal shutdown is implemented to prevent
the chip from running away thermally. When the
MPQ9841 Rev. 1.0
5/10/2019
Current Comparator and Current Limit
The power MOSFET current is accurately
sensed via a current sense MOSFET. The
current is then fed to the high-speed current
comparator for current-mode control purposes.
The current comparator takes this sensed
current as one of its inputs. When the HS-FET
is turned on, the comparator is first blanked
until the end of the turn-on transition to avoid
noise. Then the comparator compares the
power switch current with VCOMP. When the
sensed current is higher than VCOMP, the
comparator outputs low to turn off the HS-FET.
The maximum current of the internal power
MOSFET is limited cycle-by-cycle internally.
Hiccup Protection
When the output is shorted to ground, causing
the output voltage to drop below 55% of its
nominal output, the IC is shut down
momentarily and begins discharging the softstart capacitor. The IC restarts with a full soft
start when the soft-start capacitor is fully
discharged. This hiccup process is repeated
until the fault is removed.
Start-Up and Shutdown
If both VIN and EN are higher than their
appropriate thresholds, the chip starts up. The
reference block starts first, generating a stable
reference voltage and current, and then the
internal regulator is enabled. The regulator
provides a stable supply for the rest of the
circuitries.
While the internal supply rail is up, an internal
timer holds the power MOSFET off for about
50µs to blank any start-up glitches. When the
soft-start block is enabled, the SS output is held
low to ensure that the rest of the circuitries are
ready before slowly ramping up.
Three events can shut down the chip: EN low,
VIN low, and thermal shutdown. In the
shutdown procedure, the signaling path is
blocked first to avoid any fault triggering. VCOMP
and the internal supply rail are then pulled down.
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MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
The floating driver is not subject to this
shutdown command, but its charging path is
disabled.
Power Good (PG) Output
The MPQ9841 includes an open-drain power
good (PG) output that indicates whether the
regulator output is within ±10% of its nominal
output range. When the output voltage moves
outside of this range, the PG output is pulled to
ground.
MPQ9841 Rev. 1.0
5/10/2019
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MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
APPLICATION INFORMATION
Setting the Output Voltage
The external resistor divider connected to FB
sets the output voltage (see Figure 4).
Where ∆IL is the peak-to-peak inductor ripple
current.
Choose the inductor ripple current to be
approximately 30% of the maximum load
current. The maximum inductor peak current
can be calculated with Equation (5):
ILP ILOAD
Figure 4: Feedback Network
Choose RFB1 first, RFB2 can then be calculated
with Equation (3):
R FB2
R FB1
VOUT
1
0.8V
(3)
Table 1 lists the recommended feedback
resistor values for common output voltages.
Table 1: Resistor Selection for Common Output
Voltages
VOUT (V)
3.3
5
RFB1 (kΩ)
41.2 (1%)
68.1 (1%)
RFB2 (kΩ)
13 (1%)
13 (1%)
For fixed output version, connect VOUT pin to
the output directly.
Selecting the Inductor
A 1µH to 10µH inductor with a DC current rating
at least 25% higher than the maximum load
current is recommended for most applications.
For higher efficiency, choose an inductor with a
lower DC resistance. A larger-value inductor
results in less ripple current and a lower output
ripple voltage, but also has a larger physical
size, higher series resistance, and lower
saturation current. A good rule for determining
the inductor value is to allow the inductor ripple
current to be approximately 30% of the
maximum load current. The inductance value
can then be calculated with Equation (4):
L
MPQ9841 Rev.1.02
5/10/2019
VOUT
V
(1 OUT )
fSW IL
VIN
(4)
VOUT
V
(1 OUT )
2fSW L
VIN
(5)
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous and therefore requires a
capacitor to supply AC current to the converter
while maintaining the DC input voltage. For the
best performance, use low ESR capacitors.
Ceramic capacitors with X5R or X7R dielectrics
are highly recommended because of their low
ESR and small temperature coefficients.
For most application, use a 4.7µF to 10µF
capacitor. It is strongly recommended to use
another lower-value capacitor (e.g.: 0.1µF) with
a small package size (0603) to absorb highfrequency switching noise. Place the smaller
capacitor as close to VIN and GND as possible.
Since CIN absorbs the input switching current, it
requires an adequate ripple current rating. The
RMS current in the input capacitor can be
estimated with Equation (6):
ICIN ILOAD
VOUT
V
(1 OUT )
VIN
VIN
(6)
The worst-case condition occurs at VIN = 2VOUT,
shown in Equation (7):
ICIN
ILOAD
2
(7)
For simplification, choose an input capacitor
with an RMS current rating greater than half of
the maximum load current.
The input capacitor can be electrolytic, tantalum,
or ceramic. When using electrolytic or tantalum
capacitors, add a small, high-quality ceramic
capacitor (e.g.: 0.1μF) as close to the IC as
possible. When using ceramic capacitors,
ensure that they have enough capacitance to
provide a sufficient charge to prevent excessive
voltage ripple at the input.
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MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
The input voltage ripple caused by the
capacitance can be estimated with Equation (8):
I
V
V
VIN LOAD OUT (1 OUT )
fSW CIN VIN
VIN
VIN
VIN
RUP
EN
(8)
RDOWN
Selecting the Output Capacitor
The output capacitor maintains the DC output
voltage. Ceramic, tantalum, or low ESR
electrolytic capacitors are recommended. For
best results, use low ESR capacitors to keep
the output voltage ripple low. The output
voltage ripple can be estimated with Equation
(9):
V
V
1
) (9)
VOUT OUT (1 OUT ) (RESR
fSW L
VIN
8fSW COUT
Figure 5: Adjustable UVLO Using EN Divider
The UVLO threshold can be calculated with
Equation (12) and Equation (13):
INUVRISING (1
R UP
) VEN_RISING
R DOWN
(12)
INUVFALLING (1
R UP
) VEN_FALLING
R DOWN
(13)
Where L is the inductor value, and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
Where VEN_RISING is 1.05V, and VEN_FALLING is
0.93V.
For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency and causes the majority of the output
voltage ripple. For simplification, the output
voltage ripple can be estimated with Equation
(10):
External BST Diode and Resistor
An external BST diode can enhance the
efficiency of the regulator when the duty cycle is
high. A power supply between 2.5V and 5V can
be used to power the external bootstrap diode.
VCC or VOUT is recommended to be the power
supply in the circuit (see Figure 6).
VOUT
VOUT
V
(1 OUT )
8 fSW L COUT
VIN
2
(10)
For tantalum or electrolytic capacitors, the ESR
dominates the impedance at the switching
frequency. For simplification, the output ripple
can be approximated with Equation (11):
VOUT
VOUT
V
(1 OUT ) RESR
fSW L
VIN
(11)
The characteristics of the output capacitor also
affect the stability of the regulation system. The
MPQ9841 can be optimized for a wide range of
capacitance and ESR values.
VIN UVLO Setting
The MPQ9841 has an internal, fixed, UVLO
threshold. The rising threshold is 2.8V, while
the falling threshold is about 2.65V. For
applications that require a higher UVLO point,
an external resistor divider between VIN and
EN can be used to achieve a higher equivalent
UVLO threshold (see Figure 5).
MPQ9841 Rev.1.02
5/10/2019
Figure 6: External Bootstrap Diode and Resistor
The recommended external BST diode is
IN4148, and the recommended BST capacitor
value is 0.1µF to 1μF.
A resistor in series with the BST capacitor (RBST)
can reduce the SW rising rate and voltage
spikes. This helps enhance EMI performance
and reduce voltage stress at a high VIN. A
higher resistance is better for SW spike
reduction but compromises efficiency. To make
a tradeoff between EMI and efficiency, a ≤20Ω
RBST is recommended.
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MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
PCB Layout Guidelines (8)
Efficient PCB layout is critical for stable operation,
especially for the input capacitor placement. A
four-layer layout is strongly recommended to
achieve better thermal performance. For best
results, refer to Figure 7 and follow the guidelines
below.
1.
Use a large ground plane to connect directly
to PGND. Recommend to connect pin1 to
GND for symmetric input structure if in-phase
not used. Pin3 and pin10 are internally
connected. Connecting together on layout or
not are both OK. Recommend to leave pin3
floating for shorter pin4 and pin1 trace and
smaller input hot loop.
2.
Add vias near PGND if the bottom layer is a
ground plane.
3.
Ensure that the high-current paths at GND
and VIN have short, direct, and wide traces.
4.
Place the ceramic input capacitors,
especially the small package size (0603)
input bypass capacitor, as close to VIN and
PGND as possible to minimize highfrequency noise.
5.
Keep the connection of the input capacitor
and VIN as short and wide as possible.
6.
Place the VCC capacitor as close to VCC
and GND as possible.
7.
Route SW and BST away from sensitive
analog areas such as FB.
8.
Place the feedback resistors close to the
chip to ensure that the trace connecting to
FB is as short as possible.
9.
Use multiple vias to connect the power
planes to the internal layers.
Top Layer
Inner Layer 1
Inner Layer 2
NOTE:
8) The recommended PCB layout is based on Figure 8.
Bottom Layer
Figure 7: Recommended PCB Layout
MPQ9841 Rev.1.02
5/10/2019
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MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
13
4, 9
TYPICAL APPLICATION CIRCUITS
Figure 8: VOUT = 3.3V, FSW = 500kHz
U1
VIN
3.3V-36V
GND
2
C1A
10μF
R1
100kΩ
C1B
10μF
C1C C1D
0.1μF 0.1μF
5
EN
VIN
BST
EN
SW
11
C5
0.1μF
L1
3, 10
R3
68.1kΩ
12
R5
100kΩ
PG
VCC
FB
C4
1μF
C6
10pF
C2A C2B
22μF 22μF
VOUT
GND
15
R4
13kΩ
7
PG
SS
14
C3
4.7nF
SYNC
5V/1A
10μH
6
SYNC
FREQ
R6
10Ω
16
R2
169kΩ
PHASE
BIAS
PGND
AGND
13
1
4, 9
PHASE
8
C7
0.1µF
Figure 9: VOUT = 5V, FSW = 500kHz
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5/10/2019
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MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL APPLICATION CIRCUITS (continued)
Figure 10: VOUT = 3.3V, FSW = 2.2MHz
Figure 11: VOUT = 5V, FSW = 2.2MHz
MPQ9841 Rev.1.02
5/10/2019
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26
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
TYPICAL APPLICATION CIRCUITS (continued)
Figure 12: VOUT = 3.3V, FSW = 500kHz for Big FB Resistor Divider Application
Figure 13: VOUT = 3.3V, FSW = 2.2MHz for Big FB Resistor Divider Application
MPQ9841 Rev.1.02
5/10/2019
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
27
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
Figure 14: Application Circuit with EMI Filter @VOUT = 5V/1A, FSW = 450kHz
U1
VIN
GND
3.3V-36V
2
C1A
10μF
R1
100kΩ
C1B
10μF
C1C C1D
0.1μF 0.1μF
5
EN
12
R5
100kΩ
PG
VIN
BST
C5
0.1μF
L1
MPQ9841
EN
SW
3, 10
VOUT
6
C2A C2B
22μF 22μF
VOUT
PG
SS
15
14
C3
4.7nF
SYNC
3.3V/1A
10μH
GND
VCC
C4
1μF
7
11
SYNC
FREQ
R6
NS
16
R2
169kΩ
PHASE
BIAS
PGND
AGND
13
1
4, 9
PHASE
8
C7
NS
Figure 15: 3.3V Fixed Output, FSW = 500kHz
MPQ9841 Rev. 1.0
5/10/2019
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
28
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
U1
VIN
3.3V-36V
GND
2
C1A
10μF
R1
100kΩ
C1B
10μF
C1C C1D
0.1μF 0.1μF
5
EN
12
R5
100kΩ
PG
VIN
BST
C5
0.1μF
L1
MPQ9841
EN
SW
3, 10
VOUT
6
C2A C2B
22μF 22μF
VOUT
PG
SS
15
14
C3
4.7nF
SYNC
5V/1A
10μH
GND
VCC
C4
1μF
7
11
SYNC
FREQ
R6
10Ω
16
R2
169kΩ
PHASE
BIAS
PGND
AGND
13
1
4, 9
PHASE
8
C7
0.1µF
Figure 16: 5V Fixed Output, FSW = 500kHz
MPQ9841 Rev.1.02
5/10/2019
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
29
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
PACKAGE INFORMATION
QFN-16 (3mmx4mm)
Non-Wettable Flank
MPQ9841 Rev.1.02
5/10/2019
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
30
MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
PACKAGE INFORMATION (continued)
QFN-16 (3mmx4mm)
Wettable Flank
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MPQ9841 Rev.1.02
5/10/2019
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
31
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