NB650A
High-Effeciency, Fast-Transient, 6A, 28V
Synchronous Step-Down Converters with 2-Bit VID
DESCRIPTION
FEATURES
The NB650A is fully-integrated, high-frequency,
synchronous, rectified, step-down, switch-mode
converters with dynamic-output–voltage control.
It offers a very compact solution to achieve 6A
of continuous output current over a wide input
supply range, and has excellent load and line
regulation. The NB650A operates at high
efficiency over a wide output-current–load
range.
Constant-On-Time control mode provides fast
transient response and eases loop stabilization.
2-bit VID inputs support changing the output
voltage on-the-fly.
Full protection features include short-circuit
protection, over-current protection, over-voltage
protection, under-voltage protection, and
thermal shut down.
The NB650A requires a minimal number of
readily-available standard external components,
and is available in a space-saving 3mm×4mm
QFN17 package.
Wide 4.5V-to-28V Operating Input Range
6A Output Current
Internal 50mΩ High-Side, 18mΩ Low-Side
Power MOSFETs
Proprietary Switching Loss Reduction
Technique
1% Reference Voltage
Programmable Soft-Start Time
2-bit VID Input
Soft Shutdown
Frequency Programmable from 150kHz to
1MHz
SCP, OCP, OVP, UVP, and Thermal
Shutdown
Optional OCP Protection: Latch-Off Mode
Output Adjustable from 0.6V to 13V
Available in QFN17 (3mm×4mm) Package
APPLICATIONS
Notebook Systems and I/O Power
Networking Systems
Digital Set Top Boxes
Flat-Panel Televisions and Monitors
Distributed Power Systems
All MPS parts are lead-free, halogen free, and adhere to the RoHS directive. For
MPS green status, please visit MPS website under Quality Assurance. “MPS”
and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION （FOR NOTEBOOK）
NB650A Rev. 1.02
6/21/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
1
NB650A – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
ORDERING INFORMATION
Part Number
Package
Top Marking
NB650AGL*
QFN17 (3mmx4mm)
See Below
* For Tape & Reel, add suffix –Z (e.g. NB650AGL–Z).
TOP MARKING
NB650A: part number
Y: year code
W: week code
LLL: lot number
PACKAGE REFERENCE
TOP VIEW
SW
SW
FREQ
SS
17
16
1
15
14
13
AGND
12
IN
11
IN
GND
10
GND
GND
9
GND
SW
2
3
RFB1 RFB2 FB
SW
4
5
6
7
8
BST PG EN VID1 VID2 VCC
EXPOSED PAD
ON BACKSIDE
QFN17 (3x4mm)
NB650A Rev. 1.02
6/21/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
2
NB650A – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VIN .......................................28V
VSW ....................................... -0.3V to VIN + 0.3V
VSW ............................. -3V to VIN + 3V for 200ns
RFREQ=200kΩ, VOUT=1.2V
Min
8
RFREQ=200kΩ
ILIM=1
ILIM=1
Typ
0
400
0
10
200
VFB = 600mV
VSS=0V
100
1.2
50
600
10
10
VSS=0.6V
10
594
Max
Units
1
μA
μA
μA
A
ns
606
100
0.4
2
VEN = 2V
VEN = 0V
1.5
0
0.8
0.4
ns
μs
μs
mV
nA
μA
μA
V
V
μA
V
V
0
mV
mV
μA
SRFB
±20
mV/μs
VIDRDS-ON
PGVth-Hi
PGVth-Lo
100
0.9
0.85
Ω
VFB
VFB
PGTd
VPG
0.5
12
ms
V
nA
μs
INUVVth
4
V
INUVHYS
800
mV
TSD
150
°C
IPG_LEAK
tSTANDBY
385
635
Sink 4mA
VPG = 3.3V
0.4
10
Note:
5) Not tested. Not guaranteed.
NB650A Rev. 1.02
6/21/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
4
NB650A – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
PIN FUNCTIONS
QFN17
Pin #
Name
1,2
SW
3
BST
4
PG
5
EN
6,7
VID1
VID2
8
VCC
9,10
GND
11
IN
12
AGND
13
FB
14,15
RFB2
RFB1
16
SS
17
FREQ
NB650A Rev. 1.02
6/21/2017
Description
Switch Output. Connect using wide PCB traces.
Bootstrap. Requires a capacitor between SW and BST to form a floating supply across
the high-side switch driver.
Power Good. Output is an open drain and is high if the output voltage exceeds 90% of
the nominal voltage. There is a delay from FB≥90%×Vref to PG goes high.
EN=1 to enable. For automatic start-up, connect to VIN with a 100kΩ resistor.
VID inputs. Control signals for the output-voltage scaling. Acts as the control signals for
the internal VID switches. Usually uses an external resistor in parallel with the low-side
FB resistor. Changing the VID ON/OFF state changes the FB divider scaling and result
in different output voltages. Use 100kohm resistor to pull-up the VID1 / VID2 pins.
Internal LDO output. The power supply of the internal control circuits. Decouple with 1μF
capacitor.
System Ground. The reference ground of the regulated output voltage. Layout requires
extra care.
Supply Voltage. Operates from a 4.5V-to-28V input rail. Requires C1 to decouple the
input rail. Connect using wide PCB traces.
Analog Ground.
Feedback. Connect to the tap of an external resistor divider from the output to GND to
set the output voltage.
Drain of the internal VID switches. Typically uses an external resistor in parallel with the
low-side FB resistor along with the internal VID switch to change the ON/OFF state of
the VID switching to change the FB divider scaling and result in different output
voltages.
Soft-Start. Connect an external capacitor to program the soft-start time for the switchmode regulator.
Frequency Set during CCM. The input voltage and the frequency-set resistor between
the IN and FREQ pin determines the ON period. For best results, use an ON period
longer than 200ns.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
5
NB650A – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
TYPICAL PERFORMANCE CHARACTERISTICS
VIN=12V, VOUT =1.05V, L=1µH, TA=+25°C, unless otherwise noted.
NB650A Rev. 1.02
6/21/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
6
NB650A – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=12V, VOUT =1.05V, L=1µH, TA=+25°C, unless otherwise noted.
NB650A Rev. 1.02
6/21/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
7
NB650A – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=12V, VOUT =1.05V, L=1µH, TA=+25°C, unless otherwise noted.
NB650A Rev. 1.02
6/21/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
8
NB650A – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
FUNCTIONAL BLOCK DIAGRAM
Figure 1: Functional Block Diagram
NB650A Rev. 1.02
6/21/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
9
NB650A – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
OPERATION
PWM Operation
The NB650A is a fully-integrated, synchronous,
rectified, step-down, switch-mode converter with
dynamic output voltage control. It offers a very
compact solution to achieve a 6A continuous
output current over a wide input supply range,
with excellent load and line regulation. The
NB650A operates at high efficiency over a wide
output current load range.
Constant-on-time (COT) provides a fast transient
response and easy loop stabilization. At the
beginning of each cycle, the high-side MOSFET
(HS-FET) turns on when the feedback voltage
(VFB) falls below the reference voltage (VREF),
which indicates an insufficient output voltage.
The input voltage and the frequency-set resistor
determine the ON as follows:
t ON (ns)
9.6 RFREQ (k)
tDELAY1(ns)
VIN (V) 0.4
(1)
Where tDELAY1 is the 20ns delay of a comparator
in the tON module.
For best results, select tON ≥120ns.
After the ON period elapses, the HS-FET turns
off to enter the OFF state. The part turns ON
again when VFB drops below VREF. By repeating
this operation, the converter regulates the output
voltage. The integrated low-side MOSFET (LSFET) turns on when the HS-FET is OFF to
minimize conduction loss. There is a dead short
between input and GND (shoot-through) if both
HS-FET and LS-FET turn on at the same time.
An internally-generated dead-time (DT) between
HS-FET OFF and LS-FET ON, or LS-FET OFF
and HS-FET OFF avoids shoot-through.
Figure 2: Heavy-Load Operation
Light-Load Operation
When the load current decreases, the NB650A
automatically reduces the switching frequency to
maintain high efficiency. Figure 3 shows the lightload operation. VFB does not reach VREF when the
inductor current approaches zero. As the output
current drops from heavy-load condition, the
inductor current also decreases and eventually
approaches zero. The LS-FET driver enters a tristate (high-Z) whenever the inductor current
reaches zero. A current modulator takes control
of the LS-FET and limits the inductor current to
less than 600μA to slowly discharge the output
capacitors to GND through LS-FET as well as R1
and R2A, R2B and R2C. The HS-FET does not
turn ON as frequently as in heavy-load condition.
As a result, the efficiency at light-load condition
increases greatly. This operation mode is also
called skip mode.
Heavy-Load Operation
As shown in Figure 2, the HS-FET and LS-FET
repeatedly turn on/off when the output current is
high, and the inductor current never goes to zero.
It’s called continuous-conduction-mode (CCM)
operation. In CCM operation, the switching
frequency (fSW) is fairly constant.
NB650A Rev. 1.02
6/21/2017
Figure 3: Light-Load Operation
As the output current increases from the lightload condition, the time period within which the
current modulator regulates becomes shorter.
As the part exits light-load mode, the HS-FET
turns on more frequently to increase the switching
frequency. The output current reaches critical
when the current modulator time is zero. The
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
10
NB650A – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
following equation determines the critical level of
the output current:
IOUT
(VIN VOUT ) VOUT
2 L fSW VIN
(2)
When the output current exceeds the critical level,
light load mode turns into PWM mode, and the
switching frequency stays fairly constant over the
output current range.
Switching Frequency
The NB650A uses constant-on-time (COT)
control, and has no dedicated internal oscillator.
The input voltage is feed-forwarded to the ontime one-shot timer through the resistor RFREQ.
The duty ratio is kept as VOUT/VIN. Hence, the
switching frequency is fairly constant over the
input voltage range. The switching frequency can
be set as follows:
9.6 R FREQ (k)
t DELAY1 (ns)
VIN ( V ) 0.4
f SW (kHz)
V (V)
IN
t DELAY2 (ns)
VOUT ( V )
Jitter and FB Ramp Slope
Figure 5 and Figure 6 show jitter in both PWM
and skip modes. When there is noise in the VFB
downward slope, the ON time of HS-FET
deviates from its intended level and produces
jitter. There is a relationship between a system’s
stability and the steepness of the VFB ripple’s
downward slope: The steepness of the VFB
ripple’s slope dominates in noise immunity. The
magnitude of the VFB ripple doesn’t directly affect
the noise immunity.
1
10 6
(3)
Figure 5: Jitter in PWM Mode
Where tDELAY2 is another comparator delay of
about 40ns.
Figure 6: Jitter in Skip Mode
Ramp with Large ESR Cap
When using POSCAPs or other types of
capacitors with larger ESR as output capacitors.
the ESR ripple dominates the output ripple, and
the slope on the FB is ESR-related. Figure 7
shows an equivalent circuit in PWM mode with
the HS-FET off and without an external ramp
circuit. The application section includes design
steps for large ESR capacitors.
Figure 4: Plot of VOUT as a Function of RFREQ and
the Frequency
NB650A is optimized to operate at high switching
frequencies at high efficiency. Higher switching
frequencies allow for smaller LC filter
components to reduce system PCB space.
NB650A Rev. 1.02
6/21/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
11
NB650A – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
And R2 is the equivalent resistor from FB to GND
that varies with VID input, the ramp on the VFB
can then be estimated as:
SW
L
Vo
ESR
R1
FB
VRAMP
POSCAP
R2
Figure 7: Simplified Circuit in PWM Mode without
External Ramp Compensation
To realize the stability without the use of an
external ramp, select an ESR value as follows:
RESR
t SW
t
ON
0.7 2
COUT
(4)
VRAMP
The ESR ripple when using ceramic output
capacitors is not high enough to stabilize the
system and requires an external compensation
ramp. The application section includes a
description of designing with small ESR
capacitors.
SW
R4
Vo
IC4
The downward slope of the VFB ripple then
follows
VOUT
VRAMP
t off
R 4 C4
(9)
As shown in equation 8, if there is instability in
PWM mode, we can reduce either R4 or C4. If
C4 can not be reduced further due to limitations
from equation 5, then we can only reduce R4.
For a stable PWM operation, the Vslope1 should be
designed as follows.
t SW
t
+ ON -RESRCOUT
Io 103
0.7
π
2
(10)
-Vslope1
VOUT +
2 L COUT
t SW -t on
Where IO is the load current.
R1
In skip mode, the downward slope of the VFB
ripple is almost the same with or without the
external ramp. Figure 9 shows the simplified
circuit of the skip mode when both HS-FET and
LS-FET are off.
I FB
Ceramic
FB
R2
Figure 8: Simplified Circuit in PWM Mode with
External Ramp Compensation
Figure 7 shows a simplified equivalent circuit in
PWM mode with the HS-FET OFF and an
external ramp compensation circuit (R4, C4). The
external ramp is derived from the inductor ripple
current. If one chooses C4, R9, R1 and R2 to
meet the following condition:
1
2 fSW C4
1 R1 R2
R9
5 R1 R2
(5)
Vo
FB
IR4 IC4 IFB IC4
(6)
R1
Cout
Ro
R2
Figure 9: Simplified Circuit in Skip Mode
The downward slope of the VFB ripple in skip
mode can be determined as:
Where:
NB650A Rev. 1.02
6/21/2017
(8)
C4
IR4
R9
( VIN VO ) ON
R4 C4
VSLOPE1
Ramp with Small ESR Capacitor
(7)
Usually R9 is set to 0Ω, then equation 7 can be
simplified as:
Where tSW is the switching period.
L
VIN VO
R1 // R2
t ON
R 4 C4
R1 // R2 R9
VSLOPE2
VREF
(R1 R2 // Ro) COUT
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
(11)
12
NB650A – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
Where RO is the equivalent load resistor.
As described in Figure 6, VSLOPE2 in skip mode is
smaller than VSLOPE1 in PWM mode, so the jitter in
the skip mode is larger. For less jitter during
ultra-light–load conditions, select smaller VFB
resistors, though at the cost of light-load
efficiency.
VID Input
Typically, R1 and R2 set the output voltage with
VFB=0.6V. R2, in this case, is a combination of
R2A, R2B, and R2C depends on the VID, which
is active low. The NB650A can dynamically track
VID codes as they change. As a result, the
converter output voltage can change without the
need to reset either the controller or the value of
R1 and R2A. As shown in Figure 1, R2B and
R2C are parallel with R2A. The equivalent value
of R2 can change due to different VID codes.
One can get four VOUT values depending on the
VID codes with the details in the application
information. The VID logic and equivalent R2s
are shown in Table 1.
Table 1: VID Logic
VID2
VID1
R2
1
1
R2 R2A
1
0
R2 R2A // R2B
0
1
R2 R2A // R2C
0
0
R2 R2A //R2B //R2C
Enable Control
The NB650A has a dedicated Enable control pin
(EN). Pulling this pin high or low enables or
disables the IC. Tie EN to VIN through a resistor
for automatic start-up.
Soft Start/Stop
The NB650A employs a soft-start/stop (SS)
mechanism to ensure smooth output during
power-up and power shutdown. When the EN pin
goes high, an internal current source (10μA)
charges up the SS capacitor. The SS capacitor
voltage then acts as the VREF voltage to the PWM
comparator. The output voltage smoothly ramps
up with the SS voltage. Once the SS voltage
reaches the same level as the REF voltage, it
continues ramping up while the REF voltage
NB650A Rev. 1.02
6/21/2017
becomes the reference to the PWM comparator.
At this point, the soft-start finishes and it enters
steady-state operation.
When the EN pin goes low, a 10µA internal
current source discharges the SS capacitor.
Once the SS voltage reaches the REF voltage,
acts as the reference to the PWM comparator.
The output voltage decreases smoothly with the
SS voltage until it reaches zero level. Determine
the SS capacitor as follows:
CSS (nF)
t SS (ms) ISS (A )
VREF ( V )
(12)
If the output capacitors have large capacitance
values, avoid setting a short SS time. Use a
minimum value of 4.7nF if the output capacitance
value exceeds 330µF.
Power Good
The NB650A has power-good (PG) output. The
PG pin is the open drain of a MOSFET. Connect
to VCC or another voltage source through a
resistor (e.g. 100kΩ). The MOSFET turns ON
after the application of the input voltage so that
the PG pin is pulled to GND before the SS is
ready. After the FB voltage reaches 90% of the
reference voltage, the PG pin is pulled high after
a delay.
The PG delay is determined as follows:
t PG (ms)
4 t SS (ms)
9
(13)
When the FB voltage drops to 90% of the
reference voltage, the PG pin is pulled low.
Over-Current Protection and Short-Circuit
Protection
The NB650A has cycle-by-cycle over-current limit
control. The inductor current is monitored during
the ON state. Once the inductor current hits the
current limit, the HS-FET turns off. At the same
time, the over-current protection (OCP) timer
starts. The OCP timer is set as 50μs. If the
current limit is hit for every cycle within that 50μs
period, then OCP will trigger.
When the output is shorted to ground, the device
hits its current limit and the FB voltage is less
than 0.4V. The device treats this as a dead-short
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
13
NB650A – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
on the output and triggers OCP immediately. This
is short circuit protection (SCP).
Under OCP/SCP condition, NB650A will latch off.
The converter needs power cycle to restart.
Over/Under-Voltage Protection
The NB650A monitors the output voltage through
the FB voltage to detect overvoltage and under
voltage on the output. When the FB voltage
exceeds 0.8V, the over-voltage protection (OVP)
triggers. Once OVP triggers, the LS-FET is
always on while the HS-FET is always off. The
device needs to power cycle to power up again.
Under-voltage protection (UVP) triggers when the
FB voltage is below 0.4V. Usually, UVP
accompanies hitting the current limit, which
results in SCP.
NB650A Rev. 1.02
6/21/2017
UVLO Protection
The NB650A has under-voltage lockout (UVLO)
protection. When VIN exceeds the UVLO-rising
threshold voltage, the NB650A powers up. It
shuts off when VIN falls below the UVLO-falling
threshold voltage. This is non-latch protection.
Thermal Shutdown
The NB650A employs thermal shutdown by
internally monitoring the temperature of the
junction. If the junction temperature exceeds the
threshold value (typically 150°C), the converter
shuts off. This is non-latch protection. There is
about 25°C hysteresis. Once the junction
temperature drops to around 125°C, it initiates a
soft-start.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
14
NB650A – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
APPLICATION INFORMATION
Setting the Output Voltage-Large ESR Caps
A resistor divider from the output voltage to the
FB pin sets the output voltage. Changing the VID
codes for the NB650A accomplishes the same
thing.
When there is no external ramp, the output
voltages are set by feedback resistors R1 and
R2A, R2B and R2C. First, choose R1 within 5kΩto-100kΩ to ensure stable operation. VOUT1, VOUT2,
VOUT3 and VOUT4 are the voltages at different VID
codes, arranged from low to high. Then
determine R2A, R2B and R2C as follows:
R2C
R2B
1
1
) (VOUT1 VFB(AVG) )
R1 R4 R9
VOUT2 VFB(AVG)
VFB(AVG)
R2C
VOUT3 VFB(AVG)
VFB(AVG)
(15)
1
VOUT3 21 VOUT3 VREF 1
1
VREF
R1 R2A
(16)
The VFB(AVG) is the average value on FB. VFB(AVG)
varies with the VIN, VO, and load condition; its
value in skip mode is lower than in PWM mode,
which means the load regulation is strictly related
to the VFB(AVG). Also the line regulation is related
to the VFB(AVG); use a lower VRAMP that meets the
conditions of equation 10 for better load or line
regulation.
For PWM operation, estimate VFB(AVG) from the
following equation:
Where VOUTx is the output ripple determined by
equation 30.
Setting the Output Voltage-Small ESR Caps
SW
L
VFB(AVG) VREF
R4
Vo
C4
1
R1//R2
VRAMP
2
R1//R2 R9
(21)
Usually, R9 is set to 0Ω, and it can also be set
following equation 22 for better noise immunity.
Set the value to 10×C4 for better DC blocking, but
select a value less than 0.47µF when considering
start up performance. For larger CDC values for
better FB noise immunity, combine with reduced
R1 and R2 to limit the CDC to a reasonable value
without affecting system start-up. Note that even
with CDC, the load and line regulation are still
related to VRAMP.
SW
FB
L
R4
current of the converter. The input ripple current
can be estimated as:
VOUT
V
ICIN IOUT
(1 OUT )
(26)
VIN
VIN
The worst-case condition occurs at:
1
VRAMP )
1
2
R2A
1
1
R1
(23)
C4
R1
Ceramic
R2
Figure 11: Simplified Circuit with Ceramic DCBlocking Capacitor
(27)
For simplification, choose an input capacitor
whose RMS current rating is greater than half of
the maximum load current.
The input capacitance value determines the input
voltage ripple of the converter. If the system
requires a specific input voltage ripple, choose
the input capacitor that meets the specification.
The input voltage ripple can be estimated as:
VIN
IOUT
V
V
OUT (1 OUT )
fSW CIN VIN
VIN
(28)
The worst-case condition occurs at VIN = 2VOUT,
where:
VIN
Vo
Cdc
IOUT
2
I
1
OUT
4 fSW CIN
(29)
Output Capacitor
The output capacitor maintains the DC output
voltage. Use ceramic or POSCAP capacitors.
The output voltage ripple can be estimated as:
VOUT
VOUT
V
1
(1 OUT ) (RESR
) (30)
fSW L
VIN
8 fSW COUT
Input Capacitor
The input current to the step-down converter is
discontinuous, and therefore requires a capacitor
to supply the AC current to the step-down
converter while maintaining the DC input voltage.
Use ceramic capacitors for best performance.
The capacitance varies significantly over
temperature. Capacitors with X5R and X7R
ceramic dielectrics are recommended because
they are fairly stable over temperature.
Where RESR is the equivalent series resistance
(ESR) of the output capacitor.
In the layout, place the input capacitors as close
to the IN pin as possible.
The output voltage ripple caused by ESR is very
small, and therefore requires an external ramp to
stabilize the system. The external ramp can be
generated through resistor R4 and capacitor C4
following equations 5, 9 and 10.
The capacitors must also have a ripple current
rating greater than the maximum input ripple
NB650A Rev. 1.02
6/21/2017
For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency, and causes the majority of the output
voltage ripple. For simplification, the output
voltage ripple can be estimated as:
VOUT
VOUT
V
(1 OUT )
VIN
8 fSW L COUT
2
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
(31)
16
NB650A – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
For POSCAP capacitors, the ESR dominates the
impedance at the switching frequency. The ramp
voltage generated from the ESR is high enough
to stabilize the system. Therefore, an external
ramp is not needed. A minimum ESR value of
12mΩ is required to ensure stable operation of
the converter. For simplification, the output ripple
can be approximated as:
VOUT
VOUT
V
(1 OUT ) RESR
fSW L
VIN
(32)
Inductor
The inductor supplies constant current to the
output load while being driven by the switching
input voltage. A larger value inductor results in
less ripple current, which results in lower output
ripple voltage. However, a larger value inductor is
physically larger, has a higher series resistance,
NB650A Rev. 1.02
6/21/2017
and/or lower saturation current. To determine the
inductor value, allow the inductor peak-to-peak
ripple current to reach approximately 30% to 40%
of the maximum switch current limit. Make sure
that the peak inductor current is below the
maximum switch current limit. The inductance
value can be calculated as:
VOUT
V
L
(1 OUT )
(33)
fSW IL
VIN
Where ΔIL is the peak-to-peak inductor ripple cur
rent.
Choose an inductor that will not saturate under
the maximum inductor peak current. The peak
inductor current can be calculated as:
VOUT
V
ILP IOUT
(1 OUT )
(34)
2fSW L
VIN
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
17
NB650A – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
TYPICAL APPLICATION
Figure 12: Typical Application Circuit with No External Ramp
VIN = 12V, VOUT = 1.05/1.15/1.20V, IOUT = 6A, fSW = 550kHz
Figure 13: Typical Application with Low-ESR Ceramic Capacitor
VIN = 12V, VOUT = 1.05/1.10/1.15/1.20V, IOUT = 6A, fSW = 550kHz
NB650A Rev. 1.02
6/21/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
18
NB650A – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
Figure 14: Typical Application Circuit with Low-ESR Ceramic Capacitor and DC-Blocking Capacitor
VIN =12V, VOUT = 1.05/1.10/1.15/1.20V, IOUT = 6A, fSW = 550kHz
Figure 15: Typical Application Circuit
VIN = 19V, VOUT = 0.65/0.75/0.80/0.90V, IOUT = 6A
NB650A Rev. 1.02
6/21/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
19
NB650A – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
LAYOUT RECOMMENDATIONS
GND
1. Place the high current paths (GND, IN, and
SW) as close to the device as possible with
direct, short, and wide traces.
2. Use a 0.1μF input decoupling capacitor to
connect the IN and GND pins. Put the input
decoupling capacitor and input capacitors as
close to the IN and GND pins as possible.
3. Put the VCC decoupling capacitor as close to
the VCC and GND pins as possible.
4. Keep the switching node SW short and away
from the feedback network.
5. Place the external feedback resistors next to
the FB pin. Make sure that there is no via on
the FB trace.
6. Keep the BST voltage path (BST, CBST, and
SW) as short as possible.
7. Keep the IN and GND pads connected with
large copper to to achieve better thermal
performance. Also, add several Vias with
10mil_drill/18mil_copper_width close to the
IN and GND pads to help on thermal
dissipation.
GND
Inner1 Layer
GND
GND
8. Use a four-layer layout to achieve better
thermal performance.
R3
C4
GND
Inner2 Layer
R3
R2A
R3
R2C
R3
R7
R2B
R3
R3
R4
R3
R1
GND
GND
SW
L1
SW
RFB1
16
15
1
RFB2
FB
14
13
AGND
12
IN
11
IN
PGND
10
PGND
PGND
9
PGND
C6
C1
SS
17
R3
SW
FREQ
SW
SW
2
R3
C3
3
4
5
6
7
8
BST
PG
EN
VID1
VID2
VCC
R3
C5
R3
R5
GND
GND
VOUT
VIN
SW1
C2
R3
R11
Top Layer
R3
R10
R3
R6
VOUT
+1V
Bottom Layer
Figure 16: PCB Layout Guide
NB650A Rev. 1.02
6/21/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
20
NB650A – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
PACKAGE OUTLINE DRAWING FOR 17L FCQFN (3X4MM)
PACKAGE INFORMATION
MF-PO-D-0091 revision 1.0
QFN17 (3 x 4mm)
1.00
BSC
0.35
0.45
2.90
3.10
0.50
0.70
17
12
PIN 1 ID
MARKING
0.20
0.30
11
1
3.90
4.10
PIN 1 ID
INDEX AREA
0.80
BSC
0.80
BSC
2
9
0.35
0.45
8
TOP VIEW
0.20
0.30
3 0.50
BSC
BOTTOM VIEW
0.80
1.00
0.20 REF
0.00
0.05
SIDE VIEW
2.90
1.00
NOTE:
0.80
0.80
3.90
0.25
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT
INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10
MILLIMETER MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
0.70
0.70
0.25
0.60
0.50
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
NB650A Rev. 1.02
6/21/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
21
工商网监
湘ICP备2023018690号
