NB671L
24V, High Current
Synchronous Step-down Converter
DESCRIPTION
FEATURES
The NB671L is the low quiescent current
version of NB671. It is a fully integrated high
frequency synchronous rectified step-down
switch mode converter, which offers very
compact solutions to achieve 6A continuous
output current and 9A peak current over a wide
input supply range with excellent load and line
regulation. The NB671L operates at high
efficiency over a wide output current load range.
•
•
•
•
•
•
Constant-On-Time
(COT)
control
mode
provides fast transient response and eases loop
stabilization.
Under voltage lockout is internally set as 4.5 V,
An open drain power good signal indicates the
output is within its nominal voltage range.
Full protection features include OCP, OVP, and
thermal shut down.
The converter requires minimum number of
external components and is available in QFN16
(3mmx3mm) package.
The NB671L is pin-to-pin compatible with
NB671 with a NC pin changed to LP#, which is
used to receive the power state command from
the system.
•
•
•
•
•
•
•
•
Wide 5.5V to 24V Operating Input Range
6A Continuous Output Current
9A Peak Output Current
120μA Quiescent Current
Low RDS(ON) Internal Power MOSFETs
Proprietary Switching Loss Reduction
Technique
1% Reference Voltage
Internal Soft Start
Output Discharge
500kHZ Switching Frequency
OCP, OVP, UVP Protection and Thermal
Shutdown
Latch off Reset via EN or Power Cycle.
Output Adjustable from 0.604V to 5.5V
Support 5V Output from 5.5V Input
APPLICATIONS
•
•
•
•
•
•
Laptop Computer
Tablet PC
Networking Systems
Personal Video Recorders
Flat Panel Television and Monitors
Distributed Power Systems
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
NB671L Rev. 1.02
1/5/2018
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1
NB671L, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number*
Package
Top Marking
NB671LGQ
QFN16 (3x3mm)
AES
* For Tape & Reel, add suffix –Z (e.g. NB671LGQ–Z)
PACKAGE REFERENCE
TOP VIEW
VIN
AGND
EN
FB
VCC
BST
14
13
12
11
10
1
15 SW
PGND
9
SW
8
SW
2
16 SW
3
4
5
6
7
LP#
PG
NC
NC
VOUT
(5)
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
Supply Voltage VIN .......................................24V
VSW ............................................. -0.3V to 24.3V
VSW (30ns) ................................... -3V to VIN+4V
VBST .....................................................VSW + 6V
VEN ...............................................................12V
Enable Current IEN(2)................................ 2.5mA
All Other Pins ............................. –0.3V to +5.5V
(3)
Continuous Power Dissipation (TA=+25°)
QFN16...……………………….…..…………1.8W
Junction Temperature .............................. 150°C
Lead Temperature ................................... 260°C
Storage Temperature ............... -65°C to +150°C
Notes:
1) Exceeding these ratings may damage the device.
2) Refer to Page 19 of Configuring the EN Control.
3) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
4) The device is not guaranteed to function outside of its
operating conditions.
5) Measured on JESD51-7, 4-layer PCB.
Recommended Operating Conditions
QFN16 (3mmx3mm) ............... 70 ...... 15 ... °C/W
(4)
Supply Voltage VIN .......................... 5.5V to 22V
Output Voltage VOUT................... 0.604V to 5.5V
Enable Current IEN...................................... 1mA
Operating Junction Temp. (TJ). -40°C to +125°C
NB671L Rev. 1.02
1/5/2018
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2
NB671L, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = 25°C, LP=High,unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
0
1
μA
Supply Current
Supply Current (Shutdown)
IIN
Supply Current (Quiescent)
IIN
Supply Current (Quiescent)
IIN
VEN = 0V
VEN = 2V, VFB = 0.65V,
VLP#=0V
VEN = 2V, VFB = 0.65V,
VLP#=1V
120
μA
240
μA
30
15
0
1
mΩ
mΩ
μA
7.8
8.5
9.5
A
400
500
600
MOSFET
High-side Switch On Resistance
Low-side Switch On Resistance
Switch Leakage
HSRDS-ON
LSRDS-ON
SW LKG
VEN = 0V, VSW = 0V or 12V
Current Limit
Low-side Valley Current Limit
ILIMIT
Switching frequency and minimum off timer
VIN>7V, VOUT=5V
Switching frequency
FS
6V1M
resistor if not used, the LP# support 1.05V Logic and is 3.3V tolerant.
The quiescent current will be lowered to 60μA in low power mode to further improve
the light load efficiency.
Power good output, the output of this pin is an open drain signal and is high if the
output voltage is higher than 95% of the nominal voltage. There is a delay from FB ≥
95% to PGOOD goes high.
VOUT pin is used to sense the output voltage of the Buck regulator, connect this pin
to the output capacitor of the regulator directly.
Switch Output. Connect this pin to the inductor and bootstrap capacitor. This pin is
driven up to the VIN voltage by the high-side switch during the on-time of the PWM
duty cycle. The inductor current drives the SW pin negative during the off-time. The
on-resistance of the low-side switch and the internal diode fixes the negative
voltage. Use wide and short PCB traces to make the connection. Try to minimize the
area of the SW pattern.
Bootstrap. A capacitor connected between SW and BS pins is required to form a
floating supply across the high-side switch driver.
Internal 5V LDO output. The driver and control circuits are powered from this
voltage. Decouple with a minimum 1µF ceramic capacitor as close to the pin as
possible. X7R or X5R grade dielectric ceramic capacitors are recommended for their
stable temperature characteristics.
Feedback. An external resistor divider from the output to GND, tapped to the FB pin,
sets the output voltage. It is recommended to place the resistor divider as close to
FB pin as possible. Vias should be avoided on the FB traces.
Enable pin. EN is a digital input that turns the regulator on or off. Drive EN high to
turn on the regulator, drive it low to turn it off. Connect EN with VIN through a pull-up
resistor or a resistive voltage divider for automatic startup. Do not float this pin.
Analog ground. The internal reference is referred to AGND. Connect the GND of the
FB divider resistor to AGND for better load regulation.
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5
NB671L, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN=20V, VOUT =5V, L=2µH, TJ=+25°C, unless otherwise noted.
NB671L Rev. 1.02
1/5/2018
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6
NB671L, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN=20V, VOUT =5V, L=2µH, TJ=+25°C, unless otherwise noted.
NB671L Rev. 1.02
1/5/2018
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7
NB671L, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN=20V, VOUT =5V, L=2µH, TJ=+25°C, unless otherwise noted.
NB671L Rev. 1.02
1/5/2018
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8
NB671L, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
BLOCK DIAGRAM
LP#
VOUT
VCC
VIN
BST
BSTREG
POR &
Reference
Softstart
VIN
0.6V Vref
On Time
One Shot
FB
Control
Logic
Min off time
SW
EN
VOUT
PGND
1V
SW
130% Vref
OCP
PG
OVP
95% Vref
Fault
logic
POK
60% Vref
UVP
AGND
Figure 1—Functional Block Diagram
NB671L Rev. 1.02
1/5/2018
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9
NB671L, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
OPERATION
PWM Operation
The NB671L is fully integrated synchronous
rectified step-down switch mode converter with
ultra low quiescent current. Constant-on-time
(COT) control is employed to provide fast
transient response and easy loop stabilization. At
the beginning of each cycle, the high-side
MOSFET (HS-FET) is turned ON when the
feedback voltage (VFB) is below the reference
voltage (VREF), which indicates insufficient
output voltage. The ON period is determined by
both the output voltage and input voltage to make
the switching frequency fairy constant over input
voltage range.
After the ON period elapses, the HS-FET is
turned off, or becomes OFF state. It is turned ON
again when VFB drops below VREF. By
repeating operation this way, the converter
regulates the output voltage. The integrated lowside MOSFET (LS-FET) is turned on when the
HS-FET is in its OFF state to minimize the
conduction loss. There will be a dead short
between input and GND if both HS-FET and LSFET are turned on at the same time. It’s called
shoot-through. In order to avoid shoot-through, a
dead-time (DT) is internally generated between
HS-FET off and LS-FET on, or LS-FET off and
HS-FET on.
The NB671L detects VIN and VOUT, when VIN is
close to VOUT, the ON time will be extended;
hence the switching frequency decreases. By
doing that, this part is able to support 5.5V VIN to
5V VOUT conversion.
The switching frequency is lowered to around
150kHz when VIN is 5.5V and VOUT is 5V. As VIN
is so close to VOUT, the inductor current ripple is
very small; hence the output voltage ripple is also
well controlled even the switching frequency is
150kHz.
An internal compensation is applied for COT
control to make a more stable operation even
when ceramic capacitors are used as output
capacitors, this internal compensation will then
improve the jitter performance without affect the
line or load regulation.
NB671L Rev. 1.02
1/5/2018
Heavy-Load Operation
Figure 2—Heavy Load Operation
When the output current is high and the inductor
current is always above zero amps, it is called
continuous-conduction-mode (CCM). The CCM
mode operation is shown in Figure 2 shown.
When VFB is below VREF, HS-MOSFET is turned
on for a fixed interval which is determined by
one- shot on-timer as equation 1 shown. When
the HS-MOSFET is turned off, the LS-MOSFET
is turned on until next period.
In CCM mode operation, the switching frequency
is fairly constant and it is called PWM mode.
Light-Load Operation
With the load decrease, the inductor current
decrease too. Once the inductor current touch
zero, the operation is transition from continuousconduction-mode (CCM) to discontinuousconduction-mode (DCM).
The light load operation is shown in Figure 3.
When VFB is below VREF, HS-MOSFET is turned
on for a fixed interval which is determined by
one- shot on-timer as equation 1 shown. When
the HS-MOSFET is turned off, the LS-MOSFET
is turned on until the inductor current reaches
zero. In DCM operation, the VFB does not reach
VREF when the inductor current is approaching
zero. The LS-FET driver turns into tri-state (high
Z) whenever the inductor current reaches zero. A
current modulator takes over the control of LSFET and limits the inductor current to less than 1mA. Hence, the output capacitors discharge
slowly to GND through LS-FET. As a result, the
efficiency at light load condition is greatly
improved. At light load condition, the HS-FET is
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10
NB671L, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
not turned ON as frequently as at heavy load
condition. This is called skip mode.
At light load or no load condition, the output
drops very slowly and the NB671L reduces the
switching frequency naturally and then high
efficiency is achieved at light load.
Figure 5—Jitter in Skip Mode
Operating without external ramp
Figure 3—Light Load Operation
As the output current increases from the light
load condition, the time period within which the
current modulator regulates becomes shorter.
The HS-FET is turned ON more frequently.
Hence, the switching frequency increases
correspondingly. The output current reaches the
critical level when the current modulator time is
zero. The critical level of the output current is
determined as follows:
IOUT =
(VIN − VOUT ) × VOUT
2 × L × FSW × VIN
(1)
It turns into PWM mode once the output current
exceeds the critical level. After that, the switching
frequency stays fairly constant over the output
current range.
Jitter and FB Ramp Slope
Jitter occurs in both PWM and skip modes when
noise in the VFB ripple propagates a delay to the
HS-FET driver, as shown in Figures 4 and 5.
Jitter can affect system stability, with noise
immunity proportional to the steepness of VFB’s
downward slope. However, VFB ripple does not
directly affect noise immunity.
The traditional constant-on-time control scheme
is intrinsically unstable if output capacitor’s ESR
is not large enough as an effective current-sense
resistor. Ceramic capacitors usually can not be
used as output capacitor.
To realize the stability, the ESR value should be
chosen as follow:
TSW
T
+ ON
2
RESR ≥ 0.7 × π
COUT
TSW is the switching period.
(2)
The NB671L has built in internal ramp
compensation to make sure the system is stable
even without the help of output capacitor’s ESR;
and thus the pure ceramic capacitor solution can
be applicant. The pure ceramic capacitor solution
can significantly reduce the output ripple, total
BOM cost and the board area.
Figure 6 shows a typical output circuit in PWM
mode without an external ramp circuit. Turn to
application information section for design steps
without external compensation.
SW
L
FB
Vo
R1
R2
ESR
CAP
Figure 6—Simplified Circuit in PWM Mode
without External Ramp Compensation
Figure 4—Jitter in PWM Mode
NB671L Rev. 1.02
1/5/2018
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11
NB671L, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
When using a large-ESR capacitor on the output,
add a ceramic capacitor with a value of 10uF or
less to in parallel to minimize the effect of ESL.
Operating with external ramp compensation
The NB671L is usually able to support ceramic
output capacitors without external ramp, however,
in some of the cases, the internal ramp may not
be enough to stabilize the system, and external
ramp compensation is needed. Skip to
application information section for design steps
with external ramp compensation.
L
SW
TSW
T
+ ON -RESRCOUT
Io × 10-3
0.7
π
2
×
(7)
-Vslope1 ≥
VOUT +
2 × L × COUT
TSW -Ton
Io is the load current.
In skip mode, the downward slope of the VFB
ripple is the same whether the external ramp is
used or not. Figure 8 shows the simplified circuit
of the skip mode when both the HS-FET and LSFET are off.
Vo
Vo
C4
R4
IR4
IC4
R9
R1
FB
R1
I FB
Ro
Ceramic
FB
R2
R2
Figure 7—Simplified Circuit in PWM Mode
with External Ramp Compensation
2π × FSW × C4
<
1 R1 × R2
×
+ R9
5 R1 + R2
(3)
Where:
IR4 = IC4 + IFB ≈ IC4
(4)
And the Vramp on the VFB can then be estimated
as:
V=
RAMP
VIN − VOUT
R1 // R2
× TON ×
R 4 × C4
R1 // R2 + R9
(5)
The downward slope of the VFB ripple then
follows
V
=
SLOPE1
− VOUT
− VRAMP
=
Toff
R 4 × C4
(6)
As can be seen from equation 6, if there is
instability in PWM mode, we can reduce either
R4 or C4. If C4 can not be reduced further due to
limitation from equation 3, then we can only
reduce R4. For a stable PWM operation, the
Vslope1 should be design follow equation 7.
NB671L Rev. 1.02
1/5/2018
Cout
Figure 8—Simplified Circuit in skip Mode
Figure 7 shows a simplified external ramp
compensation (R4 and C4) for PWM mode, with
HS-FET off. Chose R1, R2, R9 and C4 of the
external ramp to meet the following condition:
1
ESR
The downward slope of the VFB ripple in skip
mode can be determined as follow:
VSLOPE2 =
− VREF
((R1 + R2 ) // Ro) × COUT
(8)
Where Ro is the equivalent load resistor.
As described in Figure 5, VSLOPE2 in the skip
mode is lower than that is in the PWM mode, so
it is reasonable that the jitter in the skip mode is
larger. If one wants a system with less jitter
during light load condition, the values of the VFB
resistors should not be too big, however, that will
decrease the light load efficiency.
Configuring the EN Control
EN is used to enable or disable the whole chip.
Pull En high to turn on the regulator and pull EN
low to turn it off. Do not float the pin.
For automatic start-up the EN pin can be pulled
up to input voltage through a resistive voltage
divider. Choose the values of the pull-up resistor
(Rup from Vin pin to EN pin) and the pull-down
resistor (Rdown from EN pin to GND) to
determine the automatic start-up voltage:
= 1.25 ×
VIN−START
(Rup + Rdown )
Rdown
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(V)
(9)
12
NB671L, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
For
example,
for
Rup=191kΩ
Rdown=51kΩ,the VIN−START is set at 6V.
and
To avoid noise, a 10nF ceramic capacitor from
EN to GND is recommended.
There is an internal Zener diode on the EN pin,
which clamps the EN pin voltage to prevent it
from running away. The maximum pull up current
assuming a worst case 6V internal Zener clamp
should be less than 1mA.
Therefore, when EN is driven by an external logic
signal, the EN voltage should be lower than 6V;
when EN is connected with VIN through a pull-up
resistor or a resistive voltage divider, the
resistance selection should ensure the maximum
pull up current less than 1mA.
If using a resistive voltage divider and VIN higher
than 5.5V, the allowed minimum pull-up resistor
Rup should meet the following equation:
VIN -6V 6V
(10)
=1mA
Rup
Rdown
Especially, just using the pull-up resistor Rup(the
pull-down resistor is not connected), the
VIN-START is determined by input UVLO, and the
minimum resistor value is:
V -6V
(11)
Rup = IN
(W)
1mA
A typical pull-up resistor is 100kΩ.
Soft Start
The NB671L employs soft start (SS) mechanism
to ensure smooth output during power-up. When
the EN pin becomes high, the internal reference
voltage ramps up gradually; hence, the output
voltage ramps up smoothly, as well. Once the
reference voltage reaches the target value, the
soft start finishes and it enters into steady state
operation.
If the output is pre-biased to a certain voltage
during startup, the IC will disable the switching of
both high-side and low-side switches until the
voltage on the internal reference exceeds the
sensed output voltage at the FB node.
Power Good (PGOOD)
The NB671L has power-good (PGOOD) output
used to indicate whether the output voltage of the
Buck regulator is ready or not. The PGOOD pin
is the open drain of a MOSFET. It should be
NB671L Rev. 1.02
1/5/2018
connected to VCC or other voltage source through
a resistor (e.g. 100k). After the input voltage is
applied, the MOSFET is turned on so that the
PGOOD pin is pulled to GND before SS is ready.
After FB voltage reaches 95% of REF voltage,
the PGOOD pin is pulled high after a delay. The
PGOOD delay time is 1ms.
When the FB voltage drops to 85% of REF
voltage, the PGOOD pin will be pulled low.
Over Current Protection
NB671L has cycle-by-cycle over current limiting
control. The current-limit circuit employs a
"valley" current-sensing algorithm. The part uses
the Rds(on) of the low side MOSFET as a
current-sensing element. If the magnitude of the
current-sense signal is above the current-limit
threshold, the PWM is not allowed to initiate a
new cycle.
The trip level is fixed internally. The inductor
current is monitored by the voltage between GND
pin and SW pin. GND is used as the positive
current sensing node so that GND should be
connected to the source terminal of the bottom
MOSFET.
Since the comparison is done during the high
side MOSFET OFF and low side MOSFET ON
state, the OC trip level sets the valley level of the
inductor current. Thus, the load current at overcurrent threshold, IOC, can be calculated as
follows:
IOC I _ limit +
=
∆Iinductor
2
(12)
In an over-current condition, the current to the
load exceeds the current to the output capacitor;
thus the output voltage tends to fall off.
Eventually, it will end up with crossing the under
voltage protection threshold and shutdown. And
fault latching can be reset by EN going low or
Power-cycling of VIN.
Over/Under-Voltage Protection (OVP/UVP)
NB671L monitors a resistor divided feedback
voltage to detect over and under voltage. When
the feedback voltage becomes higher than 115%
of the target voltage, the controller will enter
Dynamic Regulation Period. During this period,
the LS will off when the LS current goes to -1A,
this will then discharge the output and try to keep
it within the normal range. If the dynamic
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13
NB671L, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
regulation can not limit the increasing of the Vo,
once the feedback voltage becomes higher than
130% of the feedback voltage, the OVP
comparator output goes high and the circuit
latches as the high-side MOSFET driver OFF
and the low-side MOSFET turns on acting as an 1A current source.
When the feedback voltage becomes lower than
60% of the target voltage, the UVP comparator
output goes high if the UV still occurs after 26us
delay;; then the fault latch will be triggered--latches HS off and LS on; the LS FET keeps on
until the inductor current goes zero. Also fault
latching can be reset by EN going low or Powercycling of VIN.
UVLO Protection
The NB671L has under-voltage lock-out
protection (UVLO). When the VCC voltage is
higher than the UVLO rising threshold voltage,
the part will be powered up. It shuts off when the
VIN voltage is lower than the UVLO falling
threshold voltage. This is non-latch protection.
The part is disabled when the VCC voltage falls
below 4.5V. Besides fault latching can be reset
by EN going low or Power-cycling of VIN. If an
application requires a higher under-voltage
lockout (UVLO), use the EN pin as shown in
Figure 9 to adjust the input voltage UVLO by
using two external resistors. It is recommended
to use the enable resistors to set the UVLO
falling threshold (VSTOP) above 4.5V. The rising
threshold (VSTART) should be set to provide
enough hysteresis to allow for any input supply
variations.
Thermal Shutdown
Thermal shutdown is employed in the NB671L.
The junction temperature of the IC is internally
monitored. If the junction temperature exceeds
the threshold value (typical 150ºC), the converter
shuts off. This is a non-latch protection. There is
about 25ºC hysteresis. Once the junction
temperature drops to about 125ºC, it initiates a
SS.
Output Discharge
NB671L discharges the output when EN is low,
or the controller is turned off by the protection
functions (UVP & OCP, OCP, OVP, UVLO, and
thermal shutdown). The part discharges outputs
using an internal 6Ω MOSFET which is
connected to VOUT and GND. The external lowside MOSFET is not turned on for the output
discharge operation to avoid the possibility of
causing negative voltage at the output.
IN
RUP
RDOWN
EN Comparator
EN
Figure 9—Adjustable UVLO
NB671L Rev. 1.02
1/5/2018
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14
NB671L, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
APPLICATION INFORMATION
Setting the Output Voltage---without external
compensation
For applications that electrolytic capacitor or POS
capacitor with a controlled output of ESR is set
as
output
capacitors,
or
the
internal
compensation is enough for a stable operation
when ceramic capacitors is used, then the
external compensation is not need.. The output
voltage is set by feedback resistors R1 and R2.
As Figure 10 shows.
SW
Vo
L
ESR
R1
FB
POSCAP
R2
1
Figure10—Simplified Circuit of POS Capacitor
First, choose a value for R2. R2 should be
chosen reasonably, a small R2 will lead to
considerable quiescent current loss while too
large R2 makes the FB noise sensitive. It is
recommended to choose a value within 5kΩ100kΩ for R2, then R1 is determined as follow
with the output ripple considered:
1
VOUT − ∆VOUT − VREF
2
(13)
=
R1
⋅ R2
VREF
∆VOUT is the output ripple.
Setting the Output Voltage---with external
compensation
SW
Vo
L
FB
R4
C4
R1
R9
Ceramic
R2
Figure11—Simplified Circuit of Ceramic
Capacitor
NB671L Rev. 1.02
1/5/2018
If the system is not stable enough when low ESR
ceramic capacitor is used in the output, an
external voltage ramp should be added to FB
through resistor R4 and capacitor C4.The output
voltage is influenced by ramp voltage VRAMP
besides R divider as shown in Figure 11. The
VRAMP can be calculated as shown in equation 7.
R2 should be chosen reasonably, a small R2 will
lead to considerable quiescent current loss while
too large R2 makes the FB noise sensitive. It is
recommended to choose a value within 5kΩ50kΩ for R2, using a comparatively larger R2
when Vo is low, etc.,1.05V, and a smaller R2
when Vo is high. And the value of R1 then is
determined as follow:
R2
(14)
R=
VFB(AVG)
R2
(VOUT -VFB(AVG) ) R 4 +R9
-
The VFB(AVG) is the average value on the FB,
VFB(AVG) varies with the Vin, Vo, and load
condition, etc., its value on the skip mode would
be lower than that of the PWM mode, which
means the load regulation is strictly related to the
VFB(AVG). Also the line regulation is related to the
VFB(AVG). If one wants to gets a better load or line
regulation, a lower Vramp is suggested, as long
as the criterion shown in equation 8 can be met.
For PWM operation, VFB(AVG) value can be
deduced from the equation below.
R1 // R2
1
(15)
VFB( AVG) =
VREF + VRAMP ×
2
R1 // R2 + R9
Usually, R9 is set to 0Ω, and it can also be set
following equation 14 for a better noise immunity.
It should also set to be 5 times smaller than
R1//R2 to minimize its influence on Vramp.
1
(16)
R9 =
2π × C4 × 2FSW
Using equation 13 to calculate the R1 can be
complicated. To simplify the calculation, a DCblocking capacitor Cdc can be added to filter the
DC influence from R4 and R9. Figure 12 shows
a simplified circuit with external ramp
compensation and a DC-blocking capacitor. With
this capacitor, R1 can easily be obtained by
using the simplified equation for PWM mode
operation:
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15
NB671L, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
1
(VOUT − VREF − VRAMP )
2
(17)
R1 =
R2
1
VREF + VRAMP
2
Cdc is suggested to be at least 10 times larger
than C4 for better DC blocking performance, and
should also not larger than 0.47uF considering
start up performance. In case one wants to use
larger Cdc for a better FB noise immunity,
combined with reduced R1 and R2 to limit the
Cdc in a reasonable value without affecting the
system start up. Be noted that even when the
Cdc is applied, the load and line regulation are
still Vramp related.
L
The input voltage ripple can be estimated as
follows::
=
∆VIN
IOUT
V
V
× OUT × (1 − OUT )
FSW × CIN VIN
VIN
(20)
R4
Vo
IOUT
1
∆VIN = ×
4 FSW × CIN
R1
C4
Cdc
Figure12—Simplified Circuit of Ceramic
Capacitor with DC blocking capacitor
Input Capacitor
The input current to the step-down converter is
discontinuous and therefore requires a capacitor
to supply the AC current to the step-down
converter while maintaining the DC input voltage.
Ceramic capacitors are recommended for best
performance and should be placed as close to
the VIN pin as possible. Capacitors with X5R and
X7R ceramic dielectrics are recommended
because they are fairly stable with temperature
fluctuations.
The capacitors must also have a ripple current
rating greater than the maximum input ripple
current of the converter. The input ripple current
can be estimated as follows:
ICIN= IOUT ×
VOUT
V
× (1 − OUT )
VIN
VIN
(18)
The worst-case condition occurs at VIN = 2VOUT,
where:
ICIN =
IOUT
2
(21)
Output Capacitor
Ceramic
R2
NB671L Rev. 1.02
1/5/2018
The input capacitance value determines the input
voltage ripple of the converter. If there is an input
voltage ripple requirement in the system, choose
the input capacitor that meets the specification.
Under worst-case conditions where VIN = 2VOUT:
SW
FB
For simplification, choose the input capacitor with
an RMS current rating greater than half of the
maximum load current.
(19)
The output capacitor is required to maintain the
DC output voltage. Ceramic or POSCAP
capacitors are recommended. The output voltage
ripple can be estimated as:
∆V=
OUT
VOUT
V
1
× (1 − OUT ) × (RESR +
) (22)
FSW × L
VIN
8 × FSW × COUT
In the case of ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance. The output voltage ripple is mainly
caused by the capacitance. For simplification, the
output voltage ripple can be estimated as:
=
∆VOUT
VOUT
V
× (1 − OUT )
2
8 × FSW × L × COUT
VIN
(23)
The output voltage ripple caused by ESR is very
small. Therefore, an external ramp is needed to
stabilize the system. The external ramp can be
generated through resistor R4 and capacitor C4.
In the case of POSCAP capacitors, the ESR
dominates the impedance at the switching
frequency. The ramp voltage generated from the
ESR is high enough to stabilize the system.
Therefore, an external ramp is not needed. A
minimum ESR value around 12mΩ is required to
ensure stable operation of the converter. For
simplification, the output ripple can be
approximated as:
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16
NB671L, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
∆V=
OUT
VOUT
V
× (1 − OUT ) × RESR
FSW × L
VIN
(24)
Maximum output capacitor limitation should be
also considered in design application. NB671L
has an around 1.6ms soft-start time period. If the
output capacitor value is too high, the output
voltage can’t reach the design value during the
soft-start time, and then it will fail to regulate. The
maximum output capacitor value Co_max can be
limited approximately by:
CO _ MAX
= (ILIM _ AVG − IOUT ) × Tss / VOUT
(25)
Where, ILIM_AVG is the average start-up current
during soft-start period. Tss is the soft-start time.
Inductor
The inductor is necessary to supply constant
current to the output load while being driven by
the switched input voltage. A larger-value
inductor will result in less ripple current that will
result in lower output ripple voltage. However, a
larger-value inductor will have a larger physical
footprint, higher series resistance, and/or lower
saturation current. A good rule for determining
the inductance value is to design the peak-topeak ripple current in the inductor to be in the
range of 30% to 40% of the maximum output
current, and that the peak inductor current is
below the maximum switch current limit. The
inductance value can be calculated by:
=
L
VOUT
V
× (1 − OUT )
FSW × ∆IL
VIN
(26)
PCB Layout Guide
1. The high current paths (GND, IN, and SW)
should be placed very close to the device
with short, direct and wide traces.
2. Put the input capacitors as close to the IN
and GND pins as possible.
3. Put the decoupling capacitor as close to the
VCC and GND pins as possible. Place the
Cap close to AGND if the distance is long.
And place >3 Vias if via is required to reduce
the leakage inductance.
4. Keep the switching node SW short and away
from the feedback network.
5. The external feedback resistors should be
placed next to the FB pin. Make sure that
there is no via on the FB trace.
6. Keep the BST voltage path (BST, C3, and
SW) as short as possible.
7. Keep the IN and GND pads connected with
large copper and use at least two layers for
IN and GND trace to achieve better thermal
performance. Also, add several Vias with
10mil_drill/18mil_copper_width close to the
IN and GND pads to help on thermal
dissipation.
8. Four-layer layout is strongly recommended to
achieve better thermal performance.
Note:
Please refer to the PCB Layout Application Note
for more details.
Where ΔIL is the peak-to-peak inductor ripple
current.
The inductor should not saturate under the
maximum inductor peak current, where the peak
inductor current can be calculated by:
ILP= IOUT +
NB671L Rev. 1.02
1/5/2018
VOUT
V
× (1 − OUT )
2FSW × L
VIN
(27)
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17
NB671L, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
--Top Layer
--Bottom Layer
AGND KELVIN
CONNECT TO PGND
--Inner PGND Layer
--Via
GND
AGND
EN
14
12
13
11
10
SW
VIN
1
9
15 SW
2
SW
16
3
LP#
4
5
8
6
7
VOUT
PG
VOUT
GND
DO NOT CONNECT
TO AGND
Figure 13—Recommend Layout
Recommend Design Example
A design example is provided below when the
ceramic capacitors are applied:
Table 2—Design Example
NB671L
VOUT
(V)
Cout
(F)
L
(μH)
R4
(Ω)
C4
(F)
1.05
22μx3
1.2
NS
220p
0.5
59
82
5.0
22μ+330μF
OSCON
2.2
NS
220p
0.5
71.5
10
NB671L Rev. 1.02
1/5/2018
R9
R1
(kΩ) (kΩ)
R2
(kΩ)
The detailed application schematic is shown in
Figure 14 when low ESR caps are used. The
typical performance and circuit waveforms have
been shown in the Typical Performance
Characteristics section. For more possible
applications of this device, please refer to related
Evaluation Board Data Sheets.
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18
NB671L, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL APPLICATION
Figure 14 — Typical Application Circuit For NB671L
VIN=5.5-22V, VOUT=5V, IOUT=6A
NB671L Rev. 1.02
1/5/2018
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19
NB671L, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER
PACKAGE INFORMATION
QFN16 (3X3mm)
PIN 1 ID
MARKING
PIN 1 ID
0.10x45? YP.
PIN 1 ID
INDEX AREA
BOTTOM VIEW
TOP VIEW
SIDE VIEW
NOTE:
0.10x45°
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE
MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
NB671L Rev. 1.02
1/5/2018
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20
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