NB679A
28V, Low IQ, Fixed 5.1V, 8A,
Synchronous Buck Converter
with 100mA LDO and LP# VOUT Scaling
DESCRIPTION
FEATURES
The NB679A is a fully integrated, highfrequency, synchronous, rectified, step-down,
switch-mode converter with a fixed 5.1V output
and low-power mode voltage scaling. It offers a
very compact solution to achieve an 8A
continuous output current and a 10A peak
output current over a wide input supply range
with excellent load and line regulation.
The NB679A operates at high efficiency over a
wide output current load range based on MPS
proprietary switching loss reduction technology
and internal low Ron power MOSFETs.
Adaptive constant-on-time (COT) control mode
provides fast transient response and eases loop
stabilization. The DC auto-tune loop provides
good load and line regulation.
The NB679A provides a fixed 5V LDO, which
can be used to power the external peripheries.
Full protection features include OC limit, OVP,
UVP, and thermal shutdown.
Wide 5.5V to 28V Operating Input Range
Fixed 5.1V Vout (+2% of 5V Vout)
LP# Output Voltage Scaling (-3% of 5V Vout)
Supports Large Duty Operation
Ultrasonic Mode
100μA Low Quiescent Current
8A Continuous Output Current and 10A
Peak Output Current
Adaptive COT for Fast Transient
DC Auto-Tune Loop
Stable with POSCAP and Ceramic Output
Capacitors
Built-In 5V, 100mA LDO with Switch Over
1% Reference Voltage
Internal Soft Start
Output Discharge
700kHZ Switching Frequency
OCP, OVP, UVP, and Thermal Shutdown
Latch-Off Reset via EN or Power Cycle
QFN-12 2mm x 3mm Package
APPLICATIONS
The converter requires a minimum number of
external components and is available in a
QFN-12 2mm x 3mm package.
Laptop Computers
Tablet PCs
Networking Systems
Flat Panel Televisions and Monitors
Distributed Power Systems
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
3.3Ω
VIN
220nF
5.5V-24V
BST
VIN
22μF
LP#
GND
EN
5V/ 100mA
VOUT
1.5μH
5.1V/8A
SW
LP#
NB679A
88μF
VOUT
EN
PGND
LDO
PG
VCC
AGND
100kΩ
GND
4.7μF
1μF
NB679A Rev. 1.03
7/27/2017
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© 2017 MPS. All Rights Reserved.
1
NB679A–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING
ORDERING INFORMATION
Part Number*
Package
Top Marking
NB679AGD
QFN-12 (2mm x 3mm)
See Below
* For Tape & Reel, add suffix –Z (e.g. NB679AGD–Z)
TOP MARKING
APA: Product code of NB679AGD
Y: Year code
LLL: Lot number
PACKAGE REFERENCE
Top View
LP#
EN
12
11
AGND VCC
10
9
8
1
Vin
SW
7
PGND
NB679A Rev. 1.03
7/27/2017
BST
2
3
4
5
6
PG
NC
VOUT
LDO
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2
NB679A–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING
ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage (VIN) .....................................28V
VSW (DC) ........................................... -1V to 26V
VSW (25ns) ..................................... -3.6V to 28V
VBST ...................................................VSW +4.5V
VOUT, VLDO ..................................... -0.3V to 6.5V
All other pins ............................... -0.3V to +4.5V
(2)
Continuous power dissipation (TA = +25°C)
QFN-12 (2mm x 3mm) ...............................1.8W
Junction temperature ............................... 150C
Lead temperature .................................... 260C
Storage temperature ................ -65C to +150C
Recommended Operating Conditions
(3)
Thermal Resistance
(4)
θJA
θJC
QFN-12 (2mm x 3mm) ........... 70 ...... 15 ... C/W
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation
will produce an excessive die temperature, causing the
regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
Supply voltage ................................ 5.5V to 24V
Operating junction temp. (TJ). .. -40°C to +125°C
NB679A Rev. 1.03
7/27/2017
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3
NB679A–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING
ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = 25C, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
1
2
μA
110
130
µA
Supply Current
Supply current (shutdown)
IIN
VEN = 0V, VLP# = 0V,
Supply current (quiescent)
IIN
VEN = VLP# = 3.3V,
VOUT = 5.5V
MOSFET
High-side switch on resistance
HSRDS-ON
25
mΩ
Low-side switch on resistance
LSRDS-ON
12
mΩ
Switch leakage
SW LKG
VEN = 0V, VSW = 0V
0
1
μA
11
12
A
Current Limit
Low-side valley current limit
ILIMIT
10
Switching Frequency and Timer
Switching frequency
Constant on timer
(5)
Minimum on time
(5)
Minimum off time
FS
Ton
Vin = 9.7V, VLP# = 0V
600
TON_Min
TOFF_Min
700
710
50
200
820
kHz
ns
ns
ns
Ultrasonic Mode
Ultrasonic mode operation period
TUSM
20
30
40
µs
117%
70%
127%
80%
45%
122%
75%
32
50%
VREF
VREF
µs
VREF
VLP# = 3.3V
5.05
5.1
5.15
VLP# = 0V
EN to Vout OK
4.8
4.85
1.7
4.9
2.5
1.3
150
1.4
Over-Voltage and Under-Voltage Protection
OVP threshold
UVP-1 threshold
(5)
UVP-1 foldback timer
UVP-2 threshold
VOVP
VUVP-1
TUVP-1
VUVP-2
55%
Reference and Soft Start
Vout REF voltage
VOUT_REF
Soft-start time
Enable and UVLO
TSS
Enable rising threshold
Enable hysteresis
EN high limit @ USM
VEN_H_USM
EN low limit @ Normal
VEN_L_Normal
Enable input current
VIN under-voltage lockout
threshold rising
NB679A Rev. 1.03
7/27/2017
VEN_H
VEN-HYS
IEN
VINVTH
1.2
1.8
2.6
VEN = 2V
VEN = 0V
V
ms
V
mV
V
V
5
0
4.45
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μA
4.7
V
4
NB679A–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, TJ = 25C, unless otherwise noted.
Parameters
Symbol
VIN under-voltage lockout threshold
hysteresis
LP# Logic
LP# rising threshold
LP# hysteresis
Condition
Min
VINHYS
Typ
Max
450
VLP#_H
VLP#-HYS
Units
mV
1.2
1.3
150
1.4
V
mV
4.85
4.97
5.12
V
LDO Regulator
LDO regulator
VLDO
LDO load regulation
LDO I-LIMIT
(5)
Switch Rdson
ILDO_Limit
(5)
RSwitch
VEN = 3.3V, VOUT = 0V
VEN = 3.3V, VOUT = 0V ,
LDO load = 100mA
VEN = 3.3V, VOUT = 0V , VLDO
= 4.5V
ILDO = 50mA
2
%
135
mA
0.9
1.2
Ω
3.6
3.7
V
VCC Regulator
VCC regulator
VCC
VCC load regulation
3.5
Icc = 5mA
5
%
Power Good
PG when FB risng (good)
PG when FB falling (fault)
PG_Rising(GOOD) VFB rising, percentage of VFB
PG_Falling(Fault) VFB falling, percentage of VFB
95
85
PG when FB rising (fault)
PG when FB falling (good)
Power good low to high delay
EN low to power good low delay
Power good sink current capability
Power good leakage current
Thermal Protection
PG_Rising(Fault)
PG_Falling(GOOD)
PGTd
PGTd_EN low
VPG
IPG_LEAK
115
105
750
(5)
Thermal shutdown
(5)
Thermal shutdown hysteresis
TSD
TSD-HYS
VFB rising, percentage of VFB
VFB falling, percentage of VFB
%
5
0.4
5
Sink 4mA
VPG = 3.3V
140
25
μs
μs
V
μA
°C
°C
NOTE:
5) Guaranteed by design.
NB679A Rev. 1.03
7/27/2017
www.MonolithicPower.com
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5
NB679A–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING
PIN FUNCTIONS
PIN #
Name
1
VIN
2
PGND
3
PG
4
NC
5
VOUT
6
LDO
7
SW
8
BST
9
VCC
10
AGND
11
EN
12
LP#
NB679A Rev. 1.03
7/27/2017
Description
Supply voltage. VIN supplies power for the internal MOSFET and regulator. The NB679A
operates from a 5.5V to 24V input rail. An input capacitor is needed to decouple the input
rail. Use wide PCB traces and multiple vias to make the connection. Apply at least two
layers for this input trace.
Power ground. To make the connection, use wide PCB traces and enough vias to handle
the load current.
Power good output. The output of PG is an open-drain signal. It is high if the output
voltage is higher than 95% or lower than 105% of the nominal voltage.
No connection.
Senses the output voltage of the buck regulator. Connect VOUT to the output
capacitor of the regulator directly. VOUT also acts as the input of the internal LDO switch
over-power input. Keep the VOUT sensing trace far away from the SW node. Vias should
be avoided on the VOUT sensing trace. A > 25 mil trace is required.
Internal LDO output. The driver and control circuits are powered from this voltage.
Decouple with a minimum 4.7µF ceramic capacitor as close to LDO as possible. X7R or
X5R grade dielectric ceramic capacitors are recommended for their stable temperature
characteristics. Once the PG of the output voltage of the buck regulator is ready, it will
switch over the LDO output to reduce power loss.
Switch output. Connect SW to the inductor and bootstrap capacitor. SW is driven up to
the VIN voltage by the high-side switch during the on-time of the PWM duty cycle. The
inductor current drives SW negative during the off time. The on resistance of the low-side
switch and the internal diode fixes the negative voltage. Use wide and short PCB traces to
make the connection. Try to minimize the area of the SW pattern.
Bootstrap. A capacitor connected between SW and BST is required to form a floating
supply across the high-side switch driver.
Internal VCC LDO output. The driver and control circuits are powered from this voltage.
Decouple with a minimum 1µF ceramic capacitor as close to VCC as possible. X7R or
X5R grade dielectric ceramic capacitors are recommended for their stable temperature
characteristics.
Signal logic ground. A Kelvin connection to PGND is required.
Buck enable. EN is a digital input that turns the buck regulator on or off. When the power
supply of the control circuit is ready, drive EN high to turn on the buck regulator and drive
EN low to turn off the buck regulator. Note that there is a 600kΩ internal pull low resistor.
Connect EN with 3V3 through a pull-up resistor or a resistive voltage divider for automatic
start-up. EN threshold also sets mode between USM and normal. When EN is in the range
of 1.4V to 1.8V, it will enter USM. If EN is in the range of 2.6V to 3.6V, it is normal mode.
Low-power mode control logic. LP# is pulled high internally. Leave LP# open to enter
normal mode with a 5.1V Vout. Drive LP# low to enter low-power mode with lower than a
4.85V Vout.
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NB679A–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, LP# = 1, VOUT = 5.1V, L = 1.5µH/10mΩ, fs = 700kHz, TJ = +25°C, unless otherwise noted.
NB679A Rev. 1.03
7/27/2017
www.MonolithicPower.com
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© 2017 MPS. All Rights Reserved.
7
NB679A–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, LP# = 1, VOUT = 5.1V, L = 1.5µH/10mΩ, fs = 700kHz, TJ = +25°C, unless otherwise noted.
NB679A Rev. 1.03
7/27/2017
www.MonolithicPower.com
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© 2017 MPS. All Rights Reserved.
8
NB679A–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, LP# = 1, VOUT = 5.1V, L = 1.5µH/10mΩ, fs = 700kHz, TJ = +25°C, unless otherwise noted.
NB679A Rev. 1.03
7/27/2017
www.MonolithicPower.com
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© 2017 MPS. All Rights Reserved.
9
NB679A–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, LP# = 1, VOUT = 5.1V, L = 1.5µH/10mΩ, fs = 700kHz, TJ = +25°C, unless otherwise noted.
NB679A Rev. 1.03
7/27/2017
www.MonolithicPower.com
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© 2017 MPS. All Rights Reserved.
10
NB679A–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING
FUNCTIONAL BLOCK DIAGRAM
NB679A
AGND
EN
VCC
VIN
VOUT
VIN
BST
BSTREG
POR &
Reference
Soft Start
VIN
VOUT
FB
On-Time One
Shot
REF
Min Off Time
DC Error
Correction
SW
Control
Logic
VOUT
+
+
Output
Discharge
LP#
PGND
Vref
SW
VCC
122% Vref
OC Limit
OVP
PG
FB
90% Vref
POK
50% Vref
UVP-2
75% Vref
UVP-1
Fault
Logic
VIN
VOUT
LDO
Control
LDO Switching
Over
PG
EN
LDO
Figure 1: Functional Block Diagram
NB679A Rev. 1.03
7/27/2017
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11
NB679A–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING
OPERATION
PWM Operation
The NB679A is a fully integrated, synchronous,
rectified, step-down, switch-mode converter with
a fixed 5.1V output. Constant-on-time (COT)
control provides fast transient response and
eases loop stabilization. At the beginning of each
cycle, the high-side MOSFET (HS-FET) is turned
on when the feedback voltage (VFB) is below the
reference voltage (VREF), which indicates
insufficient output voltage. The on period is
determined by the output voltage and the input
voltage to make the switching frequency fairly
constant over the input voltage range.
After the on period elapses, the HS-FET is turned
off or enters an off state. It is turned on again
when VFB drops below VREF. By repeating
operation this way, the converter regulates the
output voltage. The integrated low-side MOSFET
(LS-FET) is turned on when the HS-FET is in its
off state to minimize the conduction loss. A dead
short occurs between the input and GND if both
the HS-FET and the LS-FET are turned on at the
same time (shoot-through). In order to avoid
shoot-through, a dead time (DT) is generated
internally between the HS-FET off and the LSFET on period or the LS-FET off and the HS-FET
on period.
Internal compensation is applied for COT control
for stable operation even when ceramic
capacitors are used as output capacitors. This
internal compensation improves the jitter
performance without affecting the line or load
regulation.
Heavy-Load Operation (CCM)
Continuous conduction mode (CCM) occurs
when the output current is high, and the inductor
current is always above zero amps (see Figure 2).
When VFB is below VREF, the HS-FET is turned on
for a fixed interval. When the HS-FET is turned
off, the LS-FET is turned on until the next period.
In CCM operation, the switching frequency is
fairly constant (PWM mode).
Light-Load Power Save Mode (DCM)
When the load decreases, the inductor current
will decrease as well. Once the inductor current
reaches zero, the part transitions from CCM to
discontinuous conduction mode (DCM).
DCM operation is shown in Figure 3. When VFB is
below VREF, the HS-FET is turned on for a fixed
interval, which is determined by the one-shot on
timer. See Equation 1. When the HS-FET is
turned off, the LS-FET is turned on until the
inductor current reaches zero. In DCM operation,
the VFB does not reach VREF when the inductor
current is approaching zero. The LS-FET driver
turns into tri-state (high Z) when the inductor
current reaches zero. A current modulator takes
over the control of the LS-FET and limits the
inductor current to less than -1mA. Hence, the
output capacitors discharge slowly to GND
through the LS-FET. As a result, the efficiency
during a light-load condition is improved greatly.
The HS-FET is not turned on as frequently during
a light-load condition as it is during a heavy-load
condition (skip mode).
At a light-load or no-load condition, the output
drops very slowly, and the NB679A reduces the
switching frequency naturally, achieving high
efficiency at light load.
Figure 2: CCM Operation
NB679A Rev. 1.03
7/27/2017
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12
NB679A–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING
Figure 3: DCM Operation
As the output current increases from the lightload condition, the time period within which the
current modulator regulates becomes shorter.
The HS-FET is turned on more frequently. Hence,
the switching frequency increases accordingly.
The output current reaches the critical level when
the current modulator time is zero. The critical
level of the output current is determined using
Equation (1):
IOUT
(VIN VOUT ) VOUT
2 L FSW VIN
DC
Error
Configuring the EN Control
The NB679A has one EN pin to control the on/off
of the internal regulators and LDO. See Table 2
for the NB679A EN logics
Table 2: EN Control
(1)
The device enters PWM mode once the output
current exceeds the critical level. After that, the
switching frequency stays fairly constant over the
output current range.
DC Auto-Tune Loop
NB679A applies the DC auto-tune loop to
balance the DC error between VFB and VREF by
adjusting the comparator input REF to make VFB
always follow VREF. This loop is quite small, so it
improves the load and line regulation without
affecting the transient performance. The
relationship between VFB, VREF, and REF is
shown in Figure 4.
VFB
Once the part detects both the HS-FET and the
LS-FET are off (for about 32µs), it reduces the
Ton so as to keep Vout under regulation with
optimal efficiency. If the load continues to reduce,
the part discharges the Vout to make sure the FB
is smaller than 102% of the internal reference.
The HS-FET will turn on again once the internal
FB reaches VREF and then stops switching.
USM is selected by the EN voltage level. When
EN is in the range of 1.4V to 1.8V, it enters USM.
If EN is in the range of 2.6V to 3.6V, then it
operates in normal mode.
VREF
State
EN
VCC
VOUT
5V LDO
S0
1
ON
ON
ON
S3/S5
0
OFF
OFF
OFF
For automatic start-up, EN can be pulled up to
the input voltage through a resistive voltage
divider. See the “UVLO Protection” section for
additional details.
Configuring the LP# Control
The NB679A implements a voltage scaling
function on low-power mode by controlling LP#
(see Table 3).
Table 3: LP# Control
State
LP#
VOUT(V)
S0
S3/S5
1
0
5.1V
4.85V
REF
Soft Start (SS)
Figure 4: DC Auto-Tune Loop Operation
Large Duty Operation
The NB679A supports larger duty operation
(5.6Vin to 5.1Vout) by its internal Ton extension
function. When FB is lower than VREF and
Vin - Vo < 2V, the Ton can be extended,
extending the duty cycle. If FB > REF or Ton
meets its limitation, Ton will stop extending
The NB679A employs a soft-start (SS)
mechanism to ensure smooth output during
power-up. When EN goes high, the internal
reference voltage ramps up gradually; hence, the
output voltage ramps up smoothly as well. Once
the reference voltage reaches the target value,
the soft start finishes, and the part enters
steady-state operation.
Light-Load Ultrasonic Mode (USM)
Ultrasonic mode (USM) is designed to keep the
switching frequency above an audible frequency
area during light-load or no-load conditions.
NB679A Rev. 1.03
7/27/2017
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13
NB679A–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING
If the output is pre-biased to a certain voltage
during start-up, the IC disables the switching of
both the high-side and the low-side switches until
the voltage on the internal reference exceeds the
sensed output voltage at the internal FB node.
sets the valley level of the inductor current. Thus,
the load current at the over-current threshold (IOC)
can be calculated with Equation (2):
5V Linear Regulator
In an over-current condition, the current to the
load exceeds the current to the output capacitor;
thus the output voltage tends to fall off.
Eventually, it ends up crossing the under-voltage
protection threshold and shuts down. Fault
latching can be re-set by EN going low or the
power-cycling of VIN.
There is a built-in 100mA standby linear regulator
with a fixed output at 5V, controlled by EN. The
LDO is intended mainly for an auxiliary 5V supply
for the notebook system during standby mode.
Add a ceramic capacitor with a value between
4.7μF and 22µF placed close to the LDO pins to
stabilize the LDOs.
IOC I _ limit
Iinductor
2
(2)
Over/Under-Voltage Protection (OVP/UVP)
LDO Switch Over
When the output voltage becomes higher than
4.8V, and the power good is OK, the internal
LDO is switched over to VOUT by the internal
MOSFET. This helps reduce the power loss from
the LDO.
NB679A monitors the output voltage to detect
over and under voltage. Once the feedback
voltage becomes higher than 122% of the target
voltage, the OVP comparator output goes high,
and the circuit latches as the HS-FET driver turns
off, and the LS-FET driver turns on, acting as an
-2A current source.
Power Good (PG)
The NB679A has power-good (PG) output used
to indicate whether the output voltage of the buck
regulator is ready. PG is the open drain of a
MOSFET. It should be connected to VCC or
another voltage source through a resistor (e.g.
100k). After the input voltage is applied, the
MOSFET is turned on so that PG is pulled to
GND before SS is ready. After the FB voltage
reaches 95% of the REF voltage, PG is pulled
high after 750µs.
When the FB voltage drops to 85% of the REF
voltage, PG is pulled low.
When the feedback voltage drops below 75% of
the VREF but remains higher than 50% of the VREF,
the UVP-1 comparator output goes high. The part
latches if the FB voltage remains in this range for
about 32µs (latching the HS-FET off and the LSFET on). The LS-FET remains on until the
inductor current hits zero. During this period, the
valley current limit helps control the inductor
current.
Over-Current Protection (OCP)
NB679A has cycle-by-cycle over-current limiting
control. The current-limit circuit employs a
"valley" current-sensing algorithm. The part uses
the Rds(on) of the LS-FET as a current-sensing
element. If the magnitude of the current-sense
signal is above the current-limit threshold, the
PWM is not allowed to initiate a new cycle.
The trip level is fixed internally. The inductor
current is monitored by the voltage between GND
and SW. GND is used as the positive current
sensing node, so GND should be connected to
the source terminal of the bottom MOSFET.
When the feedback voltage drops below 50% of
the VREF, the UVP-2 comparator output goes high.
The part latches off directly after the comparator
and logic delay (latching the HS-FET off and the
LS-FET on). The LS-FET remains on until the
inductor current hits zero. Fault latching can be
re-set by EN going low or the power-cycling of
VIN.
UVLO Protection
The part starts up only when Vin is higher than
the UVLO rising threshold voltage. The part shuts
down when VIN is lower than the Vin falling
threshold. The UVLO protection is non-latch off.
Fault latching can be re-set by EN going low or
the power-cycling of VIN.
Since the comparison is done during the HS-FET
off and the LS-FET on state, the OC trip level
NB679A Rev. 1.03
7/27/2017
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14
NB679A–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING
If an application requires a higher under-voltage
lockout (UVLO), use EN to adjust the input
voltage UVLO using two external resistors (see
Figure 5). Note that there is a 600kΩ internal pull
low resistor on the EN Pin. The Calculation of the
two resistors need to consider this resistor.
It is recommended to use the enable resistors to
set the Vin falling threshold above 5.5V. The
rising threshold should be set to provide enough
hysteresis to allow for any input supply variations.
Figure 5: Adjustable UVLO
To avoid too much sink current on EN when
Rdown is not applied, the EN resistor (Rup) is
usually in the range of 1M-2MΩ. A typical pull-up
resistor is 2MΩ.
Thermal Shutdown
Thermal shutdown is employed in the NB679A.
The junction temperature of the IC is monitored
internally. If the junction temperature exceeds the
threshold value (140ºC, typically), the converter
shuts off. This is a non-latch protection. There is
about 25ºC hysteresis. Once the junction
temperature drops to about 115ºC, it initiates a
SS.
Output Discharge
NB679A discharges the output when EN is low,
or the controller is turned off by the protection
functions UVP, OCP, OCP, OVP, UVLO, and
thermal shutdown. The part discharges outputs
using an internal 6Ω MOSFET from Vout Pin, so
it is suggest that the Vout trace need to be over
20mil.
NB679A Rev. 1.03
7/27/2017
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15
NB679A–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING
APPLICATION INFORMATION
Input Capacitor
The input current to the step-down converter is
discontinuous, and therefore requires a capacitor
to supply the AC current to the step-down
converter while maintaining the DC input voltage.
Ceramic capacitors are recommended for best
performance and should be placed as close to
VIN as possible. Capacitors with X5R and X7R
ceramic dielectrics are recommended because
they are fairly stable with temperature
fluctuations.
The capacitors must have a ripple current rating
greater than the maximum input ripple current of
the converter. The input ripple current can be
estimated using Equation (3) and Equation (4):
ICIN IOUT
VOUT
V
(1 OUT )
VIN
VIN
(3)
ICIN
(4)
For simplification, choose an input capacitor with
an RMS current rating greater than half of the
maximum load current.
The input capacitor value determines the input
voltage ripple of the converter. If there is an input
voltage ripple requirement in the system, choose
the input capacitor that meets the specification.
The input voltage ripple can be estimated using
Equation (5) and Equation (6):
IOUT
V
V
VIN
OUT (1 OUT )
FSW CIN VIN
VIN
I
1
OUT
4 FSW CIN
(5)
(6)
Output Capacitor
An output capacitor is required to maintain the
DC output voltage. Ceramic or POSCAP
capacitors are recommended. The output voltage
ripple can be estimated using Equation (7):
NB679A Rev. 1.03
7/27/2017
When using ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance. The output voltage ripple is caused
mainly by the capacitance. For simplification, the
output voltage ripple can be estimated using
Equation (8):
VOUT
VOUT
V
(1 OUT )
2
8 FSW L COUT
VIN
(8)
When using POSCAP capacitors, the ESR
dominates the impedance at the switching
frequency.
The
output
ripple
can
be
approximated with Equation (9):
VOUT
V
(1 OUT ) RESR
FSW L
VIN
(9)
The maximum output capacitor limitation should
be considered in design application. For a small
soft-start time period (if the output capacitor
value is too high), the output voltage cannot
reach the design value during the soft-start time,
causing it to fail to regulate. The maximum output
capacitor value (Co_max) can be limited
approximately with Equation (10):
CO _ MAX (ILIM _ AVG IOUT ) Tss / VOUT
(10)
Where, ILIM_AVG is the average start-up current
during a soft-start period, and Tss is the soft-start
time.
Inductor
The worst-case conditions occur at VIN = 2VOUT,
where:
VIN
VOUT
V
1
(1 OUT ) (RESR
) (7)
FSW L
VIN
8 FSW COUT
VOUT
The worst-case condition occurs at VIN = 2VOUT,
where:
I
OUT
2
VOUT
The inductor is necessary to supply constant
current to the output load while being driven by
the switched input voltage. A larger value
inductor results in less ripple current, resulting in
a lower output ripple voltage. However, a larger
value inductor has a larger physical footprint, a
higher series resistance, and/or a lower
saturation current. A good rule for determining
the inductance value is to design the peak-topeak ripple current in the inductor to be in the
range of 30% to 50% of the maximum output
current, with the peak inductor current below the
maximum
switching
current
limit.
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16
NB679A–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING
The inductance value can be calculated with
Equation (11):
L
VOUT
V
(1 OUT )
FSW IL
VIN
(11)
Where ΔIL is the peak-to-peak inductor ripple
current.
The inductor should not saturate under the
maximum inductor peak current (including short
current), so it is suggested to choose Isat > 11A.
PCB LAYOUT GUIDELINES
Efficient PCB layout is critical for optimum IC
performance. For best results, refer to Figure 6
and follow the guidelines below. For more
information, refer to AN087.
1. Place the high current paths (GND, IN, and
SW) very close to the device with short, direct,
and wide traces.
2. Place the input capacitors as close to IN and
GND as possible.
3. Place the decoupling capacitor as close to
VCC and GND as possible. Keep the
switching node (SW) short and away from the
feedback network.
4. Keep the BST voltage path as short as
possible with a > 25 mil trace.
5. Keep the IN and GND pads connected with a
large copper plane to achieve better thermal
performance. Add several vias with a 10 mil
drill/18mil copper width close to the IN and
GND pads to help thermal dissipation.
6. Keep the Vout sense trace over 20 mil.
7. A 4-layer layout is strongly recommended to
achieve better thermal performance.
PG
0402
LP#
EN
12
11
AGND VCC
10
0603
9
VIN
8
1
Vin
SW
7
PGND
BST
SW
2
3
4
5
PG
NS
VOUT
6
LDO
PGND
VOUT
L
7mm*6.6mm
VOUT
Vout
Vout
0805
Figure 6: Recommend PCB Layout
NB679A Rev. 1.03
7/27/2017
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17
NB679A–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING
TYPICAL APPLICATION
3.3Ω
VIN
220nF
5.5V-24V
BST
VIN
VOUT
1.5μH
5.1V/8A
SW
22μF
LP#
GND
LP#
EN
NB679A
VOUT
EN
PGND
LDO
PG
5V/100mA
88μF
VCC
AGND
100kΩ
GND
4.7μF
1μF
Figure 7: Typical Application Schematic with Ceramic Output Capacitors
3.3Ω
VIN
5.5V-24V
220nF
BST
VIN
1.5μH
VOUT
5.1V/8A
SW
22μF
GND
LP#
LP#
EN
EN
5V/100mA
NB679A
150μF
VOUT
PGND
LDO
PG
VCC
AGND
100 kΩ
GND
4.7μF
1μF
Figure 8: Typical Application Schematic with POSCAP Output Capacitors—Recommended for Large-Duty
Operation Only
NB679A Rev. 1.03
7/27/2017
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18
NB679A–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING
PACKAGE OUTLINE DRAWING FOR 12L FCQFN (2X3MM) -6
PACKAGE INFORMATIONMF-PO-D-0212 revision 0.0
QFN-12 (2mm x 3mm)
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
BOTTOM VIEW
TOP VIEW
SIDE VIEW
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT
INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
NB679A Rev. 1.03
7/27/2017
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