NB679GD-Z

NB679 28V, Low Iq, High Current, Fixed 5V-8A Synchronous Buck Converter with 100 mA LDO DESCRIPTION FEATURES           The NB679 is a fully integrated, high-frequency, synchronous, rectified, step-down switch-mode converter with a fixed 5 V output. It offers a very compact solution to achieve 8 A continuous output current and 10 A peak output current over a wide input supply range with excellent load and line regulation. The NB679 operates at high efficiency over a wide output current load range based on MPS proprietary switching loss reduction technology and internal low Ron power MOSFETs.         Adaptive constant-on-time (COT) control mode provides fast transient response and eases loop stabilization. The DC auto-tune loop provides good load and line regulation. NB679 provides a fixed 5 V LDO, which can be used to power the external peripheries. Full protection features include OC limit, OVP, UVP, and thermal shutdown. Wide 5.5 V to 28 V Operating Input Range Fixed 5 V Vout Supports 5.5 V-5 V Ultrasonic Mode with Fs over 25 kHz 100 μA Low Quiescent Current 8 A Continous Output Current 10 A Peak Output Current Adaptive COT for Fast Transient DC Auto-Tune Loop for Load Regulation Stable with POSCAP and Ceramic Output Capacitors Built-In 5 V, 100 mA LDO with Switch Over 1% Reference Voltage Internal Soft Start Output Discharge 700 kHZ Switching Frequency OCP, OVP, UVP, and Thermal Shutdown. Latch-Off Reset via EN or Power Cycle QFN-12 (2mm x 3mm) Package APPLICATIONS The converter requires a minimum number of external components and is available in QFN 2mm x 3mm package.       Laptop Computers Tablet PCs Networking Systems Personal Video Recorders Flat Panel Television and Monitors Distributed Power Systems All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION 3.3 Ω VIN 220 nF 5.5 V-24 V BST VIN 22 μF ENLDO GND EN 5 V/ 100 mA VOUT 1.5 μH 5 V/8 A SW ENLDO NB679 88 μF VOUT EN PGND LDO PG VCC AGND 100 kΩ GND 4.7 μF 1μF NB679 Rev. 1.03 7/27/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 1 NB679— 28V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO ORDERING INFORMATION Part Number* Package Top Marking NB679GD QFN-12 (2mm x 3mm) See Below * For Tape & Reel, add suffix –Z (e.g. NB679GD–Z) TOP MARKING ALT: Product code of NB679GD Y: Year code LLL: Lot number PACKAGE REFERENCE ENLDO EN 12 11 AGND VCC 10 9 8 1 Vin SW 7 PGND NB679 Rev. 1.03 7/27/2017 BST 2 3 4 5 6 PG NC VOUT LDO www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 2 NB679— 28V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO (4) θJA θJC ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance Supply voltage (VIN) ....................................28 V VSW (DC) ......................................... -1 V to 26 V VSW (25 ns) .................................. -3.6 V to 28 V VBST ..................................................VSW +4.5 V VOUT,VLDO .................................... -0.3 V to 6.5 V All other pins ............................. -0.3 V to +4.5 V (2) Continuous power dissipation (TA=+25°C) QFN-12 (2mm x 3mm) ............................. 1.8 W Junction temperature ............................... 150C Lead temperature .................................... 260C Storage temperature ................ -65C to +150C NOTES: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. Recommended Operating Conditions QFN-12 (2mm x 3mm) ........... 70 ...... 15 ... C/W (3) Supply voltage .............................. 5.5 V to 24 V Operating junction temp. (TJ). .. -40°C to +125°C NB679 Rev. 1.03 7/27/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 3 NB679— 28V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO ELECTRICAL CHARACTERISTICS VIN = 12 V, TJ = 25C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units 1 2 μA Supply current Supply current (shutdown) IIN VEN = 0 V, VENLDO = 0 V, Supply current (quiescent) IIN VEN = VENLDO = 3.3 V, VOUT = 5.5 V 110 130 µA Supply current (standby) IIN VEN = 0 V, VENLDO = 3.3 V, ILDO = 0 A 60 80 μA MOSFET High-side switch on resistance HSRDS-ON 25 mΩ Low-side switch on resistance LSRDS-ON 12 mΩ Switch leakage SW LKG VEN = 0 V, VSW = 0 V 0 1 μA 11 12 A Current limit Low-side valley current limit ILIMIT 10 Switching frequency and timer Switching frequency Constant on timer (6) Minimum on time (6) Minimum off time FS Ton Vin = 10 V 600 TON_Min TOFF_Min 700 710 50 220 820 kHz ns ns ns Ultrasonic mode Ultrasonic mode operation period TUSM 20 30 40 µs VOVP VUVP-1 TUVP-1 VUVP-2 117% 70% 127% 80% 45% 122% 75% 32 50% 55% VREF VREF µs VREF VOUT_REF 4.95 5 5.05 V 1.7 2.5 ms Over-voltage and under-voltage protection OVP threshold UVP-1 threshold (6) UVP-1 foldback timer UVP-2 threshold Reference and soft start Vout REF voltage Soft-start time NB679 Rev. 1.03 7/27/2017 TSS EN to Vout OK www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 4 NB679— 28V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, TJ = 25C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units 1.2 1.3 150 1.3 1.4 V mV V Enable and UVLO EN rising threshold EN hysteresis ENLDO rising threshold VEN_H VEN-HYS VEN_H ENLDO hysteresis EN high limit @ USM EN low limit @ normal VEN-HYS EN input current 1.4 150 VEN_H_USM VEN_L_Normal IEN VIN under-voltage lockout threshold rising VIN under-voltage lockout threshold hysteresis 1.2 1.8 2.6 VEN = 2 V VEN = 0 V 5 0 VINVTH 4.45 VINHYS 450 mV V V μA 4.7 V mV LDO regulator LDO regulator LDO load regulation (5) LDO Iimit Switch Rdson (5) VLDO VEN = 0 V 4.85 5.12 VEN = 0 V, VLDO = 4.5 V 4.97 2 135 V % mA ILDO = 50 mA 0.9 1.2 Ω 3.6 3.7 V VEN = 0 V, LDO load =100 mA ILDO_Limit RSwitch VCC regulator VCC regulator VCC VCC load regulation 3.5 Icc = 5 mA 5 % Power good PG when FB rising (good) PG when FB falling (fault) PG when FB rising (fault) PG when FB falling (good) Power good low to high delay EN low to power good low delay Power good sink current capability Power good leakage current Thermal protection (5) Thermal shutdown (5) Thermal shutdown hysteresis PG_Rising(Good) PG_Falling(Fault) PG_Rising(Fault) PG_Falling(Good) PGTd PGTd_EN low VPG IPG_LEAK TSD TSD-HYS VFB rising, percentage of VFB VFB falling, percentage of VFB VFB rising, percentage of VFB VFB falling, percentage of VFB 95 85 115 105 750 % Sink 4 mA 5 0.4 μs μs V VPG = 3.3 V 5 μA 140 25 °C °C NOTE: 5) Guaranteed by design. NB679 Rev. 1.03 7/27/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 5 NB679— 28V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO PIN FUNCTIONS NB679 PIN # Name 1 VIN 2 PGND 3 PG 4 NC 5 VOUT 6 LDO 7 SW 8 BST 9 VCC 10 AGND 11 EN 12 ENLDO NB679 Rev. 1.03 7/27/2017 Description Supply voltage. VIN supplies power for the internal MOSFET and regulator. The NB679 operates from a 5.5 V to 24 V input rail. An input capacitor is needed to decouple the input rail. Use wide PCB traces and multiple vias to make the connection. Apply at least two layers for this input trace. Power ground. Use wide PCB traces and enough vias to handle the load current to make the connection. Make the PGND trace to the Vin decoupling capacitor as wide as possible. Power good output. The output of PG is an open-drain signal. It is high if the output voltage is higher than 95 percent of the nominal voltage or lower than 105 percent of the nominal voltage. No connection. VOUT is used to sense the output voltage of the buck regulator. Connect VOUT to the output capacitor of the regulator directly. Also, VOUT acts as the input of the internal LDO switch over power input. Keep the VOUT sensing trace far away from the SW node. Avoid vias on the VOUT sensing trace. A >25 mil trace is required. Internal LDO output. Decouple with a minimum 4.7 µF ceramic capacitor as close to LDO as possible. X7R or X5R grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. If ENLDO is high, it switches over to the LDO to buck after PG is ok. Switch output. Connect SW to the inductor and bootstrap capacitor. SW is driven up to the VIN voltage by the high-side switch during the on-time of the PWM duty cycle. The inductor current drives SW negative during the off-time. The on-resistance of the low-side switch and the internal diode fixes the negative voltage. Use wide and short PCB traces to make the connection. Try to minimize the area of the SW pattern. Bootstrap. A capacitor connected between SW and BS is required to form a floating supply across the high-side switch driver. Internal VCC LDO output. The driver and control circuits are powered from this voltage. Decouple with a minimum 1 µF ceramic capacitor as close to VCC as possible. X7R or X5R grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. Signal logic ground. Kelvin connection to PGND. Buck enable. EN is a digital input that turns the buck regulator on or off. When the power supply of the control circuit is ready, drive EN high to turn on the buck regulator, and drive it low to turn off the buck regulator. Connect EN to 3V3 through a pull-up resistor or a resistive voltage divider for automatic start-up. Do NOT float this pin. EN can be used to set USM. When EN is in the range of 1.4 V to 1.8 V, it enters USM. If EN is in the range of 2.6V to 3.6V, it operates in normal mode. LDO enable pin. ENLDO is pulled up internally to high. Leave ENLDO open to enable the LDO. Drive it low to turn off the LDO. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 6 NB679— 28V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO TYPICAL PERFORMANCE CHARACTERISTICS VINv= 19 V, VOUT = 5 V, L = 1.5 µH/10 mΩ, Fs = 700 kHz, TJ = +25°C, unless otherwise noted. NB679 Rev. 1.03 7/27/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 7 NB679— 28V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO TYPICAL PERFORMANCE CHARACTERISTICS VIN = 19 V, VOUT = 5 V, L = 1.5 µH/10 mΩ, Fs = 700 kHz, TJ=+25°C, unless otherwise noted. NB679 Rev. 1.03 7/27/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 8 NB679— 28V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO TYPICAL PERFORMANCE CHARACTERISTICS VIN= 19 V, VOUT = 5 V, L = 1.5 µH/10 mΩ, Fs = 700 kHz, TJ=+25°C, unless otherwise noted. NB679 Rev. 1.03 7/27/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 9 NB679— 28V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO FUNCTIONAL BLOCK DIAGRAM NB679 AGND EN VCC VIN VOUT VIN BST BSTREG POR & Reference Soft Start VIN VOUT FB On Time One Shot REF Min off time DC Error Correction SW Control Logic VOUT + + Output Discharge PGND Vref SW 122% Vref OC Limit OVP PG FB 90% Vref POK 50% Vref UVP-2 75% Vref UVP-1 Fault Logic VIN VOUT LDO Control LDO Switching Over PG LDO ENLDO Figure 1—Functional block diagram of NB679 NB679 Rev. 1.03 7/27/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 10 NB679— 28 V VIN, FIXED 5 V-8 A BUCK CONVERTER WITH LDO OPERATION PWM Operation The NB679 is a fully integrated, synchronous, rectified, step-down, switch-mode converter with a fixed 5 V output. Constant-on-time (COT) control provides fast transient response and eases loop stabilization. At the beginning of each cycle, the high-side MOSFET (HS-FET) is turned on when the feedback voltage (VFB) is below the reference voltage (VREF), which indicates insufficient output voltage. The on period is determined by the output voltage and the input voltage to make the switching frequency fairly constant over the input voltage range. After the on period elapses, the HS-FET is turned off or enters an off state. It is turned on again when VFB drops below VREF. By repeating operation this way, the converter regulates the output voltage. The integrated low-side MOSFET (LS-FET) is turned on when the HS-FET is in its off state to minimize the conduction loss. There is a dead short between the input and GND if both the HS-FET and the LS-FET are turned on at the same time (shoot-through). In order to avoid shoot-through, a dead time (DT) is generated internally between the HS-FET off and the LSFET on period or the LS-FET off and the HS-FET on period. Internal compensation is applied for COT control for stable operation even when ceramic capacitors are used as output capacitors. This internal compensation improves the jitter performance without affecting the line or load regulation. CCM Operation current is always above zero amps (see Figure 2). When VFB is below VREF, the HS-FET is turned on for a fixed interval. When the HS-FET is turned off, the LS-FET is turned on until the next period. In CCM operation, the switching frequency is fairly constant (PWM mode). DCM Operation When the load decreases, the inductor current will decrease as well. Once the inductor current reaches zero, the part transitions from CCM to discontinuous conduction mode (DCM). DCM operation is shown in Figure 3. When VFB is below VREF, the HS-FET is turned on for a fixed interval, which is determined by the one-shot on timer. See Equation (1). When the HS-FET is turned off, the LS-FET is turned on until the inductor current reaches zero. In DCM operation, VFB does not reach VREF when the inductor current approaches zero. The LS-FET driver turns into tri-state (high Z) when the inductor current reaches zero. A current modulator takes over the control of the LS-FET and limits the inductor current to less than -1 mA. Hence, the output capacitors discharge slowly to GND through the LS-FET. As a result, the efficiency at light-load is improved greatly. The HS-FET is not turned on as frequently during a light-load condition as it is during a heavy-load condition (skip mode). At a light-load or no-load condition, the output drops very slowly, and the NB679 reduces the switching frequency naturally, achieving high efficiency at light load. Figure 3—DCM operation Figure 2—CCM operation Continuous conduction mode (CCM) occurs when the output current is high, and the inductor NB679 Rev. 1.03 7/27/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 11 NB679, 28 V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO As the output current increases from the lightload condition, the time period within which the current modulator regulates becomes shorter. The HS-FET is turned on more frequently. Hence, the switching frequency increases accordingly. The output current reaches the critical level when the current modulator time is zero. The critical level of the output current is determined with Equation (1): IOUT  (VIN  VOUT )  VOUT 2  L  FSW  VIN (1) The device enters PWM mode once the output current exceeds the critical level. After that, the switching frequency stays fairly constant over the output current range. DC Auto-Tune Loop NB679 applies a DC auto-tune loop to balance the DC error between VFB and VREF by adjusting the comparator input REF to make VFB always follow VREF. The small DC loop improves the load and line regulation without affecting transient performance. The relationship between VFB, VREF, and REF is shown in Figure.4 VFB DC Error VREF REF Figure 4—DC auto-tune loop operation Large Duty Operation The NB679 supports larger duty operation (5.5 V5 V) by its internal Ton extension function. When the parts detects its FB is lower than Vref and Vin - Vo < 2 V, the Ton can be extended, extending the duty. If FB > REF or Ton reaches its limitation, Ton will stop extending. Light load Ultrasonic Mode Ultrasonic mode (USM) keeps the switching frequency above an audible frequency area during light-load or no-load conditions. Once the part detects both the HS-FET and the LS-FET are off (for about 30 µs), it shrinks the Ton so as to keep Vout under regulation with optimal efficiency. If the load continues to reduce, the part discharges the Vout to make sure FB is smaller than 102 percent of the internal reference. The HS-FET turns on again once the internal FB reaches VREF and then stops switching. NB679 Rev. 1.03 7/27/2017 USM is selected by the EN voltage level. When EN is in the range of 1.4 V to 1.8 V, it enters USM. If EN is in the range of 2.6 V to 3.6 V, it operates in normal mode. Configuring the EN Control The NB679 has two enable pins to control the on/off of the internal regulators and LDO. For NB679, the buck regulator and LDO are controlled by EN and ENLDO, respectively. For example, when the application is only used with the buck regulator, the buck regulator is realized by pulling ENLDO low, allowing the buck to be controlled by EN. See Table 2 for the NB679 EN logics. Table 2—ENLDO/EN control State ENLDO EN VCC VOUT 5V LDO S0 S3 S5 Others 1 1 0 0 1 0 0 1 ON ON OFF ON ON OFF OFF ON ON ON OFF OFF For automatic start-up, EN can be pulled up to the input voltage through a resistive voltage divider. Refer to the “UVLO Protection” section for more details. Soft Start (SS) The NB679 employs a soft-start (SS) mechanism to ensure smooth output during power-up. When EN becomes high, the internal reference voltage ramps up gradually; this causes the output voltage to ramp up smoothly as well. Once the reference voltage reaches the target value, the soft start finishes, and the part enters steadystate operation. If the output is pre-biased to a certain voltage during start-up, the IC disables the switching of both the high-side and low-side switches until the voltage on the internal reference exceeds the sensed output voltage at the internal FB node. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 12 NB679, 28 V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO 5 V Linear Regulator There is a built-in 100 mA standby linear regulator with a fixed output at 5 V, controlled by ENLDO. The 5 V LDO is intended mainly for an auxiliary 5 V supply for the notebook system during standby mode. Add a ceramic capacitor with a value between 4.7 μF and 22 µF placed close to the LDO pins to stabilize the LDOs. LDO Switch Over When the output voltage becomes higher than 4.8 V (and the power good is ok), the internal LDO is switched over to VOUT by the internal MOSFET. This helps reduce the power loss from the LDO. Power Good (PG) The NB679 has power good (PG) output used to indicate whether the output voltage of the buck regulator is ready. PG is the open drain of a MOSFET. It should be connected to VCC or another voltage source through a resistor (e.g. 100 k). After the input voltage is applied, the MOSFET is turned on so that PG is pulled to GND before SS is ready. After the FB voltage reaches 95 percent of the REF voltage, PG is pulled high after 750 µs. When the FB voltage drops to 85 percent of the REF voltage, PG is pulled low. Over-Current Protection (OCP) NB679 has cycle-by-cycle over-current limiting control. The current-limit circuit employs a "valley" current-sensing algorithm. The part uses the Rds(on) of the LS-FET as a current-sensing element. If the magnitude of the current-sense signal is above the current-limit threshold, the PWM is not allowed to initiate a new cycle. The trip level is fixed internally. The inductor current is monitored by the voltage between GND and SW. GND is used as the positive current sensing node, so GND should be connected to the source terminal of the bottom MOSFET. Since the comparison is done during the HS-FET off and LS-FET on state, the OC trip level sets the valley level of the inductor current. Thus, the load current at the over-current threshold (IOC) can be calculated with Equation (2): NB679 Rev. 1.03 7/27/2017 IOC  I _ limit  Iinductor 2 (2) In an over-current condition, the current to the load exceeds the current to the output capacitor; thus, the output voltage tends to fall off. Eventually, it ends up crossing the under-voltage protection threshold and shuts down. Fault latching can be re-set by EN going low or the power cycling of VIN. Over/Under-Voltage Protection (OVP/UVP) NB679 monitors the output voltage to detect over and under voltage. Once the feedback voltage becomes higher than 122 percent of the target voltage, the OVP comparator output goes high, and the circuit latches as the HS-FET driver turns off, and the LS-FET driver turns on, acting as an -1.8 A current source. When the feedback voltage drops below 75 percent of the Vref but remains higher than 50 percent, the UVP-1 comparator output goes high. The part is latched if the FB voltage remains in this range for about 32 µs (latching the HS-FET off and the LS-FET on). The LS-FET remains on until the inductor current hits zero. During this period, the valley current limit helps control the inductor current. When the feedback voltage drops below 50 percent of the Vref, the UVP-2 comparator output goes high, and the part is latched off directly after the comparator and logic delay (latching the HSFET off and the LS-FET on). The LS-FET remains on until the inductor current hits zero. Fault latching can be re-set by EN going low or the power cycling of VIN. UVLO Protection The part starts up only when the Vin voltage is higher than the UVLO rising threshold voltage. The part shuts down when VIN is lower than the Vin falling threshold. The UVLO protection is non-latch off. Fault latching can be re-set by EN going low or the power -cycling of VIN. If an application requires a higher under-voltage lockout (UVLO), use EN (see Figure 5) to adjust the input voltage UVLO by using two external resistors. It is recommended to use the enable resistors to set the Vin falling threshold above 5.5 V. The rising threshold should be www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 13 NB679, 28 V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO set to provide enough hysteresis to allow for any input supply variations. Figure 5—Adjustable UVLO To avoid too much sink current on EN, the EN resistor (Rup) is usually in the range of 1 M-2 MΩ. A typical pull-up resistor is 2 MΩ. Thermal Shutdown Thermal shutdown is employed in the NB679. The junction temperature of the IC is monitored internally. If the junction temperature exceeds the threshold value (140ºC, typically), the converter shuts off. This is a non-latch protection. There is about 25ºC hysteresis. Once the junction temperature drops to about 115ºC, it initiates a SS. Output Discharge NB679 discharges the output when EN is low, or the controller is turned off by the protection functions UVP, OCP, OCP, OVP, UVLO, and thermal shutdown. The part discharges outputs using an internal 6 Ω MOSFET. NB679 Rev. 1.03 7/27/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 14 NB679, 28 V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO APPLICATION INFORMATION Input Capacitor The input current to the step-down converter is discontinuous, and therefore requires a capacitor to supply the AC current to the step-down converter while maintaining the DC input voltage. Ceramic capacitors are recommended for best performance and should be placed as close to the VIN pin as possible. Capacitors with X5R and X7R ceramic dielectrics are recommended because they are fairly stable with temperature fluctuations. The capacitors must have a ripple-current rating greater than the maximum input ripple current of the converter. The input ripple current can be estimated with Equation (3) and Equation (4): ICIN  IOUT  VOUT V  (1  OUT ) VIN VIN (3) ICIN (4) For simplification, choose the input capacitor with an RMS current rating greater than half of the maximum load current. The input capacitor value determines the input voltage ripple of the converter. If there is an input voltage ripple requirement in the system, choose an input capacitor that meets the specification. The input voltage ripple can be estimated using Equation (5) and Equation (6): VIN  IOUT V V  OUT  (1  OUT ) FSW  CIN VIN VIN (5) The worst-case condition occurs at VIN = 2VOUT, where: VIN  I 1  OUT 4 FSW  CIN (6) Output Capacitor An output capacitor is required to maintain the DC output voltage. Ceramic or POSCAP capacitors are recommended. The output voltage ripple can be estimated using Equation (7): NB679 Rev. 1.03 7/27/2017 VOUT V 1  (1  OUT )  (RESR  ) (7) FSW  L VIN 8  FSW  COUT When using ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage ripple is caused mainly by the capacitance. For simplification, the output voltage ripple can be estimated using Equation (8): VOUT  VOUT V  (1  OUT ) 2 8  FSW  L  COUT VIN (8) When using POSCAP capacitors, the ESR dominates the impedance at the switching frequency. The output ripple can be approximated with Equation (9): VOUT  The worst-case condition occurs at VIN = 2VOUT, where: I  OUT 2 VOUT  VOUT V  (1  OUT )  RESR FSW  L VIN (9) The maximum output capacitor limitation should be considered in design application. For a small soft-start time period (if the output capacitor value is too high), the output voltage cannot reach the design value during the soft-start time, causing it to fail to regulate. The maximum output capacitor value (Co_max) can be limited approximately using Equation (10): CO _ MAX  (ILIM _ AVG  IOUT )  Tss / VOUT (10) Where, ILIM_AVG is the average start-up current during a soft-start period (it can be equivalent to the current limit value), and Tss is the soft-start time. Inductor The inductor is necessary to supply constant current to the output load while being driven by the switched input voltage. A larger value inductor results in less ripple current, resulting in a lower output ripple voltage. However, a larger value inductor has a larger physical footprint, a higher series resistance, and/or a lower saturation current. A good rule for determining the inductance value is to design the peak-topeak ripple current in the inductor to be in the range of 30 percent to 50 percent of the maximum output current, with the peak inductor current below the maximum switch current limit. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 15 NB679, 28 V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO The inductance value can be calculated using Equation (11): L VOUT V  (1  OUT ) FSW  IL VIN (11) 2. 3. Where ΔIL is the peak-to-peak inductor ripple current. The inductor should not saturate under the maximum inductor peak current (including short current), so it is suggested to choose Isat > 10 A. 4. PCB Layout Guidelines 5. Efficient PCB layout is critical for optimum IC performance. For best results, refer to Figure 6 and follow the guidelines below. For more information, refer to AN087. 1. Place the high-current paths (GND, IN, and SW) very close to the device with short, direct, and wide traces. The PGND trace should be 6. as wide as possible (This should be the number one priority). Place the input capacitors as close to IN and GND as possible on the same layer as the IC. Place the decoupling capacitor as close to VCC and GND as possible. Keep the switching node (SW) short and away from the feedback network. Keep the BST voltage path as short as possible with >50 mil trace. Keep the IN and GND pads connected with a large copper plane to achieve better thermal performance. Add several vias with 8 mil drill/16 mil copper width close to the IN and GND pads to help thermal dissipation. A 4-layer layout is strongly recommended to achieve better thermal performance. PG 0402 VIN ENLDO EN 12 11 AGND VCC 10 9 8 1 Vin SW 7 PGND BST SW 2 3 4 5 PG NS VOUT 6 LDO PGND VOUT Vout L 7mm*6.6mm Vout VOUT 0805 Figure 6—Recommended PCB layout NB679 Rev. 1.03 7/27/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 16 NB679, 28V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO TYPICAL APPLICATION 3.3 Ω VIN 220 nF 5.5 V-24 V BST VIN 22 μF ENLDO GND EN 5 V/ 100 mA VOUT 1.5 μH 5 V/8 A SW ENLDO NB679 VOUT EN 88 μF PGND LDO PG VCC AGND 100 kΩ GND 4.7 μF 1 μF Figure 7— Typical application schematic with ceramic output capacitors 3.3 Ω VIN 220 nF 5.5 V-24 V BST VIN 22 μF ENLDO GND EN 5V/100 mA VOUT 1.5 μH 5 V/8 A SW ENLDO NB679 150 μF VOUT EN PGND LDO PG VCC AGND 100 kΩ GND 4.7 μF 1 μF Figure 8— Typical application schematic with POSCAP output capacitors—recommended for large duty operation only. NB679 Rev. 1.03 7/27/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 17 NB679, 28V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO PACKAGE OUTLINE DRAWING FOR 12L FCQFN (2X3MM) -6 PACKAGE INFORMATIONMF-PO-D-0212 revision 0.0 QFN-12 (2mm x 3mm) PIN 1 ID MARKING PIN 1 ID INDEX AREA BOTTOM VIEW TOP VIEW SIDE VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 4) JEDEC REFERENCE IS MO-220. 5) DRAWING IS NOT TO SCALE. RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. NB679 Rev. 1.03 7/27/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 18