Si500D
D IFFERENTIAL O UTPUT S I L I C O N O SCILLATOR
Features
Quartz-free, MEMS-free, and PLL-free all-silicon
oscillator
Any output frequencies from 0.9 to 200 MHz
Short lead times
Excellent temperature stability (±20 ppm)
Highly reliable startup and operation
High immunity to shock and vibration
Low jitter: 80 MHz
Mid-level
Diff swing
Mid-level
—
—
—
—
34.0
19.3
14.9
25.3
36.0
22.2
16.5
29.3
mA
mA
mA
mA
—
33
36
mA
—
16
—
mA
—
—
—
—
—
46 – 13 ns/TCLK
—
—
—
VDD – 1.5
.720
—
24.5
24.3
22.2
9.7
1.0
—
—
—
1.1
—
—
N/A
27.7
26.7
25
10.7
1.9
54 + 13 ns/TCLK
460
800
1.6
VDD – 1.34
.880
—
mA
mA
mA
mA
mA
%
ps
ps
ns
V
VPK
V
Diff swing
.68
—
.95
VPK
Mid-level
Diff swing
Mid-level
Diff swing
Mid-level
Diff swing
DC termination per pad
VOH, sourcing 9 mA
VOL, sinking 9 mA
VOH
VOL
VOH
VOL
VOH
VOL
From time VDD crosses min spec
supply
1.15
0.25
0.85
0.25
0.35
0.65
45
VDD – 0.6
—
VTT + 0.375
—
VTT + 0.48
—
VTT + 0.48
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.26
0.45
0.96
0.45
0.425
0.82
55
—
0.6
—
VTT – 0.375
—
VTT – 0.48
—
VTT – 0.48
V
VPK
V
VPK
V
VPK
V
V
—
—
2
ms
—
—
250 + 3 x TCLK
ns
—
—
250 + 3 x TCLK
ns
—
—
12 + 3 x TCLK
µs
OE Deassertion to Clk Stop
Return from Output Driver Stopped
Mode
Return From Tri-State Time
V
V
V
Notes:
1. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4. VTT = .5 x VDD.
5. VTT = .45 x VDD.
2
Rev. 1.1
Si500D
Parameters
Condition
Min
Typ
Max
Units
—
—
2
Non-CMOS
—
1
2
CMOS, CL = 7 pF
—
1
3
—
0.6
1
—
0.7
1.5
ms
ps
RMS
ps
RMS
ps
RMS
ps
RMS
Return From Powerdown Time
Period Jitter (1-sigma)
Integrated Phase Jitter
1.0 MHz – min(20 MHz,
0.4 x FOUT),non-CMOS
1.0 MHz – min(20 MHz,
0.4 x FOUT),CMOS format
Notes:
1. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4. VTT = .5 x VDD.
5. VTT = .45 x VDD.
Rev. 1.1
3
Si500D
Package Specifications
Table 1. Package Diagram Dimensions (mm)
Dimension
A
A1
b
D
Min
0.80
0.00
0.59
3.20 BSC.
e
Nom
0.85
0.03
0.64
Dimension
L1
aaa
bbb
ccc
Min
0.00
—
—
—
Nom
0.05
—
—
—
Max
0.10
0.10
0.10
0.08
1.27 BSC.
ddd
—
—
0.10
E
4.00 BSC.
eee
—
—
0.05
L
0.95
1.00
Max
0.90
0.05
0.69
1.05
Table 2. Pad Connections
Table 3. Tri-State/Powerdown/Driver Stopped
Function on OE (3rd Option Code)
1
OE
2
NC—Make no external
connection to this pin
3
GND
4
Output
5
Complementary Output
6
VDD
Dimension
C1
E
X1
Y1
A
B
C
Open Active Active Active
D
E
F
Active
Active
Active
1
TriActive
State
Level
Powerdown
Active
Driver
Stopped
Active
0
TriPowerDriver
Active
Active
down
Stopped
Level State
0 C CC CC
T TTT TT
(mm)
2.70
1.27
0.75
1.55
Y Y WW
0 = Si500
CCCCC = mark code
TTTTTT = assembly manufacturing code
YY = year
WW = work week
Figure 2. Top Mark
Figure 1. Recommended Land Pattern
4
Rev. 1.1
Active
Si500D
Environmental Compliance
Parameter
Conditions/Test Method
Mechanical Shock
MIL-STD-883, Method 2002.4
Mechanical Vibration
MIL-STD-883, Method 2007.3 A
Resistance to Soldering Heat
MIL-STD-202, 260 C° for 8 seconds
Solderability
MIL-STD-883, Method 2003.8
Damp Heat
IEC 68-2-3
Moisture Sensitivity Level
J-STD-020, MSL 3
Ordering Information
The Si500D supports a variety of options including frequency, output format, supply voltage, and tristate/powerdown. Specific device configurations are programmed into the Si500D at time of shipment.
Configurations are specified using the figure below. Silicon Labs provides a web-based part number utility that can
be used to simplify part number configuration. Refer to www.silabs.com/SiliconXOPartnumber to access this tool.
The Si500D XO series is supplied in a ROHS-compliant, Pb-free, 6-pad, 3.2 x 4.0 mm package. Tape and reel
packaging is available as an ordering option.
500D
X
Si500
Differential
Oscillator
X
X
XXMXXXX
A
C
X
R
Frequency
R = Tape & Reel
Blank = Cut-Tape
xMxxxxx: fOUT < 10 MHz
xxMxxxx: 10 MHz < fOUT < 100 MHz
xxxMxxx: fOUT > 100 MHz
1st Option Code
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
U
V
W
X
VDD
Format
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
1.8
1.8
1.8
1.8
1.8
1.8
LVPECL
Low Power LVPECL
LVDS
HCSL
Dual Output CMOS
Differential CMOS
Dual Output SSTL
Differential SSTL
LVPECL
Low Power LVPECL
LVDS
HCSL
Dual Output CMOS
Differential CMOS
Dual Output SSTL
Differential SSTL
LVDS
HCSL
Dual Output CMOS
Differential CMOS
Dual Output SSTL
Differential SSTL
3rd Option Code
Tri-State/Powerdown/
Output Driver Stopped
A
OE active high/tristate
B
OE active low/tristate
C
OE active high/powerdown
D
OE active low/powerdown
E
OE active high/driver stopped
F
OE active low/driver stopped
2nd Option Code
A
B
Stability (ppm, max)
±150
±250
Oper. Temp Range
F
0 to 70 °C
*H
0 to 85 °C
Product Revision = C
Package
A
3.2 x 4.0 mm SMD
*Note: Only +250 ppm is supported.
Rev. 1.1
5
Si500D
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.3
Revision B to Revision C updated in Ordering Information
0 to 85 C° Operating Temperature Range option added
Revision 0.3 to Revision 1.0
Clarified SSTL specifications.
Revised Differential CMOS supply current values.
Clarified Differential CMOS supply current loading
conditions.
Revision 1.0 to Revision 1.1
Updated Ordering information for ±250 ppm from 0 to
+85 °C.
Updated jitter from 1.5 ps to 1.5 ps rms.
Updated operating temperature to include extended
commercial at 0 to +85 °C.
Updated features to include LVPECL, LVDS, and HCSL.
6
Rev. 1.1
ClockBuilder Pro
One-click access to Timing tools,
documentation, software, source
code libraries & more. Available for
Windows and iOS (CBGo only).
www.silabs.com/CBPro
Timing Portfolio
www.silabs.com/timing
SW/HW
Quality
Support and Community
www.silabs.com/CBPro
www.silabs.com/quality
community.silabs.com
Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without
further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Without prior
notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons. Such changes will not alter the specifications or the performance
of the product. Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly grant any license to
design or fabricate any integrated circuits. The products are not designed or authorized to be used within any FDA Class III devices, applications for which FDA premarket approval is required
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