530AC004687DG

Si5344H/42H Rev D H I G H -F R E Q U E N C Y, U LTRA -L O W J I T T E R A T T E N U A T O R C L O C K W I T H D IG ITA LLY - C O N T R O L L E D O S C I L L A T O R Features Pin Assignments Copyright © 2016 by Silicon Laboratories VDD I2C_SEL RSVD_GND NC NC VDDS 36 35 34 37 38 NC VDD 41 39 IN0 NC 40 IN0 30 LOS0 29 VDDS 28 LOS_XAXB 27 LOL 8 26 VDDS VDDA 9 25 OUT1 NC 10 24 OUT1 NC 11 23 VDDO1 21 22 NC 20 OUT0 VDD 19 18 VDDO0 OUT0 7 17 X2 VDDA GND Pad 16 6 15 5 RST 4 XB A1/SDO A0/CS X1 XA VDD I2C_SEL IN_SEL1 OUT3 OUT3 VDDO3 38 36 35 34 37 NC VDD 39 40 41 Si5344H 44QFN Top View IN1 1 33 INTR IN1 2 32 IN_SEL0 3 31 VDD OUT2 XGND 4 30 OUT2 XA 5 29 VDDO2 XB 6 28 LOS_XAXB XGND VDDA 7 27 LOL 8 26 VDDS VDDA 9 25 OUT1 NC 10 24 OUT1 NC 11 23 VDDO1 21 22 NC 18 VDDO0 OUT0 20 17 19 16 OUT0 VDD 15 RST GND Pad A1/SDO A0/CS This specialized jitter attenuating clock multiplier combines fourth-generation DSPLL with ultra-low phase jitter and MultiSynth™ technologies to enable high data rate coherent optical transceiver design. Up to four outputs can be assigned to High Frequency Mode capable of up to 2.75 GHz at 50 fs-rms typical phase jitter (1 MHz-40 MHz). Each output may also be configured as MultiSynth Mode any-frequency outputs when added frequency flexibility is required, such as clocking Forward Error Correction (FEC) while still delivering