533AC000066DG

Si 5 33 REVISION D D UAL -F R E Q U E N C Y C RY S TA L O S C I L L ATO R ( X O ) ( 1 0 MH Z TO 1 . 4 G H Z ) Features      Available with any-frequency output  frequencies from 10 MHz to 945 MHz and select frequencies to 1.4 GHz 2 selectable output frequencies  ® 3rd generation DSPLL with superior  jitter performance  3x better frequency stability than SAW-based oscillators  Pin 1 output enable (OE) Internal fixed crystal frequency ensures high reliability and low aging Available CMOS, LVPECL, LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options Industry-standard 5 x 7 mm package and pinout Pb-free/RoHS-compliant Applications Si5602 Ordering Information:  See page 7.  SONET/SDH  Networking  SD/HD video Clock and data recovery  FPGA/ASIC clock generation Pin Assignments: See page 6. Description The Si533 dual frequency XO utilizes Skyworks Solutions’ advanced DSPLL® circuitry to provide a low jitter clock at high frequencies. The Si533 is available with any-frequency output frequency from 10 to 945 MHz and select frequencies to 1400 MHz. Unlike a traditional XO, where a different crystal is required for each output frequency, the Si533 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. The Si533 IC based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. (Top View) OE 1 6 VDD FS 2 5 CLK– GND 3 4 CLK+ LVDS/LVPECL/CML Functional Block Diagram V DD Fixed Frequency XO OE CLK– CLK+ Any-frequency 10–1400 MHz DSPLL® Clock Synthesis FS OE 1 6 VDD FS 2 5 NC GND 3 4 CLK+ CMOS GND Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 4, 2022 Si5 33 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Units VDD 3.3 V option 2.97 3.3 3.63 V 2.5 V option 2.25 2.5 2.75 V 1.8 V option 1.71 1.8 1.89 V Output enabled LVPECL CML LVDS CMOS — — — — 111 99 90 81 121 108 98 88 Tristate mode — 60 75 mA VIH 0.75 x VDD — — V VIL — — 0.5 V –40 — 85 ºC Supply Voltage1 Supply Current IDD Output Enable (OE) and Frequency Select (FS)2 Operating Temperature Range TA mA Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details. 2. OE and FS pins include a 17 k pullup resistor to VDD. Table 2. CLK± Output Frequency Characteristics Parameter Nominal Frequency1,2 Initial Accuracy Symbol Test Condition Min Typ Max Units fO LVPECL/LVDS/CML 10 — 945 MHz CMOS 10 — 160 MHz Measured at +25 °C at time of shipping — ±1.5 — ppm –7 –20 –50 — — — +7 +20 +50 ppm Frequency drift over first year — — ±3 ppm Frequency drift over 20 year life — — ±10 ppm fi Temperature Stability1,3 Aging fa Notes: 1. See Section 3. "Ordering Information" on page 7 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Selectable parameter specified by part number. 4. Time from powerup or tristate mode to fO. 2 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 4, 2022 Si533 Table 2. CLK± Output Frequency Characteristics (Continued) Parameter Symbol Total Stability Test Condition Min Typ Max Units Temp stability = ±7 ppm — — ±20 ppm Temp stability = ±20 ppm — — ±31.5 ppm Temp stability = ±50 ppm — — ±61.5 ppm Powerup Time4 tOSC — — 10 ms Settling Time After FS Change tFRQ — — 10 ms Notes: 1. See Section 3. "Ordering Information" on page 7 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Selectable parameter specified by part number. 4. Time from powerup or tristate mode to fO. Table 3. CLK± Output Levels and Symmetry Parameter Symbol Test Condition Min Typ Max Units VO mid-level VDD – 1.42 — VDD – 1.25 V VOD swing (diff) 1.1 — 1.9 VPP VSE swing (single-ended) 0.55 — 0.95 VPP VO mid-level 1.125 1.20 1.275 V VOD swing (diff) 0.5 0.7 0.9 VPP 2.5/3.3 V option mid-level — VDD – 1.30 — V 1.8 V option mid-level — VDD – 0.36 — V 2.5/3.3 V option swing (diff) 1.10 1.50 1.90 VPP 1.8 V option swing (diff) 0.35 0.425 0.50 VPP VOH IOH = 32 mA 0.8 x VDD — VDD V VOL IOL = 32 mA — — 0.4 V tR, tF LVPECL/LVDS/CML — — 350 ps CMOS with CL = 15 pF — 1 — ns 45 — 55 % LVPECL Output Option1 LVDS Output Option2 VO CML Output Option2 VOD CMOS Output Option3 Rise/Fall time (20/80%) SYM Symmetry (duty cycle) LVPECL: LVDS: CMOS: VDD – 1.3 V (diff) 1.25 V (diff) VDD/2 Notes: 1. 50  to VDD – 2.0 V. 2. Rterm = 100  (differential). 3. CL = 15 pF Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 4, 2022 3 Si5 33 Table 4. CLK± Output Phase Jitter Parameter Symbol Test Condition Min Typ Max Units Phase Jitter (RMS)1 for FOUT > 500 MHz J 12 kHz to 20 MHz (OC-48) — 0.25 0.40 ps 50 kHz to 80 MHz (OC-192) — 0.26 0.37 ps Phase Jitter (RMS)1 for FOUT of 125 to 500 MHz J 12 kHz to 20 MHz (OC-48) — 0.36 0.50 ps — 0.34 0.42 ps Phase Jitter (RMS) for FOUT of 10 to 160 MHz CMOS Output Only J 12 kHz to 20 MHz (OC-48)2 — 0.62 — ps 50 kHz to 20 MHz2 — 0.61 — ps 50 kHz to 80 MHz (OC-192) 2 Notes: 1. Refer to AN256 for further information. 2. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT 000100, f0 is 644.53125 MHz (lower frequency) and f1 is 693.48299 (higher frequency), with a 3.3V supply and LVPECL output. Temperature stability is specified as ± 20 ppm. The part is specified for a -40 to +85 C° ambient temperature range operation and is shipped in tape and reel format. Figure 1. Part Number Convention Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 4, 2022 7 Si5 33 4. Outline Diagram and Suggested Pad Layout Figure 2 illustrates the package details for the Si533. Table 10 lists the values for the dimensions shown in the illustration. Figure 2. Si533 Outline Diagram Table 10. Package Diagram Dimensions (mm) Dimension A b c D D1 e E E1 H L p R aaa bbb ccc ddd eee 8 Min 1.50 1.30 0.50 4.30 6.10 0.55 1.17 1.80 Nom 1.65 1.40 0.60 5.00 BSC 4.40 2.54 BSC 7.00 BSC 6.20 0.65 1.27 — 0.70 REF 0.15 0.15 0.10 0.10 0.05 Max 1.80 1.50 0.70 4.50 6.30 0.75 1.37 2.60 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 4, 2022 Si533 5. Si533 Mark Specification Figure 3 illustrates the mark specification for the Si533. Table 11 lists the line information. Figure 3. Mark Specification Table 11. Si53x Top Mark Description Line Position 1 1–10 “533” 2 1–10 Si533: Option1 + Option2 + ConfigNum(6) + Temp 3 Description Trace Code Position 1 Pin 1 orientation mark (dot) Position 2 Product Revision (D) Position 3–6 Tiny Trace Code (4 alphanumeric characters per assembly release instructions) Position 7 Year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7) Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site Position 10 “+” to indicate Pb-Free and RoHS-compliant Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 4, 2022 9 Si5 33 6. 6-Pin PCB Land Pattern Figure 4 illustrates the 6-pin PCB land pattern for the Si533. Table 12 lists the values for the dimensions shown in the illustration. Figure 4. Si533 PCB Land Pattern Table 12. PCB Land Pattern Dimensions (mm) Dimension Min Max D2 5.08 REF e 2.54 BSC E2 4.15 REF GD 0.84 — GE 2.00 — VD 8.20 REF VE 7.30 REF X 1.70 TYP Y 2.15 REF ZD — 6.78 ZE — 6.30 Notes: 1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification. 2. Land pattern design based on IPC-7351 guidelines. 3. All dimensions shown are at maximum material condition (MMC). 4. Controlling dimension is in millimeters (mm). 10 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 4, 2022 Si533 DOCUMENT CHANGE LIST Revision 1.0 to Revision 1.1  Updated Table 1, “Recommended Operating Conditions,” on page 2. Revision 1.3 to Revision 1.4 June, 2018  Changed “Trays” to “Coil Tape” in section 3. “Ordering Information”. Device maintains stable operation over –40 to +85 ºC operating temperature range. Supply current specifications updated for revision D.  Updated Table 2, “CLK± Output Frequency Characteristics,” on page 2. Added specification for ±20 ppm lifetime stability (±7 ppm temperature stability) XO.  Updated Table 3, “CLK± Output Levels and Symmetry,” on page 3. Updated LVDS differential peak-peak swing specifications.  Updated Table 4, “CLK± Output Phase Jitter,” on page 4.  Updated Table 5, “CLK± Output Period Jitter,” on page 4. Revised period jitter specifications. Updated Table 9, “Absolute Maximum Ratings1,” on page 5 to reflect the soldering temperature time at 260 ºC is 20–40 sec per JEDEC J-STD-020C.  Updated 3. "Ordering Information" on page 7.  Changed  ordering instructions to revision D. Added 5. "Si533 Mark Specification" on page 9. Revision 1.1 to Revision 1.2         Updated 2.5 V/3.3 V and 1.8 V CML output level specifications for Table 3 on page 3. Added footnotes clarifying max offset frequency test conditions for Table 4 on page 4. Removed the words "Differential Modes: LVPECL/LVDS/CML" in the footnote referring to AN256 in Table 4 on page 4. Added CMOS phase jitter specs to Table 4 on page 4. Updated Table 7 on page 5 to include the "Moisture Sensitivity Level" and "Contact Pads" rows. Revised Figure 2 on page 8 to reflect current package outline diagram. Updated Figure 3 and Table 11 on page 9 to reflect specific marking information. Previously, Figure 3 was generic. Updated contact information on page 12. Revision 1.2 to Revision 1.3  Added Table 8, “Thermal Characteristics,” on page 5. Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 11 Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 4, 2022 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). skyworksinc.com/CBPro Portfolio SW/HW Quality Support & Resources skyworksinc.com skyworksinc.com/CBPro skyworksinc.com/quality skyworksinc.com/support Copyright © 2022 Skyworks Solutions, Inc. All Rights Reserved. Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer. 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