Rev. 1. 2Si 512/ 513
D U A L F REQUENCY C RYSTAL O SCILLATOR ( XO )
100 kH Z TO 25 0 M H Z
Features
Supports any frequency from
100 kHz to 250 MHz
Two selectable output frequencies
Low-jitter operation
2 to 4 week lead times
Total stability includes 10-year
aging
Comprehensive production test
coverage includes crystal ESR and
DLD
On-chip LDO regulator for power
supply noise filtering
3.3, 2.5, or 1.8 V operation
Differential (LVPECL, LVDS,
HCSL) or CMOS output options
Optional integrated 1:2 CMOS
fanout buffer
Runt suppression on OE and
power on
Industry standard 5x7, 3.2x5, and
2.5x3.2 mm packages
Pb-free, RoHS compliant
–40 to 85 oC operation
Si5602
2.5x3.2mm
5x7mm and 3.2x5mm
Ordering Information:
Applications
See page 13.
SONET/SDH/OTN
Gigabit Ethernet
Fibre Channel/SAS/SATA
PCI Express
Broadcast video
Switches/routers
Telecom
FPGA/ASIC clock generation
Pin Assignments:
See page 12.
Description
The Si512/513 dual frequency XO utilizes Skyworks Solutions' advanced
PLL technology to provide any frequency from 100 kHz to 250 MHz. Unlike a
traditional XO where a different crystal is required for each output frequency,
the Si512/513 uses one fixed crystal and Skyworks Solutions’ proprietary
any-frequency synthesizer to generate any frequency across this range. This
IC-based approach allows the crystal resonator to provide enhanced
reliability, improved mechanical robustness, and excellent stability. In
addition, this solution provides superior supply noise rejection, simplifying
low jitter clock generation in noisy environments. The Si512/513 is factoryconfigurable for a wide variety of user specifications, including frequency,
supply voltage, output format, output enable polarity, and stability. Specific
configurations are factory-programmed at time of shipment, eliminating long
lead times and non-recurring engineering charges associated with custom
frequency oscillators.
Functional Block Diagram
Power Supply Filtering
Fixed
Frequency
Oscillator
1
6
VDD
OE
2
5
NC
GND
3
4
CLK
Si512 CMOS Dual XO
OE
1
6
VDD
FS
2
5
NC
GND
3
4
CLK
Si513 CMOS Dual XO
FS
1
6
VDD
OE
2
5
CLK–
GND
3
4
CLK+
Si512 LVDS/LVPECL/HCSL/CMOS
Dual XO
VDD
OE
FS
Any-Frequency
0.1 to 250 MHz
DSPLL® Synthesis
CLK+
CLK–
OE
1
6
VDD
FS
2
5
CLK–
GND
3
4
CLK+
Si513 LVDS/LVPECL/HCSL/CMOS
Dual XO
FS
GND
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TA B L E
Section
OF
C ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages . . . . . . . . . . . . . . 10
3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1. Dual CMOS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. Package Outline Diagram, 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8. PCB Land Pattern: 3.2 x 5.0 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11.1. Si512/513 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2
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1. Electrical Specifications
Table 1. Operating Specifications
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Supply Voltage
Supply Current
Symbol
Test Condition
Min
Typ
Max
Units
VDD
3.3 V option
2.97
3.3
3.63
V
2.5 V option
2.25
2.5
2.75
V
1.8 V option
1.71
1.8
1.89
V
CMOS, 100 MHz,
single-ended
—
21
26
mA
LVDS
(output enabled)
—
19
23
mA
LVPECL
(output enabled)
—
39
43
mA
HCSL
(output enabled)
—
41
44
mA
Tristate
(output disabled)
—
—
18
mA
IDD
FS, OE "1" Setting
VIH
See Note
0.80 x VDD
—
—
V
FS, OE "0" Setting
VIL
See Note
—
—
0.20 x VDD
V
FS, OE Internal PullUp/Pull-Down Resistor*
RI
—
45
—
k
Operating Temperature
TA
–40
—
85
o
C
Note: Active high and active low polarity OE options available. Active high uses internal pull-up. Active low uses internal pulldown. See ordering information on page 12.
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Table 2. Output Clock Frequency Characteristics
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Nominal Frequency
Symbol
Test Condition
Min
Typ
Max
Units
FO
CMOS, Dual CMOS
0.1
—
212.5
MHz
FO
LVDS/LVPECL/HCSL
0.1
—
250
MHz
Frequency Stability Grade C
–30
+30
ppm
Frequency Stability Grade B
–50
+50
ppm
Frequency Stability Grade A
–100
+100
ppm
Frequency Stability Grade C
–20
+20
ppm
Frequency Stability Grade B
–25
+25
ppm
Frequency Stability Grade A
–50
+50
ppm
Total Stability*
Temperature Stability
Startup Time
TSU
Minimum VDD to output
frequency (FO) within specification
—
—
10
ms
Disable Time
TD
FO 10 MHz
—
—
5
µs
FO < 10 MHz
—
—
40
µs
FO 10 MHz
—
—
20
µs
FO < 10 MHz
—
—
60
µs
—
—
10
ms
Enable Time
Settling Time after FS
Change
TE
tFRQ
*Note: Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and
vibration (not under operation), and 10 years aging at 40 °C.
4
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Table 3. Output Clock Levels and Symmetry
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
CMOS Output Logic
High
VOH
0.85 x VDD
—
—
V
CMOS Output Logic
Low
VOL
—
—
0.15 x VDD
V
CMOS Output Logic
High Drive
IOH
3.3 V
–8
—
—
mA
2.5 V
–6
—
—
mA
1.8 V
–4
—
—
mA
3.3 V
8
—
—
mA
2.5 V
6
—
—
mA
1.8 V
4
—
—
mA
0.1 to 125 MHz,
CL = 15 pF
—
0.8
1.2
ns
0.1 to 212.5 MHz,
CL = no load
—
0.6
0.9
ns
CMOS Output Logic
Low Drive
IOL
CMOS Output Rise/Fall
Time
(20 to 80% VDD)
TR/TF
LVPECL/HCSL Output
Rise/Fall Time
(20 to 80% VDD)
TR/TF
—
—
565
ps
LVDS Output Rise/Fall
Time
(20 to 80% VDD)
TR/TF
—
—
800
ps
LVPECL Output
Common Mode
VOC
50 to VDD – 2 V,
single-ended
—
VDD –
1.4 V
—
V
LVPECL Output Swing
VO
50 to VDD – 2 V,
single-ended
0.55
0.8
0.90
VPPSE
LVDS Output Common
Mode
VOC
100 line-line, VDD = 3.3/2.5 V
1.13
1.23
1.33
V
100 line-line, VDD = 1.8 V
0.83
0.92
1.00
V
LVDS Output Swing
VO
Single-ended, 100 differential
termination
0.25
0.35
0.45
VPPSE
HCSL Output Common
Mode
VOC
50 to ground
0.35
0.38
0.42
V
HCSL Output Swing
VO
Single-ended
0.58
0.73
0.85
VPPSE
Duty Cycle
DC
All Output Formats
48
50
52
%
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Table 4. Output Clock Jitter and Phase Noise (LVPECL)
VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = LVPECL
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Period Jitter
(RMS)
JPRMS
10k samples1
—
—
1.3
ps
Period Jitter
(Pk-Pk)
JPPKPK
10k samples1
—
—
11
ps
Phase Jitter
(RMS)
φJ
1.875 MHz to 20 MHz integration
bandwidth2 (brickwall)
—
0.31
0.5
ps
12 kHz to 20 MHz integration bandwidth (brickwall)2
—
0.8
1.0
ps
100 Hz
—
–86
—
dBc/Hz
1 kHz
—
–109
—
dBc/Hz
10 kHz
—
–116
—
dBc/Hz
100 kHz
—
–123
—
dBc/Hz
1 MHz
—
–136
—
dBc/Hz
10 kHz sinusoidal noise
—
3.0
—
ps
100 kHz sinusoidal noise
—
3.5
—
ps
500 kHz sinusoidal noise
—
3.5
—
ps
1 MHz sinusoidal noise
—
3.5
—
ps
LVPECL output, 156.25 MHz,
offset > 10 kHz
—
–75
—
dBc
Phase Noise,
156.25 MHz
Additive RMS
Jitter Due to
External Power
Supply Noise3
Spurious
φN
JPSR
SPR
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
3. 156.25 MHz. Increase in jitter on output clock due to sinewave noise added to VDD (2.5/3.3 V = 100 mVPP).
6
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Table 5. Output Clock Jitter and Phase Noise (LVDS)
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = LVDS
Symbol
Test Condition
Min
Typ
Max
Unit
Period Jitter
(RMS)
JPRMS
10k samples1
—
—
2.1
ps
Period Jitter
(Pk-Pk)
JPPKPK
10k samples1
—
—
18
ps
Phase Jitter
(RMS)
φJ
1.875 MHz to 20 MHz integration
bandwidth2 (brickwall)
—
0.25
0.55
ps
12 kHz to 20 MHz integration bandwidth2 (brickwall)
—
0.8
1.0
ps
100 Hz
—
–86
—
dBc/Hz
1 kHz
—
–109
—
dBc/Hz
10 kHz
—
–116
—
dBc/Hz
100 kHz
—
–123
—
dBc/Hz
1 MHz
—
–136
—
dBc/Hz
LVPECL output, 156.25 MHz,
offset>10 kHz
—
–75
—
dBc
Parameter
Phase Noise,
156.25 MHz
Spurious
φN
SPR
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
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Table 6. Output Clock Jitter and Phase Noise (HCSL)
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = HCSL
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Period Jitter
(RMS)
JPRMS
10k samples*
—
—
1.2
ps
Period Jitter
(Pk-Pk)
JPPKPK
10k samples*
—
—
11
ps
Phase Jitter
(RMS)
φJ
1.875 MHz to 20 MHz integration
bandwidth*(brickwall)
—
0.25
0.30
ps
12 kHz to 20 MHz integration bandwidth* (brickwall)
—
0.8
1.0
ps
100 Hz
—
–90
—
dBc/Hz
1 kHz
—
–112
—
dBc/Hz
10 kHz
—
–120
—
dBc/Hz
100 kHz
—
–127
—
dBc/Hz
1 MHz
—
–140
—
dBc/Hz
LVPECL output, 156.25 MHz,
offset>10 kHz
—
–75
—
dBc
Phase Noise,
156.25 MHz
Spurious
φN
SPR
*Note: Applies to an output frequency of 100 MHz.
Table 7. Output Clock Jitter and Phase Noise (CMOS, Dual CMOS)
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = CMOS, Dual CMOS
Parameter
Phase Jitter
(RMS)
Phase Noise,
156.25 MHz
Spurious
Symbol
Test Condition
Min
Typ
Max
Unit
φJ
1.875 MHz to 20 MHz integration
bandwidth2 (brickwall)
—
0.25
0.35
ps
12 kHz to 20 MHz integration bandwidth2 (brickwall)
—
0.8
1.0
ps
100 Hz
—
–86
—
dBc/Hz
1 kHz
—
–108
—
dBc/Hz
10 kHz
—
–115
—
dBc/Hz
100 kHz
—
–123
—
dBc/Hz
1 MHz
—
–136
—
dBc/Hz
LVPECL output, 156.25 MHz,
offset>10 kHz
—
–75
—
dBc
φN
SPR
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 MHz.
8
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Table 8. Environmental Compliance and Package Information
Parameter
Conditions/Test Method
Mechanical Shock
MIL-STD-883, Method 2002
Mechanical Vibration
MIL-STD-883, Method 2007
Solderability
MIL-STD-883, Method 2003
Gross and Fine Leak
MIL-STD-883, Method 1014
Resistance to Solder Heat
MIL-STD-883, Method 2036
Contact Pads
Gold over Nickel
Table 9. Thermal Characteristics
Parameter
CLCC, Thermal Resistance Junction to Ambient
2.5x3.2mm, Thermal Resistance Junction to Ambient
Symbol
Test Condition
Value
Unit
JA
Still air
110
°C/W
JA
Still air
164
°C/W
Table 10. Absolute Maximum Ratings1
Parameter
Symbol
Rating
Units
TAMAX
85
oC
TS
–55 to +125
VDD
–0.5 to +3.8
V
VI
–0.5 to VDD + 0.3
V
ESD Sensitivity (HBM, per JESD22-A114)
HBM
2
kV
Soldering Temperature (Pb-free profile)2
TPEAK
260
TP
20–40
Maximum Operating Temperature
Storage Temperature
Supply Voltage
Input Voltage (any input pin)
Soldering Temperature Time at TPEAK (Pb-free profile)2
o
C
o
C
sec
Notes:
1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation or
specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended
periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020E.
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2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages
Reflow of Skyworks Solutions' components should be done in a manner consistent with the IPC/JEDEC J-STD-20E
standard. The temperature of the package is not to exceed the classification Temperature provided in the standard.
The part should not be within -5°C of the classification or peak reflow temperature (TPEAK) for longer than 30
seconds. Key to maintaining the integrity of the component is providing uniform heating and cooling of the part
during reflow and rework. Uniform heating is achieved through having a preheat soak and controlling the
temperature ramps in the process. J-STD-20E provides minimum and maximum temperatures and times for the
preheat/Soak step that need to be followed, even for rework. The entire assembly area should be heated during
rework. Hot air should be flowed from both the bottom of the board and the top of the component. Heating from the
top only will cause un-even heating of component and can lead to part integrity issues. Temperature Ramp-up rate
are not to exceed 3°C/second. Temperature ramp-down rates from peak to final temperature are not to exceed
6°C/second. Time from 25°C to peak temperature is not to exceed 8 min for Pb-free solders.
10
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3. Pin Descriptions
FS
1
6
VDD
OE
1
6
VDD
FS
1
6
VDD
OE
1
6
VDD
OE
2
5
NC
FS
2
5
NC
OE
2
5
CLK–
FS
2
5
CLK–
GND
3
4
CLK
GND
3
4
CLK
GND
3
4
CLK+
GND
3
4
CLK+
Si512 CMOS
Si513 CMOS
Si512 LVDS/LVPECL/
HCSL/ Dual CMOS*
Si513 LVDS/LVPECL/
HCSL/Dual CMOS*
*Note: Supports integrated 1:2 CMOS buffer. See section 2.1 “3.1. Dual CMOS Buffer” and section 3 “4. Ordering Information”.
Pin
Table 11. Si512 Pin Descriptions (CMOS, OE Pin 2)
Name
CMOS Function
1
FS
Frequency Selected.
0 = First frequency selected.
1 = Second frequency selected.
2
OE
Output Enable. Internal pull-up for OE active high. Pulldown for OE active low. See ordering information.
3
GND
Electrical and Case Ground.
4
CLK
Clock Output.
5
NC
No connect. Make no external connection to this pin.
6
VDD
Power Supply Voltage.
Pin
Table 12. Si513 Pin Descriptions (CMOS, OE Pin 1)
Name
CMOS Function
1
OE
Output Enable. Internal pull-up for OE active high. Pulldown for OE active low. See ordering information.
2
FS
Frequency Selected.
0 = First frequency selected.
1 = Second frequency selected.
3
GND
Electrical and Case Ground.
4
CLK
Clock Output.
5
NC
No connect. Make no external connection to this pin.
6
VDD
Power Supply Voltage.
Pin
Name
1
FS
Frequency Selected.
0 = First frequency selected.
1 = Second frequency selected.
2
OE
Output Enable. Internal pull-up for OE active high. Pulldown for OE active low. See ordering information.
3
GND
Electrical and Case Ground.
4
CLK+
Clock Output.
5
CLK–
Complementary Clock Output.
6
VDD
Table 13. Si512 Pin Descriptions (OE Pin 2)
LVPECL/LVDS/HCSL/Dual CMOS Function
Power Supply Voltage.
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Table 14. Si513 Pin Descriptions (OE Pin 1)
Pin
Name
LVPECL/LVDS/HCSL/Dual CMOS Function
1
OE
Output Enable. Internal pull-up for OE active high. Pulldown for OE active low. See ordering information.
2
FS
Frequency Selected.
0 = First frequency selected.
1 = Second frequency selected.
3
GND
Electrical and Case Ground.
4
CLK+
Clock Output.
5
CLK–
Complementary Clock Output.
6
VDD
Power Supply Voltage.
3.1. Dual CMOS Buffer
Dual CMOS output format ordering options support either complementary or in-phase output signals. This feature
enables replacement of multiple XOs with a single Si512/13 device.
~
~
Complementary
Outputs
In-Phase
Outputs
Figure 1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs
12
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Re v. 1 .2S i512/ 513
4. Ordering Information
The Si512/513 supports a wide variety of options including frequency, stability, output format, and VDD. Specific
device configurations are programmed into the Si512/513 at time of shipment. Configurations can be specified
using the Part Number Configuration chart below. Skyworks Solutions provides a web browser-based part number
configuration utility to simplify this process. Refer to www.skyworksinc.com/products/timing-oscillators and click
“Customize” in the product table. The Si512/513 XO series is supplied in industry-standard, RoHS compliant, leadfree, 2.5 x 3.2 mm, 3.2 x 5.0 mm, and 5 x 7 mm packages. Tape and reel packaging is an ordering option.
Series
Output Format
Package
514
LVPECL, LVDS, HCSL,
CMOS, Dual CMOS
6-pin
1st Option Code:
Output Format
514 X X X
VDD
Output Format
A
3.3V
LVPECL
B
3.3V
LVDS
C
3.3V
CMOS
D
3.3V
HCSL
E
2.5V
LVPECL
F
2.5V
LVDS
G
2.5V
A = Revision: A
G = Temp Range: -40°C to 85°C
R = Tape & Reel; Blank = Coil Tape
2.5V
HCSL
J
1.8V
LVDS
K
1.8V
CMOS
L
1.8V
HCSL
M
3.3V
Dual CMOS (In-phase)
N
3.3V
Dual CMOS (Complementary)
P
2.5V
Dual CMOS (In-phase)
Q
2.5V
Dual CMOS (Complementary)
R
1.8V
Dual CMOS (In-phase)
S
1.8V
Dual CMOS (Complementary)
X AGR
3rd Option Code:
Frequency Grade
CMOS (MHz)
CMOS
H
XXXXXX
LVPECL, LVDS, HCSL (MHz)
Package Option
Dimensions
A
0.1 to 212.5
0.1 to 250
B
0.1 to 170
0.1 to 170
A
5 x 7 mm
C
0.1 to 125
0.1 to 125
B
3.2 x 5 mm
C
2.5 x 3.2 mm
6-digit Frequency and Default I2C Address Code
2nd Option Code:
Frequency Stability
Total
Temperature
A
±100ppm
±50ppm
B
±50ppm
±25ppm
C
±30ppm
±20ppm
Code
Description
xxxxxx
The Si514 supports a user-defined start-up
frequency which must be in the same range as
specified by the Frequency Grade code. A
user-defined, 7-bit I2C address is supported.
Each unique start-up frequency/I2C address
combination is assigned a 6-digit code by:
(see ** below) .
** www.skyworksinc.com/en/application-pages/timing-lookup-customize
Figure 2. Part Number Convention
Example part number: 512PCA000104BAGR:
The series prefix, 512, indicates the device is a Dual CMOS XO with the OE function on pin 2. The output format
code P specifies the outputs are dual in-phase CMOS with a 2.5 V supply. The frequency stability code C indicates
a total stability of ± 30 ppm. The frequency select and output enable code A specifies that the two frequencies are
listed in ascending order, with the output frequency f0 (the lower frequency) selected when FS=0, and f1 (the
higher frequency) selected when FS = 1. The device’s output enable polarity is active High.
The six-digit code is 000104. Refer to the part number lookup at www.skyworksinc.com/products/timing-oscillators.
f0 is 155.52 MHz (the lower frequency) and f1 is 156.25 MHz (the higher frequency). The package code B refers to
the 3.2 x 5 mm footprint with six pins. The last A refers to the product revision, G indicates the temperature range
(–40 to +85oC), and R means the device ships in tape and reel format.
Note: CMOS and Dual CMOS maximum frequency is 212.5 MHz.
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Re v. 1.2 Si5 12/51 3
5. Package Outline Diagram, 5 x 7 mm, 6-pin
Figure 3 illustrates the package details for the 5 x 7 mm Si512/513. Table 15 lists the values for the dimensions
shown in the illustration.
Figure 3. Si512/513 Outline Diagram
Table 15. Package Diagram Dimensions (mm)
Dimension
A
Min
1.50
Nom
1.65
Max
b
1.30
1.40
1.50
c
0.50
0.60
0.70
4.30
5.00 BSC.
4.40
4.50
e
E
E1
6.10
2.54 BSC.
7.00 BSC.
6.20
6.30
H
0.55
0.65
0.75
L
1.17
1.27
1.37
L1
0.05
0.10
0.15
p
1.80
—
2.60
D
D1
R
aaa
bbb
ccc
1.80
0.70 REF.
0.15
0.15
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
14
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Re v. 1 .2S i512/ 513
Table 15. Package Diagram Dimensions (mm)
ddd
eee
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
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Re v. 1.2 Si5 12/51 3
6. PCB Land Pattern: 5 x 7 mm, 6-pin
Figure 4 illustrates the 5 x 7 mm PCB land pattern for the Si512/513. Table 16 lists the values for the dimensions
shown in the illustration.
Figure 4. Si512/513 PCB Land Pattern
Table 16. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
C1
4.20
E
2.54
X1
1.55
Y1
1.95
Notes:
General
1.
2.
3.
4.
All dimensions shown are in millimeters (mm) unless otherwise noted.
Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
This Land Pattern Design is based on the IPC-7351 guidelines.
All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
16
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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Re v. 1 .2S i512/ 513
7. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin
Figure 5 illustrates the package details for the 3.2 x 5.0 mm Si512/513. Table 17 lists the values for the dimensions
shown in the illustration.
Figure 5. Si512/513 Outline Diagram
Table 17. Package Diagram Dimensions (mm)
Dimension
Min
Nom
Max
A
1.06
1.17
1.33
b
0.54
0.64
0.74
c
0.35
0.45
0.55
D
D1
3.20 BSC
2.55
2.60
e
1.27 BSC
E
5.00 BSC
2.65
E1
4.35
4.40
4.45
H
0.45
0.55
0.65
L
0.80
0.90
1.00
L1
0.05
0.10
0.15
p
1.17
1.27
1.37
R
0.32 REF
aaa
0.15
bbb
0.15
ccc
0.10
ddd
0.10
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Re v. 1.2 Si5 12/51 3
Table 17. Package Diagram Dimensions (mm) (Continued)
eee
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
18
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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Re v. 1 .2S i512/ 513
8. PCB Land Pattern: 3.2 x 5.0 mm
Figure 6 illustrates the 3.2 x 5.0 mm PCB land pattern for the Si512/513. Table 18 lists the values for the
dimensions shown in the illustration.
Figure 6. Si512/513 Recommended PCB Land Pattern
Table 18. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
C1
2.60
E
1.27
X1
0.80
Y1
1.70
Notes:
General
1.
2.
3.
4.
All dimensions shown are in millimeters (mm) unless otherwise noted.
Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
This Land Pattern Design is based on the IPC-7351 guidelines.
All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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Re v. 1.2 Si5 12/51 3
9. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin
Figure 7 illustrates the package details for the 2.5 x 3.2 mm Si512/513. Table 19 lists the values for the dimensions
shown in the illustration.
Figure 7. Si512/513 Outline Diagram
20
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Re v. 1 .2S i512/ 513
Table 19. Package Diagram Dimensions (mm)
Dimension
Min
Nom
Max
A
—
—
1.1
A1
0.26 REF
A2
0.7 REF
W
0.65
0.7
D
3.20 BSC
e
1.25 BSC
E
2.50 BSC
M
0.30 BSC
L
0.45
0.5
D1
2.5 BSC
E1
1.65 BSC
SE
0.825 BSC
aaa
0.1
bbb
0.2
ddd
0.08
0.75
0.55
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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Re v. 1.2 Si5 12/51 3
10. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin
Figure 8 illustrates the 2.5 x 3.2 mm PCB land pattern for the Si512/513. Table 20 lists the values for the
dimensions shown in the illustration.
Figure 8. Si512/513 Recommended PCB Land Pattern
Table 20. PCB Land Pattern Dimensions (mm)
Dimension
C1
(mm)
1.9
E
2.50
X1
0.70
Y1
1.05
Notes:
General
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
4. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
22
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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Re v. 1 .2S i512/ 513
11. Top Marking
Use the part number utility located at: www.skyworksinc.com/en/application-pages/timing-lookup-customize to crossreference the mark code to a specific device configuration.
11.1. Si512/513 Top Marking
2 C CC CC
T TTT TT
Y Y WW
11.2. Top Marking Explanation
Mark Method:
Laser
Line 1 Marking:
2 = Si512
3 = Si513
CCCCC = Mark Code
2CCCCC
Line 2 Marking:
TTTTTT = Assembly Manufacturing Code
TTTTTT
Line 3 Marking:
Pin 1 indicator.
Circle with 0.5 mm diameter;
left-justified
YY = Year.
WW = Work week.
Characters correspond to the year and
work week of package assembly.
YYWW
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Re v. 1.2 Si5 12/51 3
REVISION HISTORY
Revision 1.2
June, 2018
Changed “Trays” to “Coil Tape” in Ordering Guide.
Revision 1.1
December, 2017
Add 2.5 x 3.2 mm package.
Revision 1.0
Updated Table 1 on page 3.
Updates
to supply current typical and maximum values for CMOS, LVDS, LVPECL and HCSL.
frequency test condition corrected to 100 MHz.
Updates to OE VIH minimum and VIL maximum values.
CMOS
Updated Table 2 on page 4.
Dual
CMOS nominal frequency maximum added.
stability footnotes clarified for 10 year aging at 40 °C.
Disable time maximum values updated.
Enable time parameter added.
Total
Updated Table 3 on page 5.
CMOS
output rise / fall time typical and maximum values updated.
output rise / fall time maximum value updated.
LVPECL output swing maximum value updated.
LVDS output common mode typical and maximum values updated.
HCSL output swing maximum value updated.
Duty cycle minimum and maximum values tightened to 48/52%.
LVPECL/HCSL
Updated Table 4 on page 6.
Phase
jitter test condition and maximum value updated.
noise typical values updated.
Additive RMS jitter due to external power supply noise typical values updated.
Footnote 3 updated limiting the VDD to 2.5/3.3V
Phase
24
Added Tables 5, 6, 7 for LVDS, HCSL, CMOS, and Dual CMOS operations.
Moved Absolute Maximum Ratings table.
Added note to Figure clarifying CMOS and Dual CMOS maximum frequency.
Updated Figure 5 outline diagram to correct pinout.
Updated Table 17 on page 17.
Updated “11. Top Marking” section and moved to page 23.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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