595KB156M250DGR

Si 5 95 REVISION D VO L TAG E - C ONTR OLLED C RYSTAL O S C I L L A T O R (VCXO) 10 TO 810 MH Z Features   Available with any-rate output frequencies from 10 to 810 MHz  3rd generation DSPLL® with superior jitter performance  Internal fixed fundamental mode crystal frequency ensures high reliability and low aging     Available CMOS, LVPECL, LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options Industry standard 5x7 and 3.2x5 mm packages Pb-free/RoHS-compliant –40 to +85 ºC operating range Applications    Si5602 Ordering Information: SONET/SDH (OC-3/12/48) Networking SD/HD SDI/3G SDI video    See page 9. FTTx Clock recovery and jitter cleanup PLLs FPGA/ASIC clock generation Pin Assignments: See page 8. Description The Si595 VCXO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low-jitter clock at high frequencies. The Si595 is available with any-rate output frequency from 10 to 810 MHz. Unlike traditional VCXOs, where a different crystal is required for each output frequency, the Si595 uses one fixed crystal to provide a wide range of output frequencies. This ICbased approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides supply noise rejection, simplifying the task of generating low-jitter clocks in noisy environments. The Si595 IC-based VCXO is factoryconfigurable for a wide variety of user specifications including frequency, supply voltage, output format, tuning slope, and absolute pull range (APR). Specific configurations are factory programmed at time of shipment, thereby eliminating the long lead times associated with custom oscillators. (Top View) VC 1 6 VDD OE 2 5 CLK– GND 3 4 CLK+ Functional Block Diagram CLK– V DD CLK+ Any-rate 10–810 MHz DSPLL ® Clock Synthesis Fixed Frequency XO ADC Vc Rev. 1.4 6/18 OE GND Copyright © 2018 by Silicon Laboratories Si595 Si5 95 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 6. Package Outline Drawing: 3.2 x 5 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7. PCB Land Pattern: 3.2 x 5 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8. Si5xx Mark Specification: 5 x 7 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9. Si5xx Mark Specification: 3.2 x 5 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2 Preliminary Rev. 1.4 Si595 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Supply Voltage1 Symbol Test Condition Min Typ Max VDD 3.3 V option 2.97 3.3 3.63 2.5 V option 2.25 2.5 2.75 1.8 V option 1.71 1.8 1.89 Output enabled LVPECL CML LVDS CMOS — — — — 120 110 100 90 135 120 110 100 Tristate mode — 60 75 VIH 0.75 x VDD — — VIL — — 0.5 –40 — 85 Supply Current IDD Output Enable (OE)2 Operating Temperature Range TA Units V mA V °C Notes: 1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 9 for further details. 2. OE pin includes an internal 17 k pullup resistor to VDD for output enable active high or a 17 k pull-down resistor to GND for output enable active low. See 3. "Ordering Information" on page 9. Table 2. VC Control Voltage Input Parameter Control Voltage Tuning Slope 1,2,3 Control Voltage Linearity4 Symbol Test Condition Min Typ Max Units KV 10 to 90% of VDD — 45 95 125 185 380 — ppm/V LVC BSL –5 ±1 +5 Incremental –10 ±5 +10 % Modulation Bandwidth BW 9.3 10.0 10.7 kHz VC Input Impedance ZVC 500 — — k VC Input Capacitance CVC — 50 — pF — VDD/2 — V VDD V Nominal Control Voltage Control Voltage Tuning Range VCNOM @ fO 0 VC Notes: 1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 9. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information. 3. KV variation is ±10% of typical values. 4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope determined with VC ranging from 10 to 90% of VDD. Rev. 1.4 3 Si5 95 Table 3. CLK± Output Frequency Characteristics Parameter Nominal Frequency1,2,3 Symbol Test Condition Min Typ Max fO LVDS/CML/LVPECL 10 — 810 CMOS 10 — 160 TA = –40 to +85 ºC –20 –50 — — +20 +50 ppm Temperature Stability1,4 Units MHz Absolute Pull Range1,4 APR ±10 — ±370 ppm Power up Time5 tOSC — — 10 ms Notes: 1. See Section 3. "Ordering Information" on page 9 for further details. 2. Specified at time of order by part number. 3. Nominal output frequency set by VCNOM = VDD/2. 4. Selectable parameter specified by part number. 5. Time from power up or tristate mode to fO. Table 4. CLK± Output Levels and Symmetry Parameter LVPECL Output Option 1 LVDS Output Option2 Symbol Test Condition Min Typ Max Units VO mid-level VDD – 1.42 — VDD – 1.25 V VOD swing (diff) 1.1 — 1.9 VPP VSE swing (single-ended) 0.55 — 0.95 VPP VO mid-level 1.125 1.20 1.275 V VOD swing (diff) 0.5 0.7 0.9 VPP 2.5/3.3 V option mid-level — VDD – 1.30 — 1.8 V option mid-level — VDD – 0.36 — 2.5/3.3 V option swing (diff) 1.10 1.50 1.90 1.8 V option swing (diff) 0.35 0.425 0.50 VOH 0.8 x VDD — VDD VOL — — 0.4 LVPECL/LVDS/CML — — 350 ps CMOS with CL = 15 pF — 2 — ns 45 — 55 % VO CML Output Option 2 VOD CMOS Output Option3 Rise/Fall time (20/80%) Symmetry (duty cycle) tR, tF SYM LVPECL: LVDS: CMOS: VDD – 1.3 V (diff) 1.25 V (diff) VDD/2 Notes: 1. 50  to VDD – 2.0 V. 2. Rterm = 100  (differential). 3. CL = 15 pF. Sinking or sourcing 12 mA for VDD = 3.3 V, 6 mA for VDD = 2.5 V, 3 mA for VDD = 1.8 V. 4 Rev. 1.4 V VPP V Si595 Table 5. CLK± Output Phase Jitter Parameter Phase Jitter (RMS)1,2 for FOUT of 50 MHz < FOUT 810 MHz Symbol J Test Condition Min Typ Max Kv = 45 ppm/V 12 kHz to 20 MHz — 0.5 — Kv = 95 ppm/V 12 kHz to 20 MHz — 0.5 — Kv = 125 ppm/V 12 kHz to 20 MHz — 0.5 — Kv = 185 ppm/V 12 kHz to 20 MHz — 0.5 — Kv = 380 ppm/V 12 kHz to 20 MHz — 0.7 — Units ps Notes: 1. Refer to AN256 for further information. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information. Table 6. CLK± Output Period Jitter Parameter Period Jitter* Symbol Test Condition Min Typ Max Units JPER RMS — 3 — ps Peak-to-Peak — 35 — *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information. Table 7. CLK± Output Phase Noise (Typical) Offset Frequency 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 20 MHz 74.25 MHz 148.5 MHz 155.52 MHz 185 ppm/V 185 ppm/V 95 ppm/V LVPECL LVPECL LVPECL –77 –101 –121 –134 –149 –151 –150 –68 –95 –116 –128 –144 –147 –148 –77 –101 –119 –127 –144 –147 –148 Rev. 1.4 Units dBc/Hz 5 Si5 95 Table 8. Environmental Compliance and Package Information Parameter Conditions/Test Method Mechanical Shock MIL-STD-883, Method 2002 Mechanical Vibration MIL-STD-883, Method 2007 Solderability MIL-STD-883, Method 2003 Gross and Fine Leak MIL-STD-883, Method 1014 Resistance to Solder Heat MIL-STD-883, Method 2036 Contact Pads Gold over Nickel Table 9. Thermal Characteristics (Typical values TA = 25 ºC, VDD = 3.3 V) Parameter Symbol Test Condition Min Typ Max Unit 5x7mm, Thermal Resistance Junction to Ambient JA Still Air — 84.6 — °C/W 5x7mm, Thermal Resistance Junction to Case JC Still Air — 38.8 — °C/W 3.2x5mm, Thermal Resistance Junction to Ambient JA Still Air — 31.1 — °C/W 3.2x5mm, Thermal Resistance Junction to Case JC Still Air — 13.3 — °C/W Ambient Temperature TA –40 — 85 °C Junction Temperature TJ — — 125 °C Table 10. Absolute Maximum Ratings1 Parameter Symbol Rating Units TAMAX 85 ºC VDD –0.5 to +3.8 V Input Voltage VI –0.5 to VDD + 0.3 Storage Temperature TS –55 to +125 ºC ESD 2500 V TPEAK 260 ºC Maximum Operating Temperature Supply Voltage ESD Sensitivity (HBM, per JESD22-A114) Soldering Temperature (Pb-free profile)2 6 Rev. 1.4 Si595 Table 10. Absolute Maximum Ratings1 Parameter Soldering Temperature Time @ TPEAK (Pb-free profile)2 Symbol Rating Units tP 20–40 seconds Notes: 1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download from www.silabs.com/VCXO for further information, including soldering profiles. Rev. 1.4 7 Si5 95 2. Pin Descriptions (Top View) VC 1 6 VDD OE 2 5 CLK– GND 3 4 CLK+ Table 11. Si595 Pin Descriptions Pin Name Type Function 1 VC Analog Input Control Voltage 2 OE* Input Output Enable 3 GND Ground Electrical and Case Ground 4 CLK+ Output Oscillator Output 5 CLK– (N/C for CMOS) Output Complementary Output (N/C for CMOS, do not make external connection) 6 VDD Power Power Supply Voltage *Note: OE pin includes a 17 k resistor to VDD for OE active high option or 17 k to GND for OE active low option. See 3. "Ordering Information" on page 9. 8 Rev. 1.4 Si595 3. Ordering Information The Si595 supports a variety of options including frequency, temperature stability, tuning slope, output format, and VDD. Specific device configurations are programmed into the Si595 at time of shipment. Configurations are specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part number configuration utility to simplify this process. To access this tool refer to www.silabs.com/oscillators and click “Customize” in the product table. The Si595 VCXO series is supplied in industry-standard, RoHS compliant, leadfree, 6-pad, 5 x 7 mm and 3.2 x 5 mm package. Tape and reel packaging is an ordering option. 595 X X XXXMXXX D G R R = Tape and Reel Blank = Coil Tape 595 VCXO Product Family Operating Temp Range(°C) G –40 to +85 °C Device Revision Letter Frequency (e.g., 148M500 is 148.5 MHz) Available frequency range is10 to 810 MHz. The position of “M” shifts to denote higher or lower frequencies . If the frequency of interest requires greater than6 digit resolution, a six digit code will be assigned for the specific frequency. 1st Option Code A B C D E F G H J K M N P Q R S T U V W V DD 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 2nd Option Code Output Format Output Enable Polarity LVPECL High LVDS High CMOS High CML High LVPECL High LVDS High CMOS High CML High CMOS High CML High LVPECL Low LVDS Low CMOS Low CML Low LVPECL Low LVDS Low CMOS Low CML Low CMOS Low CML Low Note: CMOS available to 160 MHz. Temperature Stability ± ppm (max) 20 20 50 20 20 50 50 20 20 20 50 20 20 50 50 20 Tuning Slope Kv ppm/V (typ) 380 185 185 125 95 125 95 45 380 185 185 125 95 125 95 45 Minimum APR (±ppm) for VDD @ 3.3 V 2.5 V 1.8 V 370 275 200 160 110 80 130 80 50 100 75 40 65 50 25 70 45 10 35 20 N/A 15 N/A N/A 370 275 200 160 110 80 130 80 50 100 75 40 65 50 25 70 45 10 35 20 N/A 15 N/A N/A Code Package A 5x7 mm B 5x7 mm C 5x7 mm D 5x7 mm E 5x7 mm F 5x7 mm G 5x7 mm H 5x7 mm J 3.2x5 mm K 3.2x5 mm M 3.2x5 mm P 3.2x5 mm Q 3.2x5 mm R 3.2x5 mm S 3.2x5 mm T 3.2x5 mm Notes: 1. For best jitter and phase noise performance , always choose the smallest Kv that meets the application’s minimum APR requirements. Lower Kv options minimize noise coupling and jitter in real-world PLL designs. See AN266 for more information. 2. APR is the ability of a VCXO to track a signal over the product lifetime . A VCXO with an APR of ±100 ppm is able to lock to a clock with a ±100 ppm stability over 15 years over all operating conditions. 3. Nominal Pull range (±) = 0.5 x VDD x tuning slope. 4. Minimum APR values noted above include worst case values for all parameters . Example Part Number: 595AE148M500DGR is a 5 x 7 mm VCXO in a 6 pad package. The nominal frequency is148.5 MHz, with a 3.3 V supply, LVPECL output, and Output Enable active high polarity. Temperature stability is specified as±20 ppm and the tuning slope is95 ppm/V. The part is specified for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format . Figure 1. Part Number Convention Rev. 1.4 9 Si5 95 4. Package Outline Diagram: 5 x 7 mm, 6-pin Figure 2 illustrates the package details for the 5 x 7 mm Si595. Table 12 lists the values for the dimensions shown in the illustration. Figure 2. Si595 Outline Diagram Table 12. Package Diagram Dimensions (mm) Dimension A b c D D1 e E E1 H L L1 p R aaa bbb ccc ddd eee Min 1.50 1.30 0.50 4.30 6.10 0.55 1.17 0.05 1.80 Nom 1.65 1.40 0.60 5.00 BSC 4.40 2.54 BSC. 7.00 BSC. 6.20 0.65 1.27 0.10 — 0.70 REF 0.15 0.15 0.10 0.10 0.05 Max 1.80 1.50 0.70 4.50 6.30 0.75 1.37 0.15 2.60 Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994 10 Rev. 1.4 Si595 5. PCB Land Pattern: 5 x 7 mm, 6-pin Figure 3 illustrates the 6-pin PCB land pattern for the 5 x 7 mm Si595. Table 13 lists the values for the dimensions shown in the illustration. Figure 3. Si595 PCB Land Pattern Table 13. PCB Land Pattern Dimensions (mm) Dimension (mm) C1 4.20 E 2.54 X1 1.55 Y1 1.95 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.4 11 Si5 95 6. Package Outline Drawing: 3.2 x 5 mm, 6-pin Figure 4 illustrates the package details for the 3.2 x 5 mm Si595. Table 14 lists the values for the dimensions shown in the illustration. Figure 4. Si595 Outline Diagram Table 14. Package Diagram Dimensions (mm) Dimension A A1 A2 A3 b B1 D D1 D2 e E Min 1.02 0.99 0.54 0.35 Nom 1.17 1.10 0.5 BSC 0.30 BSC Max 1.32 1.21 0.64 0.45 5.00 BSC 4.65 BSC 3.38 BSC 1.27 BSC 3.20 BSC 0.74 0.55 Dimension E1 E2 L L2 R1 aaa bbb ccc ddd eee Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 12 Rev. 1.4 Min 0.35 0.05 Nom 2.85 BSC 1.91 BSC 0.45 0.10 0.10 REF 0.15 0.15 0.08 0.10 0.05 Max 0.55 0.15 Si595 7. PCB Land Pattern: 3.2 x 5 mm, 6-pin Figure 5 illustrates the 6-pin PCB land pattern for the 3.2 x 5 mm Si595. Table 15 lists the values for the dimensions shown in the illustration. Figure 5. Si595 PCB Land Pattern Table 15. PCB Land Pattern Dimensions (mm) Dimension (mm) C1 2.91 E 1.27 X1 0.80 Y1 1.10 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Rev. 1.4 13 Si5 95 8. Si5xx Mark Specification: 5 x 7 mm 5 x 7 mm Si595. Table 16 lists the line information. Figure 6 illustrates the mark specification for the Figure 6. Mark Specification Table 16. Si595 Top Mark Description Line Position 1 1–10 “SiLabs”+ Part Family Number, 595 (First 3 characters in part number) 2 1–10 Si595: Option1+Option2+Freq(7)+Temp Si595 w/ 8-digit resolution: Option1+Option2+ConfigNum(6)+Temp 3 14 Description Trace Code Position 1 Pin 1 orientation mark (dot) Position 2 Product Revision (D) Position 3–6 Tiny Trace Code (4 alphanumeric characters per assembly release instructions) Position 7 Year (least significant year digit), to be assigned by assembly site (ex: 2009 = 9) Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site Position 10 “+” to indicate Pb-Free and RoHS-compliant Rev. 1.4 Si595 9. Si5xx Mark Specification: 3.2 x 5 mm Figure 7 illustrates the mark specification for the 3.2 x 5 mm Si595. Table 17 lists the line information. Figure 7. Mark Specification Table 17. Si595 Top Mark Description Line Position 1 1–5 “Si”+ Part Family Number, 595 (First 3 characters in part number) 6–8 Crystal trace code (3 alphanumeric characters assigned by assembly site) 1–9 Si595: Option1+Option2+Freq(7) Si595 w/ 8-digit resolution: Option1+Option2+ConfigNum(6) 2 3 Description Trace Code Position 1 Pin 1 orientation mark (dot) Position 2 Product Revision (D) Position 3–5 Tiny Trace Code (3 alphanumeric characters per assembly release instructions) Position 6–7 Year (last two digits of year), to be assigned by assembly site (ex: 2017 = 17) Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site Rev. 1.4 15 Si5 95 REVISION HISTORY Revision 1.4 June, 2018  Changed “Trays” to “Coil Tape” in 3. "Ordering Information" on page 9. Revision 1.3 December, 2017  Added 3.2 x 5 mm package. Revision 1.2  Added Table 9, “Thermal Characteristics,” on page 6. Revision 1.1  Swapped D and E values in Table 12 on page 10. Revision 1.0       Updated 2.5 V/3.3 V and 1.8 V CML output level specifications in Table 4 on page 4. Updated Si595 device to support frequencies up to 810 MHz for LVPECL, LVDS, and CML outputs. Separated 1.8 V, 2.5 V/3.3 V supply voltage. specifications for CML output in Table 3 on page 5. Updated Note 1 of Table 5 on page 5 to refer to AN256. Updated Table 8 on page 6 to include the "Moisture Sensitivity Level" and "Contact Pads" rows. Updated Figure 3 and Table 16 on page 14 to reflect specific marking information. Revision 0.2  Updated Table 5, “CLK± Output Phase Jitter,” on page 5. Updated 16 typical phase jitter from 0.6 to 0.7 ps for kV = 380 ppm/V. Rev. 1.4 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. 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