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Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M
8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Features
Description
•
•
•
•
•
•
•
The 6N137M, HCPL2601M, HCPL2611M single-channel
and HCPL2630M, HCPL2631M dual-channel optocouplers consist of a 850 nm AlGaAS LED, optically coupled
to a very high speed integrated photo-detector logic gate
with a strobable output. This output features an open collector, thereby permitting wired OR outputs. The
switching parameters are guaranteed over the temperature range of -40°C to +85°C. A maximum input signal of
5 mA will provide a minimum output sink current of
13 mA (fan out of 8).
Very High Speed – 10 MBit/s
Superior CMR – 10 kV/µs
Fan-out of 8 Over -40°C to +85°C
Logic Gate Output
Strobable Output
Wired OR-open Collector
Safety and Regulatory Approvals
– UL1577, 5,000 VACRMS for 1 Minute
– DIN EN/IEC60747-5-5
An internal noise shield provides superior common mode
rejection of typically 10 kV/µs. The HCPL2601M and
HCPL2631M has a minimum CMR of 5 kV/µs. The
HCPL2611M has a minimum CMR of 10 kV/µs.
Applications
•
•
•
•
•
•
•
Ground Loop Elimination
LSTTL to TTL, LSTTL or 5 V CMOS
Line Receiver, Data Transmission
Data Multiplexing
Switching Power Supplies
Pulse Transformer Replacement
Computer-peripheral Interface
Schematics
Package Outlines
8
8 VCC
N/C 1
8
8 VCC
+ 1
1
1
VF1
7 VE
+ 2
_ 2
7 V01
8
VF
_
6 VO
3
_
V
5 GND
N/C 4
6 V02
3
8
1
1
Figure 2. Package Options
F2
5 GND
+ 4
6N137M,
HCPL2601M,
HCPL2611M
HCPL2630M,
HCPL2631M
Truth Table (Positive Logic)
Input
Enable
Output
H
H
L
L
H
H
H
L
H
L
L
H
A 0.1µF bypass capacitor must be connected between pins 8 and 5(1).
H
NC
L
Figure 1. Schematics
L
NC
H
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.6
www.fairchildsemi.com
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
January 2016
As per DIN EN/IEC 60747-5-5, this optocoupler is suitable for “safe electrical insulation” only within the safety limit
data. Compliance with the safety ratings shall be ensured by means of protective circuits.
Parameter
Installation Classifications per DIN VDE
0110/1.89 Table 1, For Rated Mains Voltage
Characteristics
< 150 VRMS
I–IV
< 300 VRMS
I–IV
< 450 VRMS
I–III
< 600 VRMS
I–III
Climatic Classification
40/100/21
Pollution Degree (DIN VDE 0110/1.89)
2
Comparative Tracking Index
Symbol
VPR
175
Parameter
Value
Unit
Input-to-Output Test Voltage, Method A, VIORM x 1.6 = VPR,
Type and Sample Test with tm = 10 s, Partial Discharge < 5 pC
1,335
Vpeak
Input-to-Output Test Voltage, Method B, VIORM x 1.875 = VPR,
100% Production Test with tm = 1 s, Partial Discharge < 5 pC
1,669
Vpeak
890
Vpeak
VIORM
Maximum Working Insulation Voltage
VIOTM
Highest Allowable Over-Voltage
6,000
Vpeak
External Creepage
≥ 8.0
mm
External Clearance
External Clearance (for Option TV, 0.4" Lead Spacing)
DTI
TS
IS,INPUT
PS,OUTPUT
RIO
≥ 7.4
mm
≥ 10.16
mm
≥ 0.5
mm
Case
Temperature(2)
150
°C
Input
Current(2)
200
mA
300
mW
> 109
Ω
Distance Through Insulation (Insulation Thickness)
Output Power (Duty Factor ≤ 2.7%)(2)
Insulation Resistance at TS, VIO = 500 V(2)
Notes:
1. The VCC supply to each optoisolator must be bypassed by a 0.1 µF capacitor or larger. This can be either a ceramic
or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to
the package VCC and GND pins of each device.
2. Safety limit value - maximum values allowed in the event of a failure.
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.6
www.fairchildsemi.com
2
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Safety and Insulation Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. TA = 25°C unless otherwise specified.
Symbol
Parameter
Value
Unit
TSTG
Storage Temperature
-40 to +125
°C
TOPR
Operating Temperature
-40 to +100
°C
Junction Temperature
-40 to +125
°C
TJ
TSOL
Lead Solder Temperature
Symbol
260 for 10 sec
°C
Device
Value
Unit
Single Channel
50
Dual Channel
30
Parameter
EMITTER
IF (avg)
DC/Average Forward Input Current Per Channel
mA
VE
Enable Input Voltage Not to Exceed VCC
by more than 500 mV
Single Channel
5.5
V
VR
Reverse Input Voltage Per Channel
All
5.0
V
PI
Input Power Dissipation Per Channel
Single Channel
100
Dual Channel
45
mW
DETECTOR
Supply Voltage
All
-0.5 to 7.0
V
IO (avg)
Average Output Current Per Channel
All
25
mA
IO (pk)
Peak Output Current Per Channel
All
50
mA
VO
Output Voltage Per Channel
All
-0.5 to 7.0
V
PO
Output Power Dissipation Per Channel
VCC
Single Channel
85
Dual Channel
60
mW
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Min.
Max.
Unit
4.5
5.5
V
Input Current, Low Level
0
250
µA
IFH
Input Current, High Level
6.3(3)
20.0
mA
VEL
Enable Voltage, Low Level
0
0.8
V
VEH
Enable Voltage, High Level
2.0
VCC
V
TA
Ambient Operating Temperature
-40
+85
°C
N
Fan Out (TTL load)
VCC
IFL
Parameter
Supply Voltage
8
Note:
3. 6.3 mA is a guard banded value which allows for at least 20% CTR degradation. Initial input current threshold value
is 5.0 mA or less.
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.6
www.fairchildsemi.com
3
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Absolute Maximum Ratings
Individual Component Characteristics (VCC = 5.5 V, TA = 0°C to 70°C unless otherwise specified)
Symbol
Parameter
Device
Test Conditions
Min.
Typ.
Max.
1.45
1.70
Unit
EMITTER
VF
Input Forward Voltage
IF = 10 mA, TA = 25°C
All
IF = 10 mA
BVR
Input Reverse Breakdown
All
Voltage
IR = 10 µA
CIN
Input Capacitance
VF = 0, f = 1 MHz
ΔVF / ΔTA
All
Temperature Coefficient of
All
Forward Voltage
1.80
5.0
IF = 10 mA
V
V
60
pF
-1.4
mV/°C
DETECTOR
ICCL
Logic Low Supply Current
I = 10 mA, VO = Open,
Single Channel F
VE = 0.5 V
Dual Channel
ICCH
8
13
14
21
6
10
10
15
mA
IF1 = IF2 = 10 mA,
VO = Open
I = 0 mA, VO = Open,
Single Channel F
V
Logic High Supply Current
E = 0.5 V
Dual Channel IF = 0 mA, VO = Open,
mA
IEL
Low Level Enable Current Single Channel VE = 0.5 V
-0.7
-1.6
mA
IEH
-0.5
-1.6
mA
VEL
High Level Enable Current Single Channel VE = 2.0 V
Low Level Enable Voltage Single Channel IF = 10 mA(4)
0.8
V
VEH
High Level Enable Voltage Single Channel IF = 10 mA
2.0
V
Note:
4. Enable Input – No pull up resistor required as the device has an internal pull up resistor.
Transfer Characteristics (VCC = 5.5 V, TA = -40°C to +85°C unless otherwise specified)
Symbol
Parameter
Device
VO = 0.6 V, VE = 2.0 V,
IOL = 13 mA
IFT
Input Threshold Current
IOH
HIGH Level Output Current All
VO = 5.5 V, IF = 250 µA,
VE = 2.0 V
VOL
LOW Level Output Voltage
IF = 5 mA, VE = 2.0 V,
IOL = 13 mA
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.6
All
Test Conditions
All
Min.
Typ.
Max.
Unit
3
5
mA
100
µA
0.6
V
0.4
www.fairchildsemi.com
4
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Electrical Characteristics
Switching Characteristics (VCC = 5 V, IF = 7.5 mA, TA = -40°C to +85°C unless otherwise specified)
Symbol
tPHL
tPLH
Parameter
Propagation Delay
Time to Logic LOW
Propagation Delay
Time to Logic HIGH
Device
All
All
Test Conditions
RL = 350 Ω, CL = 15 pF,
TA = 25°C(5) (Fig. 14)
Min.
Typ.
25
40
75
ns
RL = 350 Ω, CL = 15 pF(5)
(Fig. 14)
RL = 350 Ω, CL = 15 pF,
TA = 25°C(6) (Fig. 14)
Max. Unit
100
20
40
75
ns
RL = 350 Ω, CL = 15 pF(6)
(Fig. 14)
100
Pulse Width Distortion All
RL = 350 Ω, CL = 15 pF
(Fig. 14)
1
tR
Output Rise Time
(10% to 90%)
All
RL = 350 Ω, CL = 15 pF(7)
(Fig. 14)
30
ns
tF
Output Fall Time
(90% to 10%)
All
RL = 350 Ω, CL = 15 pF(8)
(Fig. 14)
10
ns
tEHL
Enable Propagation
Delay Time to Output
LOW Level
Single Channel
VEH = 3.5 V, RL = 350 Ω,
CL = 15 pF(9) (Fig. 15)
15
ns
tELH
Enable Propagation
Delay Time to Output
HIGH Level
Single Channel
VEH = 3.5 V, RL = 350 Ω,
CL = 15 pF(10) (Fig. 15)
15
ns
|tPHL–tPLH|
6N137M,
HCPL2630M
|CMH|
Common Mode
Transient Immunity
at Logic High
HCPL2601M,
HCPL2631M
HCPL2611M
6N137M,
HCPL2630M
|CML|
Common Mode
Transient Immunity
at Logic Low
HCPL2601M,
HCPL2631M
HCPL2611M
IF = 0 mA, VCM = 50 VPEAK,
RL = 350 Ω, TA = 25°C(11)
(Fig. 16)
35
ns
10,000
5000
10,000
V/µs
IF = 0 mA, VCM = 400 VPEAK,
10,000 15,000
RL = 350 Ω, TA = 25°C(11)
(Fig. 16)
VCM = 50 VPEAK,
RL = 350 Ω, TA = 25°C(11)
(Fig. 16)
VCM = 400 VPEAK,
RL = 350 Ω, TA = 25°C(11)
(Fig. 16)
10,000
5000
10,000
V/µs
10,000 15,000
Notes:
5. tPHL – Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current
pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
6. tPLH – Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current
pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
7. tR – Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
8. tF – Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
9. tEHL – Enable input propagation delay is measured from the 1.5 V level on the LOW to HIGH transition of the input
voltage pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
10. tELH – Enable input propagation delay is measured from the 1.5 V level on the HIGH to LOW transition of the input
voltage pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
11. Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the leading edge
of the common mode pulse signal, VCM, to assure that the output will remain in a logic high state (i.e., VO > 2.0 V).
Common mode transient immunity in logic low level is the maximum tolerable (negative) dVcm/dt on the trailing edge
of the common mode pulse signal, VCM, to assure that the output will remain in a logic low state (i.e., VO < 0.8 V).
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.6
www.fairchildsemi.com
5
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Electrical Characteristics (Continued)
Isolation Characteristics (TA =25°C unless otherwise specified.)
Symbol
Parameter
Device
Test Conditions
VISO
Withstand Insulation
Test Voltage
All
Relative Humidity ≤ 50%,
II-O ≤ 10 µA, t = 1 min,
f = 50 Hz(12)(13)
RI-O
Resistance
(Input to Output)
All
VI-O = 500 VDC(12)
CI-O
Capacitance
(Input to Output)
All
f = 1 MHz, VI-O = 0 VDC(12)
II-O
Input-Output Insulation
Leakage Current
All
Relative Humidity ≤ 45%,
VI-I = 3000 VDC, t = 5 sec(12)
Min.
Typ.
Max.
5,000
Unit
VACRMS
1011
Ω
1
pF
1.0
µA
Notes:
12. Device is considered a two terminal device: pins 1, 2, 3 and 4 are shorted together and pins 5, 6, 7 and 8 are shorted
together.
13. 5000 VACRMS for 1 minute duration is equivalent to 6000 VACRMS for 1 second duration.
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.6
www.fairchildsemi.com
6
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Electrical Characteristics (Continued)
For Single-Channel Devices: 6N137M, HCPL2601M, and HCPL2611M
IF = 5 mA
VE = 2 V
VCC = 5.5 V
0.7
IF – FORWARD CURRENT (mA)
VOL – LOW LEVEL OUTPUT VOLTAGE (V)
0.8
0.6
IOL = 12.8 mA
0.5
IOL = 16 mA
0.4
0.3
IOL = 6.4 mA
IOL = 9.6 mA
0.2
10
1
0.100
0.010
0.1
0.0
-40
-20
0
20
40
60
80
0.001
0.9
100
1.0
1.1
TA – AMBIENT TEMPERATURE (°C)
Figure 3. Low Level Output Voltage vs. Ambient Temperature
1.4
1.5
1.6
50
IOL – LOW LEVEL OUTPUT CURRENT (mA)
VCC = 5 V
TA = 25°C
TP – PROPAGATION DELAY (ns)
1.3
Figure 4. Input Diode Forward Voltage vs. Forward Current
120
100
80
RL = 4 kΩ (tPLH)
RL = 350 Ω (tPLH)
60
RL = 1 kΩ (tPLH)
40
RL = 4 kΩ (tPHL)
RL = 1 kΩ (tPHL)
RL = 350 Ω (tPHL)
20
0
5
7
9
11
13
45
IF = 15 mA
40
IF = 10 mA
35
IF = 5 mA
30
VCC = 5 V
VE = 2 V
VOL = 0.6 V
25
20
-40
15
-20
0
20
40
60
80
100
TA – AMBIENT TEMPERATURE (°C)
IF – FORWARD CURRENT (mA)
Figure 5. Switching Time vs. Forward Current
Figure 6. Low Level Output vs. Ambient Temperature
6
4.0
VCC = 5 V
VE = 2 V
VOL = 0.6 V
3.5
5
3.0
VO – OUTPUT VOLTAGE (V)
IFT – INPUT THRESHOLD CURRENT (mA)
1.2
VF – FORWARD VOLTAGE (V)
RL = 350 Ω
2.5
RL = 1 kΩ
2.0
RL = 4 kΩ
1.5
4
RL = 1 kΩ
3
RL = 350 Ω
2
RL = 4 kΩ
1
1.0
-40
-20
0
20
40
60
80
0
100
TA – AMBIENT TEMPERATURE (°C)
1
2
3
4
5
6
IF - FORWARD CURRENT (mA)
Figure 7. Input Threshold Current vs. Ambient Temperature
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.6
0
Figure 8. Output Voltage vs. Input Forward Current
www.fairchildsemi.com
7
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Typical Performance Curves
For Single-Channel Devices: 6N137M, HCPL2601M, HCPL2611M
500
50
IF = 7.5 mA
VCC = 5 V
tR / tF – RISE AND FALL TIME (ns)
PWD – PULSE WIDTH DISTORTION (ns)
60
40
RL = 4 kΩ
30
20
10
RL = 1 kΩ
0
-10
-40
400
IF = 7.5 mA
VCC = 5 V
RL = 4 kΩ (tR)
300
200
RL = 1 kΩ (tR)
100
RL = 350 Ω (tR)
0
RL = 4 kΩ (tF)
RL = 1 kΩ (tF)
RL = 350 Ω (tF)
RL = 350 Ω
-20
0
20
40
60
80
-100
-40
100
-20
TA – AMBIENT TEMPERATURE (°C)
20
40
60
80
100
Figure 10. Rise and Fall Time vs. Temperature
100
100
IF = 7.5 mA
VCC = 5 V
90
80
TP – PROPAGATION DELAY (ns)
TE – ENABLE PROPAGATION DELAY (ns)
Figure 9. Pulse Width Distortion vs. Temperature
RL = 4 kΩ (tELH)
60
40
RL = 1 kΩ (tELH)
RL = 350 Ω (tELH)
20
RL = 4 kΩ / 1 kΩ / 350 Ω (tEHL)
0
-40
0
TA – AMBIENT TEMPERATURE (°C)
-20
0
20
40
60
80
RL = 4 kΩ (tPLH)
80
70
60
RL = 1 kΩ (tPLH)
50
RL = 350 Ω (tPLH)
40
RL = 4 kΩ (tPHL)
RL = 1 kΩ (tPHL)
RL = 350 Ω (tPHL)
30
20
-40
100
IF = 7.5 mA
VCC = 5 V
-20
TA – AMBIENT TEMPERATURE (°C)
0
20
40
60
80
100
TA – AMBIENT TEMPERATURE (°C)
Figure 11. Enable Propagation Delay vs. Temperature
Figure 12. Switching Time vs. Temperature
IOH – HIGH LEVEL OUTPUT CURRENT (μA)
1.6
1.4
1.2
VCC = 5 V
VO = 5.5 V
VE = 2 V
IF = 250 μA
1.0
0.8
0.6
0.4
0.2
0
-40
-20
0
20
40
60
80
100
TA – AMBIENT TEMPERATURE (°C)
Figure 13. High Level Output Current vs. Temperature
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.6
www.fairchildsemi.com
8
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Typical Performance Curves (Continued)
0.8
100
IF = 5 mA
VCC = 5.5 V
0.7
IF – FORWARD CURRENT (mA)
VOL – LOW LEVEL OUTPUT VOLTAGE (V)
For Dual-Channel Devices: HCPL2630M and HCPL2631M
0.6
IOL = 16 mA
IOL = 12.8 mA
0.5
0.4
IOL = 9.6 mA
IOL = 6.4 mA
0.3
0.2
0.1
0.0
-40
-20
0
20
40
60
80
10
1
0.1
0.01
0.001
0.9
100
1.0
1.1
TA – AMBIENT TEMPERATURE (°C)
Figure 14. Low Level Output Voltage vs. Ambient Temperature
IOL – LOW LEVEL OUTPUT CURRENT (mA)
TP – PROPAGATION DELAY (ns)
VCC = 5 V
TA = 25°C
RL = 4 kΩ (TPLH)
80
60
RL = 1 kΩ (TPLH)
RL = 350 Ω (TPLH )
40
RL = 1 kΩ
RL = 4 kΩ (TPHL)
RL = 350 Ω
20
0
5
7
9
1.4
1.5
1.6
11
13
15
80
100
50
45
IF = 15 mA
IF = 10 mA
40
IF = 5 mA
35
30
VCC = 5 V
VOL = 0.6 V
25
20
-40
-20
IF – FORWARD CURRENT (mA)
0
20
40
60
TA – AMBIENT TEMPERATURE (°C)
Figure 17. Low Level Output Current
vs. Ambient Temperature
Figure 16. Switching Time vs. Forward Current
6
4
VCC = 5.0 V
VOL = 0.6 V
VO – OUTPUT VOLTAGE (V)
IFT – INPUT THRESHOLD CURRENT (mA)
1.3
Figure 15. Input Diode Forward Voltage
vs. Forward Current
120
100
1.2
VF – FORWARD VOLTAGE (V)
RL = 350 Ω
3
RL = 1 kΩ
RL = 4 kΩ
2
5
4
RL = 350 Ω
RL = 4 kΩ
3
2
RL = 1 kΩ
1
1
-40
0
-20
0
20
40
60
80
0
100
2
3
4
5
6
Figure 19. Output Voltage vs. Input Forward Current
Figure 18. Input Threshold Current
vs. Ambient Temperature
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.6
1
IF - FORWARD CURRENT (mA)
TA – AMBIENT TEMPERATURE (°C)
www.fairchildsemi.com
9
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Typical Performance Curves (Continued)
For Dual-Channel Devices: HCPL2630M and HCPL2631M
600
Tr/Tf – RISE AND FALL TIME (ns)
PWD – PULSE WIDTH DISTORTION (ns)
80
RL = 4 kΩ
60
IF = 7.5 mA
VCC = 5 V
40
20
RL = 1 kΩ
500
IF = 7.5 mA
VCC = 5 V
400
RL = 4 kΩ (tr)
300
RL = 1 kΩ
RL = 4 kΩ (tf)
RL = 350 Ω
200
RL = 1 kΩ (tr)
100
RL = 350 Ω (tr)
RL = 350 Ω
0
-60
-40
-20
0
20
40
60
80
0
-60
100
-40
-20
TA – TEMPERATURE (°C)
IOH – HIGH LEVEL OUTPUT CURRENT (μA)
TP – PROPAGATION DELAY (ns)
RL = 4 kΩ (TPLH)
100
IF = 7.5 mA
VCC = 5 V
80
RL = 1 kΩ (TPLH)
RL = 350 Ω (TPLH)
40
RL = 1 kΩ
RL = 4 kΩ (TPHL)
RL = 350 Ω
-40
-20
0
20
40
60
80
100
60
80
100
1.8
1.6
1.4
VCC = 5.5 V
VO = 5.5 V
IF = 250 μA
1.2
1.0
0.8
0.6
0.4
0.2
0
-60
-40
-20
0
20
40
60
80
100
TA – TEMPERATURE (°C)
TA – TEMPERATURE (°C)
Figure 23. High Level Output Current
vs. Temperature
Figure 22. Switching Time vs. Temperature
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.6
40
TA – TEMPERATURE (°C)
120
20
-60
20
Figure 21. Rise and Fall Time vs. Temperature
Figure 20. Pulse Width Distortion vs. Temperature
60
0
www.fairchildsemi.com
10
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Typical Performance Curves (Continued)
Pulse
Generator
tr = 5 ns
Z O = 50 Ω
+5 V
IF = 7.5 mA
VCC
1
8
2
7
IF = 3.75 mA
Input
(IF )
t PHL
Input
Monitor
(I F)
.1 μF
bypass
Output
(VO )
6
3
CL
47
4
GND
tPLH
Output
(VO )
RL
1.5 V
90%
Output
(VO )
10%
5
tf
tr
Figure 24. Test Circuit and Waveforms for tPLH, tPHL, tr and tf
Pulse
Generator
tr = 5 ns
Z O = 50 Ω
Input
Monitor
(V E)
+5 V
3.0 V
Input
(VE )
VCC
1
8
1.5 V
t EHL
7.5 mA
7
2
.1 μF
bypass
RL
1.5 V
Output
(VO )
6
3
t ELH
Output
(VO )
CL
4
GND
5
Figure 25. Test Circuit tEHL and tELH
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.6
www.fairchildsemi.com
11
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Test Circuits
VCC
IF
A
1
8
2
7
3
6
+5 V
.1 μF
bypass
350 Ω
B
VFF
4
GND
Output
(VO)
5
VCM
Pulse Gen
Peak
VCM
0V
CM H
5V
Switching Pos. (A), IF = 0
VO
VO (Min)
VO (Max)
Switching Pos. (B), I F = 7.5 mA
VO
0.5 V
CM L
Figure 26. Test Circuit Common Mode Transient Immunity
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.6
www.fairchildsemi.com
12
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Test Circuits (Continued)
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Reflow Profile
Temperature (°C)
TP
260
240
TL
220
200
180
160
140
120
100
80
60
40
20
0
Maximum Ramp-up Rate = 3°C/S
Maximum Ramp-down Rate = 6°C/S
tP
Tsmax
tL
Preheat Area
Tsmin
ts
240
120
360
Time 25°C to Peak
Time (seconds)
Profile Freature
Pb-Free Assembly Profile
Temperature Min. (Tsmin)
150°C
Temperature Max. (Tsmax)
200°C
Time (tS) from (Tsmin to Tsmax)
60 to 120 s
Ramp-up Rate (tL to tP)
3°C/second maximum
Liquidous Temperature (TL)
217°C
Time (tL) Maintained Above (TL)
60 to 150 s
Peak Body Package Temperature
260°C +0°C / –5°C
Time (tP) within 5°C of 260°C
30 s
Ramp-down Rate (TP to TL)
6°C/s maximum
Time 25°C to Peak Temperature
8 minutes maximum
Figure 27. Reflow Profile
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.6
www.fairchildsemi.com
13
Part Number
Package
Packing Method
6N137M
DIP 8-Pin
Tube (50 units per tube)
6N137SM
SMT 8-Pin (Lead Bend)
Tube (50 units per tube)
6N137SDM
SMT 8-Pin (Lead Bend)
Tape and Reel (1,000 units per reel)
6N137VM
DIP 8-Pin, DIN EN/IEC 60747-5-5 Option
Tube (50 units per tube)
6N137SVM
SMT 8-Pin (Lead Bend), DIN EN/IEC 60747-5-5 Option
Tube (50 units per tube)
6N137SDVM
SMT 8-Pin (Lead Bend), DIN EN/IEC 60747-5-5 Option
Tape and Reel (1,000 units per reel)
6N137TVM
DIP 8-Pin, 0.4” Lead Spacing, DIN EN/IEC 60747-5-5 Option
Tube (50 units per tube)
6N137TSVM
SMT 8-Pin, 0.4” Lead Spacing, DIN EN/IEC 60747-5-5 Option
Tube (50 units per tube)
6N137TSR2VM
SMT 8-Pin, 0.4” Lead Spacing, DIN EN/IEC 60747-5-5 Option
Tape and Reel (1,000 units per reel)
Note:
The product orderable part number system listed in this table also applies to the HCPL2601M, HCPL2611M,
HCPL2630M and HCPL2631M product families.
Marking Information
1
V
3
6N137
2
XX YY B
6
5
4
Figure 28. Top Mark
Definitions
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.6
1
Fairchild Logo
2
Device Number
3
DIN EN/IEC60747-5-5 Option (only appears on component
ordered with this option)
4
Two Digit Year Code, e.g., ‘16’
5
Two Digit Work Week Ranging from ‘01’ to ‘53’
6
Assembly Package Code
www.fairchildsemi.com
14
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Ordering Information
D0
P0
t
K0
P2
E
F
A0
W1
d
t
P
User Direction of Feed
Symbol
W
W
B0
Description
D1
Dimension in mm
Tape Width
16.0 ± 0.3
Tape Thickness
0.30 ± 0.05
P0
Sprocket Hole Pitch
4.0 ± 0.1
D0
Sprocket Hole Diameter
1.55 ± 0.05
E
Sprocket Hole Location
1.75 ± 0.10
F
Pocket Location
7.5 ± 0.1
2.0 ± 0.1
P2
P
Pocket Pitch
A0
Pocket Dimensions
12.0 ± 0.1
10.30 ±0.20
B0
10.30 ±0.20
K0
4.90 ±0.20
W1
d
R
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.6
Cover Tape Width
13.2 ± 0.2
Cover Tape Thickness
0.1 Maximum
Maximum Component Rotation or Tilt
10°
Minimum Bending Radius
30
www.fairchildsemi.com
15
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Carrier Tape Specifications (Option SD)
D0
P0
t
K0
P2
E
F
A0
W1
d
P
User Direction of Feed
Symbol
W
W
B0
Description
D1
Dimension in mm
Tape Width
24.0 ± 0.3
Tape Thickness
0.40 ± 0.1
P0
Sprocket Hole Pitch
4.0 ± 0.1
D0
Sprocket Hole Diameter
1.55 ± 0.05
E
Sprocket Hole Location
1.75 ± 0.10
F
Pocket Location
11.5 ± 0.1
t
2.0 ± 0.1
P2
P
Pocket Pitch
16.0 ± 0.1
A0
Pocket Dimensions
12.80 ± 0.1
B0
10.35 ± 0.1
K0
5.7 ±0.1
W1
d
R
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.6
Cover Tape Width
21.0 ± 0.1
Cover Tape Thickness
0.1 Maximum
Maximum Component Rotation or Tilt
10°
Minimum Bending Radius
30
www.fairchildsemi.com
16
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Carrier Tape Specifications (Option TSR2)
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