74VHC14MTCX

Revised February 2005 74VHC14 Hex Schmitt Inverter General Description Features The VHC14 is an advanced high speed CMOS Hex Schmitt Inverter fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. Pin configuration and function are the same as the VHC04 but the inputs have hysteresis between the positive-going and negative-going input thresholds, which are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals, thus providing greater noise margin than conventional inverters. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. ■ High Speed: tPD 5.5 ns (typ) at VCC 5V ■ Low power dissipation: ICC 2 PA (Max) at TA ■ High noise immunity: VNIH VNIL 25qC 28% VCC (Min) ■ Power down protection is provided on all inputs ■ Low noise: VOLP 0.8V (Max) ■ Pin and function compatible with 74HC14 Ordering Code: Order Number Package Number Package Description 74VHC14M (Note 1) M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC14MX_NL (Note 2) M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC14SJ (Note 1) M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC14MTC (Note 1) MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC14MTC_NL (Note 3) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC14MTCX_NL (Note 2) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC14N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Pb-Free package per JEDEC J-STD-020B. Note 1: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Note 2: “_NL” indicates Pb-Free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only. Note 3: “_NL” indicates Pb-Free product (per JEDEC J-STD-020B). © 2005 Fairchild Semiconductor Corporation DS011617 www.fairchildsemi.com 74VHC14 Hex Schmitt Inverter June 1993 74VHC14 Connection Diagram Logic Symbol IEEE/IEC Pin Descriptions Truth Table Pin Names Description An Inputs On Outputs www.fairchildsemi.com 2 A O L H H L Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT) DC VCC /GND Current (ICC ) Storage Temperature (TSTG) Recommended Operating Conditions (Note 5) 0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC  0.5V 20 mA r20 mA r25 mA r50 mA 65qC to 150qC Output Voltage (VOUT) 0V to VCC 40qC to 85qC Operating Temperature (TOPR) Note 4: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. The data book specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Lead Temperature (TL) 260qC Soldering (10 seconds) 2.0V to 5.5V 0V to 5.5V Supply Voltage (VCC) Input Voltage (VIN) Note 5: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VP VN VH VOH VOL Parameter Positive Threshold Voltage Negative Threshold Voltage Hysteresis Voltage HIGH Level Output Voltage LOW Level Output Voltage IIN Input Leakage Current ICC Quiescent Supply Current VCC 25qC TA Min Typ 40qC to 85qC TA Max Min 2.20 2.20 4.5 3.15 3.15 5.5 3.85 3.85 3.0 0.90 0.90 4.5 1.35 1.35 5.5 1.65 1.65 3.0 0.30 1.20 0.30 1.20 0.40 1.40 0.40 1.40 5.5 0.50 1.60 0.50 1.60 2.0 1.9 2.0 1.9 2.9 3.0 2.9 4.5 4.4 4.5 4.4 3.0 2.58 2.48 4.5 3.94 3.80 Conditions V V 4.5 3.0 Units Max 3.0 V VIN VIL V V 2.0 0.0 0.1 0.1 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 VIN V IOH 50 PA IOH 4 mA IOH 8 mA IOL 50 PA IOL 4 mA IOL 8 mA VIH 3.0 0.36 0.44 4.5 0.36 0.44 0–5.5 r0.1 r1.0 PA VIN 5.5V or GND 5.5 2.0 20.0 PA VIN VCC or GND V Noise Characteristics Symbol Parameter TA VCC 25qC Typ Limits Units Conditions VOLP (Note 6) Quiet Output Maximum Dynamic VOL 5.0 0.4 0.8 V CL 50 pF VOLV (Note 6) Quiet Output Minimum Dynamic VOL 5.0 0.4 0.8 V CL 50 pF VIHD (Note 6) Minimum HIGH Level Dynamic Input Voltage 5.0 3.5 V CL 50 pF VILD (Note 6) Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL 50 pF Note 6: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHC14 Absolute Maximum Ratings(Note 4) 74VHC14 AC Electrical Characteristics Symbol Parameter tPLH Propagation Delay tPHL Time VCC 3.3 r 0.3 5.0 r 0.5 25qC TA Min TA 40qC to 85qC Typ Max Min Max 8.3 12.8 1.0 15.0 10.8 16.3 1.0 18.5 5.5 8.6 1.0 10.0 7.0 10.6 1.0 12.0 10 CIN Input Capacitance 4 CPD Power Dissipation Capacitance 21 10 Units ns ns Conditions CL 15 pF CL 50 pF CL 15 pF CL 50 pF pF VCC pF (Note 7) Open Note 7: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (Opr) C PD * VCC * fIN  ICC/6 (per Gate) www.fairchildsemi.com 4 74VHC14 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com 74VHC14 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 74VHC14 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 7 www.fairchildsemi.com 74VHC14 Hex Schmitt Inverter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8