ADCDS-1410
14-Bit, 10 Megapixels/Second, CCD Signal Processor
Typical unit
PRODUCT OVERVIEW FEATURES
n n n n n n n n n n
14-bit resolution 10MPPS throughput rate (14-bits) Extended temperature range -55°C to +100°C 1 LSB RMS Noise Excellent Signal-to-Noise ratio Edge triggered Small, 40-pin, TDIP package Low power, 800mW typical Low cost, functionally complete Programmable Analog Bandwidth
The ADCDS-1410 is an application-specific video signal processor designed for electronic-imaging applications that employ CCD's (charge coupled devices) as their photodetector. The ADCDS-1410 incorporates a "user configurable" input amplifier, a CDS (correlated double sampler) and a sampling A/D converter in a single package, providing the user with a complete, high performance, low-cost, low-power, integrated solution. The key to the ADCDS-1410's performance is a unique, high-speed, high-accuracy CDS circuit, which eliminates the effects of residual charge, charge injection and "kT/C" noise on the CCD's output floating capacitor, producing a "valid video" output signal. The ADCDS-1410 digitizes this resultant "valid video" signal using a high-speed, low-noise sampling A/D converter. The ADCDS-1410 requires only the rising edge of start convert pulse to initiate its conversion process. Additional features of the ADCDS-1410 include gain adjust, offset adjust, precision +2.4V reference, and a programmable analog bandwidth function.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
INPUT/OUTPUT CONNECTIONS Function Pin Function Fine Gain Adjust Offset Adjust Direct Input Inverting Input Non-Inverting Input +2.4v Ref. Output Analog Ground No Connect No Connect Bit 14 (Lsb) Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 No Connect +12v –5va Analog Ground +5va Analog Ground +5vd Digital Ground Digital Ground A1 AO No Connect No Connect Data Valid Reference Hold Start Convert Out-Of-Range Bit 1 (Msb) Bit 2 Bit 3
SIMPLIFIED SCHEMATIC
+12VA 39 INVERTING INPUT 4 75� 523� INPUT AMPLIFIER 0.01µF DIRECT INPUT 3 CORRELATED DOUBLE SAMPLER 23 BIT 1 (MSB) SAMPLING A/D 10 BIT 14 (LSB) OFFSET ADJUST 2 25 START CONVERT 1 FINE GAIN ADJUST –5VA 38 +5VA 36 +5VD 34
NON-INVERTING INPUT 5 5K �
REFERENCE HOLD 26
TIMING AND CONTROL
24 OUT-OF-RANGE 6 +2.4V REFERENCE OUTPUT
32, 33 DIGITAL GROUND
27 DATA VALID
30 31 AØ A1
7, 35, 37 ANALOG GROUND
Figure 1. ADCDS-1410 Functional Block Diagram
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MDA_ADCDS-1410.B02 Page 1 of 9
ADCDS-1410
14-Bit, 10 Megapixels/Second, CCD Signal Processor
Absolute Maximum Ratings
PARAMETERS +12V Supply (Pin 32) –5V Supply (Pin 38) +5V Supply (Pin 34, 36) Digital Input (Pin 25, 26, 30, 31) Analog Input (Pin 3,4,5) Lead Temperature (10 seconds) MIN. 0 –6.5 –0.3 –0.3 –5 — TYP. — — — — — — MAX. +14 +0.3 +6.5 Vdd+0.3V +5 300 UNITS Volts Volts Volts Volts Volts °C STATIC PERFORMANCE, continued DC Noise +25°C 0 to 70°C –55 to +100°C Offset Error +25°C 0 to 70°C –55 to +100°C Gain Error +25°C 0 to 70°C –55 to +100°C 0.350 — — 2.8 5000 10 — — — Volts p-p Ohm pF DYNAMIC PERFORMANCE Reference Hold Aquisition Time Droop @ 25°C +3.5 — — — — — — — — +.80 +10 –10 Volts Volts uA uA @ –55 to +100°C Signal-to-Noise Ratio Without Distortion (CDD-IN, input on pin (3) Input @ 98kHz) @ +25 °C @ 0 to +70°C +2.4 +4.5 — — — — — — — — +0.4 +0.1 Volts Volts Volts Volts @ –55 to +100°C (Input on pin (5) Input @ 98kHz) @ +25 °C @ 0 to +70°C @ –55 to +100°C 2.35 2.35 2.35 — 2.4 2.4 2.4 1.0 2.45 2.45 2.45 — Volts Volts Volts mA SIGNAL TIMING Conversion Rate –55 to +100°C Conversion Time Start Convert Pulse Width POWER REQUIREMENTS –.99 –.99 –.99 — — — 14 14 ±0.5 ±0.5 ±0.6 ±2.5 ±2.5 ±2.5 — — +1.5 +1.5 +1.5 — — — — — LSB LSB LSB LSB LSB LSB LSB LSB Power Supply Range +12V Supply +5V Supply –5V Supply +11.4 +4.75 –4.75 +12.0 +5.0 –5.0 +12.6 +5.25 –5.25 Volts Volts Volts 10 — — — 100 150 — — — MSPS nsec nsec 73 73 70 75 75 73 — — — dB dB dB 73 73 70 75 75 73 — — — dB dB dB — — 25 100 — — mV/us mV/us — 40 — ns — — — ±1.00 ±1.35 ±1.35 ±3.0 ±3.0 ±6.0 %FSR %FSR %FSR — — — ±0.6 ±0.6 ±0.6 ±3.0 ±3.0 ±6.0 %FSR %FSR %FSR — — — 0.75 0.75 0.75 1 1 1 LSB LSB LSB MIN. TYP. MAX. UNITS
Functional Specifications
The following specifications apply over the operating temperature range, under the following conditions: Vcc=+12V, +Vdd=+5V, Vee=–5V, fin=98KHz, sample rate=10MSPS
ANALOG INPUT Input Voltage Range (externally configurable) Input Resistance Input Capacitance DIGITAL INPUTS Logic Levels Logic 1 Logic 0 Logic Loading Logic 1 Logic 0 DIGITAL OUTPUTS Logic Levels Logic 1 (IOH = .5ma) Logic 1 (IOH = 50µa) Logic 0 (IOL = 1.6ma) Logic 0 (IOL = 50ua) Internal Reference Voltage (Fine gain adjust pin (1) grounded) +25°C 0 to 70°C –55 to +100°C External Current STATIC PERFORMANCE Differential Nonlinearity (Histogram, 98kHz) +25°C 0 to 70°C –55 to +100°C Integral Nonlinearity +25°C 0 to 70°C –55 to +100°C Guaranteed No Missing Codes 0 to 70°C –55 to +100°C MIN. TYP. MAX. UNITS
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MDA_ADCDS-1410.B02 Page 2 of 9
ADCDS-1410
14-Bit, 10 Megapixels/Second, CCD Signal Processor
POWER REQUIREMENTS Power Supply Current +12V Supply Power Supply Current +5V Supply -5V Supply Power Dissipation Power Supply Rejection (5%) @ +25°C ENVIRONMENTAL Operating Temperature Range ADCDS-1410 ADCDS-1410EX Storage Temperature Package Type Weight 0 –55 –65 — — — +70 +100 +150 °C °C °C — ±0.04 ±0.06
%FSR/%V
MIN. — — — —
TYP. +20 +65 -50 0.8
MAX. +26 +70 -55 0.99
UNITS mA
external calibration. If required, the device's small initial offset and gain errors can be reduced to zero using the FINE GAIN ADJUST (pin1) and OFFSET ADJUST (pin 2) features. Direct Mode (AC Coupled)
mA mA Watts
This is the most common input configuration as it allows the ADCDS-1410 to interface directly to the output of the CCD with a minimum amount of analog "front-end" circuitry. This mode of operation is used with full-scale video input signals from 0.350Vp-p to 2.8Vp-p. Figure 2a. describes the typical configuration for applications using a video input signal with a maximum amplitude of 0.350Vp-p. The coarse gain of the input amplifier is determined from the following equation: VOUT = 2.8Vp-p = VIN*(1+(523/75)), with all internal resistors having a 1% tolerance. Additional fine gain adjustment can be accomplished using the Fine Gain Adjust (pin 1 see Figure 5). Figure 2b. describes the typical configuration for applications using a video input signal with an amplitude greater than 0.350Vp-p and less than 2.8Vp-p. Using a single external series resistor (see Figure 4.), the coarse gain of the ADCDS-1410 can be set, with additional fine gain adjustments being made using the Fine Gain Adjust function (pin 1 see Figure 5). The coarse gain of the input amplifier can be determined from the following equation: VOUT = 2.8Vp-p = VIN*(1+(523/(75+Rext))), with all internal resistors having a 1% tolerance.
4 75� 0.01µF VOUT = 2.8Vp-p 523�
40-pin, TDIP 16.10 grams
TECHNICAL NOTES 1. Obtaining fully specified performance from the ADCDS-1410 requires careful attention to pc-card layout and power supply decoupling. The device's analog and digital grounds are connected to each other internally. Depending on the level of digital switching noise in the overall CCD system, the performance of the ADCDS-1410 may be improved by connecting all ground pins (7,32,33,35, 37) to a large analog ground plane beneath the package. The use of a single +5V analog supply for both the +5VA (pin 36) and +5VD (pin 34) may also be beneficial. 2. Bypass all power supplies to ground with a 4.7µf tantalum capacitor in parallel with a 0.1µf ceramic capacitor. Locate the capacitors as close to the package as possible. 3. If using the suggested offset and gain adjust circuits (Figure 3 & 5), place them as close to the ADCDS-1410's package as possible. 4. A0 and A1 (pins 30, 31) should be bypassed with 0.1µf capacitors to ground to reduce susceptibility to noise. ADCDS-1410 Modes of Operation The input amplifier stage of the ADCDS-1410 provides the designer with a tremendous amount of flexibility. The architecture of the ADCDS-1410 allows its input-amplifier to be configured in any of the following configurations: • Direct Mode (AC coupled) • Non-Inverting Mode • Inverting Mode When applying inputs which are less than 2.8Vp-p, a coarse gain adjustment (applying an external resistor to pin 4) must be performed to ensure that the full scale video input signal (saturated signal) produces a 2.8Vp-p signal at the input-amplifier's output (Vout). In all three modes of operation, the video portion of the signal at the CDS input (i.e. input-amplifier's Vout) must be more negative than its associated reference level and Vout should not exceed ±2.8V DC. The ADCDS-1410 achieves it specified accuracies without the need for
VIN NO CONNECT
3 5
5k�
Figure 2a.
Rext 4 75� 0.01µF VOUT = 2.8Vp-p 523�
VIN NO CONNECT
3 5
5k�
Figure 2b.
Rext 4 75� 0.01µF VOUT = 2.8Vp-p 523�
NO CONNECT VIN
3 5
5k�
Figure 2c.
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MDA_ADCDS-1410.B02 Page 3 of 9
ADCDS-1410
14-Bit, 10 Megapixels/Second, CCD Signal Processor
Non-Inverting Mode The non-inverting mode of the ADCDS-1410 allows the designer to either attenuate or add non-inverting gain to the video input signal. This configuration also allows bypassing the ADCDS-1410's internal coupling capacitor, allowing the user to provide an external capacitor of appropriate value. Figure 2c. describes the typical configuration for applications using video input signals with amplitudes greater than 0.350Vp-p and less than 2.8Vp-p (with common mode limit of ±2.5V DC). Using a single external series resistor (see Figure 4.), the coarse gain of the ADCDS-1410 can be set with additional fine gain adjustments being made using the Fine Gain Adjust function (pin 1 see Figure 5). The coarse gain of the circuit can be determined from the following equation: VOUT = 2.8Vp-p = VIN*(1+(523/(75+Rext))), with all internal resistors having a 1% tolerance. Figure 2d. describes the typical configuration for applications using a video input signal whose amplitude is greater than 2.8Vp-p. Using a single external series resistor (Rext 1) in conjunction with the internal 5K (1%) resistor to ground, an attenuation of the input signal can be achieved. Additional fine gain adjustments being made using the Fine Gain Adjust function (pin 1). The coarse gain of this circuit can be determined from the following equation: VOUT = 2.8Vp-p = [VIN*(5000/(Rext1+5000))]* [1+(523/(75+Rext2))], with all internal resistors having a 1% tolerance.
Rext2 4 75� 0.01µF VOUT = 2.8Vp-p 523�
Inverting Mode The inverting mode of operation can be used in applications where the analog input to the ADCDS-1410 has a video input signal whose amplitude is more positive than its associated reference level. The ADCDS-1410s correlated double sampler (i.e. input amplifier's VOUT) requires that the video signal's amplitude be more negative than its reference level at all times (see timing diagram for details). Using the ADCDS-1410 in the inverting mode allows the designer to perform an additional signal inversion to correct for any analog "front end" pre-processing that may have occurred prior to the ADCDS-1410. Figure 2e. describes the typical configuration for applications using a video input signal with a maximum amplitude of 0.350Vp-p. Additional fine gain adjustments can be made using the Fine Gain Adjust function (pin 1). The coarse gain of this circuit can be determined from the following equation: VOUT = 2.8Vp-p = –VIN*(523/75), with all internal resistors having a 1% tolerance. Figure 2f. describes the typical configuration used in applications needing to invert video input signals whose amplitude is greater than 0.350Vp-p. Using a single external series resistor (see Figure 4.), the initial gain of the ADCDS-1410 can be set, with additional fine gain adjustments being made using the Fine Gain Adjust function (pin 1). The coarse gain of this circuit can be determined from the following equation: VOUT = 2.8Vp-p = –VIN*(523/75+Rext), with all internal resistors having a 1% tolerance.
ADCDS-1405 10
NO CONNECT Rext1 VIN
3 5
+5V 20KΩ
5k�
External Series Resistor
Offset Adjust 2
Figure 2d.
4 75� 0.01µf VOUT = 2.8Vp-p 523�
–5V
–VIN
Figure 3. Offset Adjustment Circuit
NO CONNECT
3 5
5k�
Coarse Gain Adjustment Plot External Gain Resistor vs. Full Scale Video Input
External Gain Resistor (Ohms)
10000
Direct Mode & Non-Inverting Mode Inverting Mode
Figure 2e.
Rext –VIN 4 75� 0.01µf VOUT = 2.8Vp-p 523�
1000
NO CONNECT
3 5
100
5k�
10 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 Full Scale Video Signal (Volts)
Figure 4. Coarse Gain Adjustment Plot Figure 2f.
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MDA_ADCDS-1410.B02 Page 4 of 9
ADCDS-1410
14-Bit, 10 Megapixels/Second, CCD Signal Processor
Offset Adjustment Manual offset adjustment for the ADCDS-1410 can be accomplished using the adjustment circuit shown in Figure 3. A software controlled D/A converter can be substituted for the 20KΩ potentiometer. The offset adjustment feature allows the user to adjust the Offset/Dark Current level of the ADCDS-1410 until the output bits are 00 0000 0000 0000 and the LSB flickers between 0 and 1. Offset adjust should be performed before gain adjust to avoid interaction. The ADCDS1410's offset adjustment is dependent on the value of the external series resistor used in the offset adjust circuit (Figure 3). The Offset Adjustment graph (Figure 6) illustrates the typical relationship between the external series resistor value and its offset adjustment capability utilizing ±5V supplies. Offset Adjustment Sensitivity It should be noted that with increasing amounts of offset adjustment (smaller values of external series resistors), the ADCDS-1410 becomes more susceptible to power supply noise or voltage variations seen at the wiper of the offset potentiometer. Fine Gain Adjustment Fine gain adjustment (pin 1) is provided to compensate for the tolerance of the external coarse gain resistor (Rext) and/or the unavailability of exact coarse gain resistor (Rext) values. Note, the fine gain adjustment will not change the expected input amplifier's full scale VOUT (2.8Vp-p.) Instead, the gain of the ADCDS-1410's internal A/D is adjusted allowing the actual input amplifier's full scale VOUT to produce an output code of all ones (11 1111 1111 1111). Fine gain adjustment for the ADCDS-1410 is accomplished using the adjustment circuit shown below (Figure 5). A software controlled D/A converter can be substituted for the 20KΩ potentiometer. The fine gain adjust circuit ensures that the video input signal (saturated signal) will be properly scaled to obtain the desired Full Scale digital output of 11 1111 1111 1111, with the LSB flickering between 0 and 1. Fine gain adjust should be performed following the offset adjust to avoid interaction. The fine gain adjust provides ±256 codes of adjust when ±5V supplies are used for the Fine Gain Adjust Circuit. For Example: External 50KΩ resistor: 1. 10mV of noise or voltage variation at the potentiometer will produce 0.25LSB's of output variation. 2. 100mV of noise or voltage variation at the potentiometer will produce 2.5LSB's of output variation. The Offset Adjustment Sensitivity graph (Figure 7) illustrates the offset adjustment sensitivity over a wide range of external resistor and noise values. If a large offset voltage is required, it is recommended that a very low noise external reference be used in the offset adjust circuit in place of power supplies. The ADCDS-1410's +2.4V reference output could be configured to provide the reference voltage for this type of application.
10 ADCDS-1405
+5V 20KΩ Fine Gain Adjust 1
–5V
Figure 5. Fine Gain Adjustment Circuit
Offset Adjustment vs. External Series Resistor 10000
±LSB's of Adjustment
Offset Adjustment Sensitivity External Series Resistor vs. Output Variation (LSB's) 100
Output Variation (LSB's)
1000
10
Peak-Peak variation at potentiometer 100mV 10mV 1mV
0 5K 10K 15K 20K 25K 30K 35K 40K 45K 50K 55K 60K
1
100
0.1
10
0
5k
10k 15k
20k 25k
30k 35k
40k 45k
50k
55k 60k
0.01
External Series Resistor (Ohm's)
External Series Resistor Value (Ohms)
Figure 6. Offset Adjustment vs. External Series Resistor
Figure 7. Offset Adjustment Sensitivity
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MDA_ADCDS-1410.B02 Page 5 of 9
ADCDS-1410
14-Bit, 10 Megapixels/Second, CCD Signal Processor
Out-of-Range Indicator
Output Coding The ADCDS-1410's output coding is Straight Binary as indicated in Table 2. The table shows the relationship between the output data coding and the difference between the reference signal voltage and its corresponding video signal voltage. (These voltages are referred to the output of the ADCDS-1410's input amplifier's VOUT). Programmable Analog Bandwidth Function When interfacing to CCD arrays with very high-speed "readout" rates, the ADCDS-1410's input stage must have sufficient analog bandwidth to accurately reproduce the output signals of the CCD array. The amount of analog bandwidth determines how quickly and accurately the "Reference Hold" and the "CDS output" signals will settle. If only a single analog bandwidth was offered, the ADCDS-1410's bandwidth would be set to acquire and digitize CCD output signals to 14-bit accuracy, at maximum conversion rate of 10MHz (100ns see Figure 11. for details). Applications not requiring the maximum conversion rate would be forced to use the full analog bandwidth at the possible expense of noise performance. The ADCDS-1410 avoids this situation by offering a fully programmable analog bandwidth function. The ADCDS-1410 allows the user to "bandwidth limit" the input stage in order to realize the highest level of noise performance for the application being considered. Table 3. describes how to select the appropriate reference hold "aquisition time" and CDS output "settling time" needed for a particular application. Each of the selections listed in Table 3. have been optimized to provide only enough analog bandwidth to acquire a full scale input step, to 14-bit accuracy, in a single conversion. Increasing the analog bandwidth (using a faster settling and acquisition time) would only serve to potentially increase the amount of noise at the ADCDS-1410's output. The ADCDS-1410 uses a two bit digital word to select four different analog bandwidths for the ADCDS1410's input stage (See Table 3. for details).
The ADCDS-1410 provides a digital Out-of-Range output signal (pin 24) for situations when the video input signal (saturated signal) is beyond the input range of the internal A/D converter. The digital output bits and the Out-of-Range signal correspond to a particular sampled video input range, with both of these signals having a common pipeline delay. Using the circuit described in Figure 8, both over-range and under-range conditions can be detected (see Table 1). When combined with a D/A converter, digital detection and correction can be performed for both the gain and offset errors.
MSB
"OVERRANGE"
OUT-OF-RANGE "UNDERRANGE"
Figure 8. Overrange/ underrange Circuit
Table 1. Out-of-Range Conditions OuT OF RANGE 0 0 1 1 MSB 0 1 0 1 OvER RANGE 0 0 0 1 uNDER RANGE 0 0 1 0 INPuT SIGNAL In Range In Range Underrrange Overrange
Table 2. Output Coding INPuT AMPLIFIER vOuT, ➀ (vOLTS P-P) Video Signal-Reference Signal Video Signal-Reference Signal
Notes:
SCALE
DIGITAL OuTPuT 11 1111 1111 1111 11 1111 1111 1111 11 0000 0000 0000 10 0000 0000 0000 01 0000 0000 0000 00 1000 0000 0000 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000
OuT-OF-RANGE 1 0 0 0 0 0 0 0 1
> –2.80000 >Full Scale –1LSB –2.80000 Full Scale –1LSB –2.10000 3/4FS –1.40000 1/2FS –0.70000 1/4FS –0.35000 1/8FS –0.000171 1 LSB 0 0
