ADCDS-1603-C

ADCDS-1603 16-Bit, 2.3 Megapixels/Second CCD Signal Processor 　 For full details go to www.murata-ps.com/rohs FEATURES 2.3 MPPS Internal 16-bit resolution A/D Internal correlated doubler sampler (CDS) Resistor programmable gain adjustment from 0dB to 15.5dB 1.3 LSB RMS Noise Small, 40-pin, TDIP or SMT package Analog front end programmable bandwidth Extended temperature range –40ºC to +125ºC Low power, 674mW Low cost, functionally complete FUNCTIONAL BLOCK DIAGRAM PRODUCT OVERVIEW The ADCDS-1603 is an application-specific CCD signal processor designed for electronic-imaging applications that employ CCD's (charge coupled devices) as their photodetector. The ADCDS-1603 incorporates a "user configurable" input amplifier, a CDS (correlated double sampler) and a 16-bit resolution sampling A/D converter in a single package, providing the user with a complete, high performance, low-cost, low-power, integrated solution. The key to the ADCDS-1603's performance is a unique, high-speed, high-accuracy CDS circuit, which eliminates the effects of residual charge, charge injection and "kT/C" noise on the CCD's output floating capacitor, producing a pixel data output signal. The ADCDS-1603 digitizes this resultant pixel data signal using a high-speed, low-noise sampling A/D converter. The ADCDS-1603 requires only the rising edge of start convert pulse to initiate its conversion process and a Reference Hold command to acquire and hold the CCD reference level output. Additional features of the ADCDS-1603 include gain adjust, offset adjust, precision +2.048V reference, and a programmable analog bandwidth function. –5VA 38 499 INVERTING INPUT 4 100 INPUT AMPLIFIER 0.01μF DIRECT INPUT 3 NON-INVERTING INPUT 5 5K 22pf +5VA 36 +5V D 34 23 BIT 1 (MSB) CORRELATED DOUBLE SAMPLER SAMPLING A/D 8 BIT 16 (LSB) OFFSET ADJUST 2 REFERENCE HOLD 26 START CONVERT 25 TIMING AND CONTROL 6 +2.048V REFERENCE OUTPUT 32, 33 DIGITAL GROUND 27 DATA VALID 30 31 AØ A1 7, 35, 37 ANALOG GROUND www.murata-ps.com Technical enquiries email: sales@murata-ps.com, tel: +1 508 339 3000 MDA_ADCDS-1603.E06 Page 1 of 11 ADCDS-1603 16-Bit, 2.3 Megapixels/Second CCD Signal Processor ABSOLUTE MAXIMUM RATINGS Parameters –5V Supply (Pin 38) +5V Supply (Pin 34, 36) Digital Input (Pin 25, 26, 30, 31) Analog Input (Pin 3, 4, 5) Lead Temperature Min. –6.5 –0.3 –0.3 –6 – Typ. – – – – – Max. +0.3 +6.5 Vdd+0.3V +6 300 Units Volts Volts Volts Volts °C 1.0 MHz HI LO 1.8 MHz LO HI Noise DC Noise Gain = 1 (pin 4 = NC) Start Convert Rate 2.3 MHz A1 A0 Min. Typ. Max. Units LO LO 2 63 1.5 48 1.3 41 1.3 41 LSB RMS uV RMS LSB RMS uV RMS LSB RMS uV RMS LSB RMS uV RMS FUNCTIONAL SPECIFICATIONS The following specifications apply over the operating temperature range, under the following conditions: +5VA = +5V, +5VD = 5V, –5VA = –5V, sample rate = 2.3MHz. Analog Input Input Voltage Range (Reference Signal - Pixel data Signal) Gain of 5.99 (Pin 4 to GND) Gain of 1 (Pin 4 Open) Input Resistance Input Capacitance Digital Inputs Logic Levels Logic 1 A0, A1 (pins 30, 31) Logic 0 A0, A1 (pins 30, 31) Logic 1 (pins 25, 26) Logic 0 (pins 26, 26) Logic Loading Logic 1 Logic 0 Digital Outputs Logic Levels (pins 8-23) Logic 1 (0.5mA) Logic 0 (0.5mA) Logic Levels (pin 27) Logic 1 (0.5mA) Logic 0 (0.5mA) Internal Reference Voltage (Fine gain adjust pin 1 grounded) +25°C 0 to 70°C –40 to +125°C Reference Current Linearity Differential Nonlinearity (Histogram, 98kHz) +25°C 0 to 70°C –40 to +125°C Integral Nonlinearity +25°C 0 to 70°C –40 to +125°C Guaranteed No Missing Codes 0 to 70°C –40 to +125°C 2.8 – 4.5 – 3.0 – 5.0 – 3.3 +0.4 Volts Volts Volts Volts 4.5 – +2.4 – – – – – – – – – +Vdd 0.4 – +0.8 +10 -10 Volts Volts Volts Volts uA uA Min. Typ. Max. Units 800 MHz DC Noise Gain = 5.99 (pin 4 = GND) Start Convert Rate 2.3 MHz HI HI LO LO – – – – – – 5000 22 0.342 2.048 – – V p-p V p-p Ohms pF 1.0 MHz HI LO 1.8 MHz LO HI 2.5 13 2.0 10.8 1.6 8.5 1.6 8.5 Max. 1 1 1.5 1 1 1.5 Max. – 3.5 2.5 Max. 2.063 2.063 2.063 LSB RMS uV RMS LSB RMS uV RMS LSB RMS uV RMS LSB RMS uV RMS Units %FSR %FSR %FSR %FSR %FSR %FSR Units MHz V V Units V V V 800 MHz Offset/Gain Offset Error Gain = 1 +25°C 0 to 70°C –40 to +125°C Gain Error Gain = 1 +25°C 0 to 70°C –40 to +125°C Bandwidth Input Amplifier –3db BW Input Common Mode Voltage Output Voltage Swing Reference Reference Voltage +25ºC Reference Voltage 0 to +70ºC Reference Voltage -40 to +125ºC HI Min. – – – – – – Min. 13.5 –3.5 –2.5 Min. 2.033 2.033 2.033 HI Typ. 0.5 0.5 0.5 0.5 0.5 0.5 Typ. – – – Typ. 2.048 2.048 2.048 +0.4 2.038 2.038 2.028 – 2.048 2.048 2.048 2.058 2.058 2.068 0.2 Volts Volts Volts mA –0.90 –0.90 –0.98 – – – 16 16 ±0.5 ±0.5 ±0.6 ±1 ±1 ±2 – – +1.2 +1.2 +2 – – – – – LSB LSB LSB LSB LSB LSB LSB LSB www.murata-ps.com Technical enquiries email: sales@murata-ps.com, tel: +1 508 339 3000 MDA_ADCDS-1603.E06 Page 2 of 11 ADCDS-1603 16-Bit, 2.3 Megapixels/Second CCD Signal Processor Signal Timing Conversion Rate (–40 to 125°C) Conversion Time Start Convert Pulse Width Power Requirements Power Supply Range +5V A Supply –5V Supply +5V D Supply Power Supply Currents +5V Supply –5V Supply +5V D Supply Power Dissipation Power Supply Rejection (5%) @25°C Environmental Operating Temperature Range ADCDS-1603 ADCDS-1603EX Storage Temperature Package Type Weight Pin Type Cover See Table 3. See Timing Specs, Table 2. See Technical Note: Optimal Performance. CMOS Loading A0, A1 = LO 0.001 434 20 – – 50 2.3 – 140 MHz nSec nSec 3. Offset adjustment resistor (Figure 3), Rext (Figure 2b, 2c, & 2f), and Rext1 & Rext2 (Figure 2d) should be placed as close to the ADCDS-1603 as possible. 4. A0 and A1 (pins 30, 31) should be bypassed with 0.1μf capacitors to ground to reduce susceptibility to noise. ADCDS-1603 Modes of Operation +4.75 –4.75 –4.75 – – – – +5.0 –5.0 +5.0 +78 –47 +10 635 ±0.01 +5.25 –5.25 +5.25 +83 –52 +12 735 ±0.03 Volts Volts Volts mA mA mA mW %FSR/%V The input amplifier stage of the ADCDS-1603 provides the designer with a tremendous amount of flexibility. The architecture of the ADCDS-1603 allows its input-amplifier to be configured in any of the following configurations: When applying inputs that are less than 2.048Vp-p, a coarse gain adjustment (applying an external resistor to pin 4) must be performed to ensure that the full scale pixel data input signal (saturated signal) produces 2.048Vp-p signal at the input-amplifier's output (VOUT) (See figure 2b & 2C). In all three modes of operation, the pixel data portion of the signal at the CDS input (i.e. input-amplifier's VOUT) must be more negative than its associated reference level and VOUT should not exceed 2.048Vdc. The ADCDS-1603 achieves its specified accuracies without the need for external calibration. If required, the device's small initial offset error can be reduced to zero using the OFFSET ADJUST (pin 2) feature (See figure 3). For fine gain adjustment model, contact the factory. Direct Mode (AC Coupled) This is the most common input configuration as it allows the ADCDS-1603 to interface directly to the output of the CCD with a minimum amount of analog "front-end" circuitry. This mode of operation is used with full-scale pixel data input signals from 0.342Vp-p to 2.048Vp-p. Figure 2a. describes the configuration for applications using a pixel data input signal with a maximum amplitude of 0.342Vp-p. In this case the input amplifier is configured for the maximum gain of 5.99 (VOUT = 1+(499/100)). All input resistors having a 0.1% tolerance. Figure 2b. describes the configuration for applications using a pixel data input signal with an amplitude greater than 0.342Vp-p and less than 2.048Vp-p. Using a single external series resistor, the coarse gain of the ADCDS-1603 can be set. The coarse gain of the input amplifier can be determined fron the following equation: VOUT = 2.048Vp-p = VIN* (1+(499/(100+Rext))) (all internal resistors having a 0.1% tolerance). 0 –40 –65 – – – +70 +125 +150 °C °C °C 40-Pin, TDIP, 2.24" × 1.27" FR4 PCB 18.1 Grams .020 Diameter Au Plate Phosphor Bronze Tin Plate Steel TECHNICAL NOTES 1. Obtaining fully specified performance from the ADCDS-1603 requires careful attention to pc-board layout and power supply decoupling. The device's analog and digital grounds are connected to each other internally. Depending on the level of digital switching noise in the overall CCD system, the performance of the ADCDS-1603 may be improved by connecting all ground pins (7,32,33,35, 37) to a large analog ground plane beneath the package. The use of a single +5V analog supply for both the +5VA (pin 36) and +5VD (pin 34) may also be beneficial. 2. Bypass all power supplies to ground with a 4.7μf ceramic capacitor in parallel with a 0.1μf ceramic capacitor. Locate the capacitors as close to the package as possible. 4 100 499 Rext 4 100 499 Rext 4 100 499 VIN N.C. 3 5 0.01μF VOUT = 2.048Vp-p 22pf VIN N.C. 3 5 0.01μF V OUT = 2.048Vp-p 22pf N.C. VIN 3 5 0.01μF V OUT = 2.048Vp-p 22pf 5k 5k 5k Figure 2a. Direct Mode Figure 2b. Direct Mode Figure 2c. Non-inverting Mode www.murata-ps.com Technical enquiries email: sales@murata-ps.com, tel: +1 508 339 3000 MDA_ADCDS-1603.E06 Page 3 of 11 ADCDS-1603 16-Bit, 2.3 Megapixels/Second CCD Signal Processor Non-Inverting Mode The non-inverting mode of the ADCDS-1603 allows the designer to either attenuate or add non-inverting gain to the pixel data input signal. This configuration also allows bypassing the ADCDS-1603's internal coupling capacitor, allowing the user to provide an external capacitor of appropriate value. Figure 2c. describes the typical configuration for applications using pixel data input signals with amplitudes greater than 0.342Vp-p and less than 2.048Vp-p. Using a single external series resistor, the coarse gain of the ADCDS-1603 can be set. The coarse gain of the circuit can be determined from the following equation: VOUT = 2.048Vp-p = VIN*(1+(499/(100+Rext))), with all internal resistors having a 0.1% tolerance. Figure 2d. describes the typical configuration for applications using a pixel data input signal whose amplitude is greater than 2.048Vp-p. Using a single external series resistor (Rext 1) in conjunction with the internal 5K (1%) resistor to ground, an attenuation of the input signal can be achieved. The coarse gain of this circuit can be determined from the following equation: VOUT = 2.048Vp-p = [VIN*(5000/(Rext1+5000))]* [1+(499/(100+Rext2))], with all internal resistors having a 0.1% tolerance. Inverting Mode The inverting mode of operation can be used in applications where the analog input to the ADCDS-1603 has a pixel data input signal whose amplitude is more positive than its associated reference level. The ADCDS-1603's correlated double sampler (i.e. input amplifier's VOUT) requires that the pixel data signal's amplitude be more negative than its reference level at all times (see timing diagram for details). Using the ADCDS-1603 in the inverting mode allows the designer to perform an additional signal inversion to correct for any analog "front end" preprocessing that may have occurred prior to the ADCDS-1603. Figure 2e. describes the typical configuration for applications using a pixel data input signal with a maximum amplitude of 0.342Vp-p. The coarse gain of this circuit can be determined from the following equation: VOUT = 2.048Vp-p = –VIN*(499/100), with all internal resistors having a 0.1% tolerance. Figure 2f. describes the typical configuration used in applications needing to invert pixel data input signals whose amplitude is greater than 0.342Vp-p. Using a single external series resistor, the initial gain of the ADCDS-1603 can be set. The coarse gain of this circuit can be determined from the following equation: VOUT = 2.048Vp-p = –VIN*(499/100+Rext), with all internal resistors having a 0.1% tolerance. Offset Adjustment Manual offset adjustment for the ADCDS-1603 can be accomplished using the adjustment circuit shown in Figure 3. A software controlled D/A converter can be substituted for the 20KΩ potentiometer. The offset adjustment feature allows the user to adjust the Offset/Dark Current level of the ADCDS-1603 until the output bits are 00 0000 0000 0000 and the LSB flickers between 0 and 1. The ADCDS-1603's offset adjustment is dependent on the value of the external series resistor used in the offset adjust circuit (Figure 3) and the gain of the input-amplifier. It should be noted that with increasing amounts of offset adjustment (smaller values of external series resistors), the ADCDS-1603 becomes more susceptible to power supply noise or voltage variations seen at the wiper of the offset potentiometer. Rext2 4 100 499 –VIN Rext 4 100 499 3 NO CONNECT Rext1 VIN 5 0.01μF V OUT = 2.048Vp-p NO CONNECT 3 5 0.01μf VOUT = 2.048Vp-p 5k 22pf 5k 22pf Figure 2d. Non-inverting Mode Figure 2f. Inverting Mode –VIN 4 100 499 +5V External Series Resistor ADCDS-1603 NO CONNECT 3 5 0.01μf VOUT = 2.048Vp-p 20k Offset Adjust 2 5k 22pf –5V Figure 2e. Inverting Mode Figure 3. Offset Adjustment Circuit www.murata-ps.com Technical enquiries email: sales@murata-ps.com, tel: +1 508 339 3000 MDA_ADCDS-1603.E06 Page 4 of 11 ADCDS-1603 16-Bit, 2.3 Megapixels/Second CCD Signal Processor Fine Gain Adjustment For fine gain adjustment model, contact the factory. Output Coding The ADCDS-1603's output coding is Straight Binary as indicated in Table 1. The table shows the relationship between the output data coding and the difference between the reference signal voltage and its corresponding pixel data signal voltage. Table 1. Output Coding Reference – Pixel Data (V) >+2.048 2.048 1.536 1.024 0.512 0.256 0.00003125 0 Full Scale Full Scale -1LSB 3/4FS 1/2FS 1/4FS 1/8FS 1LSB 0