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ADS-235, ADS-236, ADS-237
12-Bit, 5MHz and 9MHz Sampling A/D Converters
FEATURES
· · · · · · · · · · 5MHz (ADS-235/236) and 9MHz (ADS-237) sampling rates Low power Outstanding dynamic performance Fully differential or single-ended analog input 100MHz full power input bandwidth Integral sample-and-hold Single +5V supply operation Internally generated DC bias Voltage 3.0/5.0V CMOS compatible digital output TTL/CMOS compatible digital inputs/outputs
GENERAL DESCRIPTION
The ADS-235, ADS-236 and ADS-237 are monolithic, 12-bit, sampling analog-to-digital converters fabricated in a CMOS process. The converters are designed for applications where high speed, wide bandwidth and low power dissipation are essential. These characteristics are provided through the use of a fully differential sampling pipeline A/D architecture with digital error correction logic. The ADS-235, ADS-236 and ADS-237 offer excellent dynamic performance while consuming only 300mW. The digital output circuit is separate and can be powered from either a 3V or 5V supply allowing the user to interface with 3V logic, if desired. The ADS-235, ADS-236 and ADS-237 provide the user with an internally generated DC bias voltage output. This DC bias voltage is ideal for AC coupled analog input applications. The units are available in a 28-lead plastic SOIC package and operate over the 0°C to 70°C and –40 to +85°C temperature ranges.
INPUT/OUTPUT CONNECTIONS
PIN FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLK, CLOCK +DVS1, +5V DIG. SUP. DGND1 +DVS1, +5V DIG. SUP. DGND1 +AVS, +5V ANALOG SUP. AGND VIN+, ANALOG INPUT VIN–, ANALOG INPUT VDC, DC BIAS OUTPUT VROUT, REF. OUT VRIN, REF. IN AGND +AVS, +5V ANALOG SUP. PIN FUNCTION 28 27 26 25 24 23 22 21 20 19 18 17 16 15 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 +DVS2, DIG. OUTPUT SUP. DGND2 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (MSB)
Stage 4 4-Bit Flash A/D X8 Stage 3
–
+
15 Bit 1 (MSB) 16 Bit 2 17 Bit 3 18 Bit 4
4-Bit Flash A/D
19 Bit 5
4-Bit DAC Digital Delay and Error Correction
20 Bit 6 23 Bit 7 24 Bit 8 25 Bit 9 26 Bit 10 27 Bit 11 28 Bit 12 (LSB)
X8 Stage 1 VROUT 11 Reference VRIN 12 VIN+ VIN– 8 9
+ –
S/H
4-Bit Flash A/D
4-Bit DAC
VDC 10
2.3 Volt DC Bias Output Clock 1 CLK
2, 4 +DVS1
3, 5 DGND 1
6, 14 +AVS
7, 13 AGND
22 +DVS2
21 DGND 2
Figure 1. ADS-235, ADS-236 and ADS-237 Functional Block Diagram
DATEL, Inc., Mansfield, MA 02048 (USA) · Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 · Email: sales@datel.com · Internet: www.datel.com
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ADS-235, ADS-236, ADS-237
ABSOLUTE MAXIMUM RATINGS
PARAMETERS +AVS, +DVS1 and +DVS2 Supplies DGND to AGND Analog I/O Pins Digital I/O Pins Lead Temperature (10 seconds, Pin Tips Only) LIMITS +6.0 0.3 AGND to +AVS Supply DGND to +DVS Supply 300 UNITS Volts Volts Volts Volts °C
PHYSICAL/ENVIRONMENTAL
PARAMETERS Operating Temperature Range ADS-235S ADS-236S/ADS-237S Storage Temperature Range Thermal Resistance, qja ➀ Junction Temperature Package Type MIN. 0 –40 –65 — — TYP. MAX. UNITS °C °C °C °C/W °C
— 70 — 85 — 150 75 — 150 28-Pin Plastic SOIC
FUNCTIONAL SPECIFICATIONS
➀ Measured mounted on PC board in free air.
(TA = +25°C, (ADS-235), TMIN to TMAX (ADS-236/237), +DVS1 = +DVS2 = +AVS = +5V, VRIN = 3.5V, FS = 5MHz (ADS-235/236) and 9MHz (ADS-237) at a 50% duty cycle, CL =10pF, and differential analog input unless otherwise specified.) ANALOG INPUTS Max. Peak-to-Peak Diff. Voltage Input Range (VIN+ - VIN–) Max. Peak-to-Peak Single-Ended Voltage Input Range Analog Input Common Mode Voltage Range (VIN+ + VIN–)/2 ➀ Input Bias Current, IB+ or IB– ➁ Differential Input Current, (IB+ - IB–) Input Impedance ➁ Input Capacitance INTERNAL VOLTAGE REFERENCE Reference Output Voltage, VROUT Reference Output Current Reference Temperature Coefficient ADS-235 ➂ ADS-236 ADS-237 REFERENCE VOLTAGE INPUT Reference Voltage Input, VRIN Total Reference Resistance, RL Reference Current PERFORMANCE Resolution Maximum Sample Rate, FCLK ADS-235 ADS-236 ADS-237 Minimum Sample Rate Integral Nonlinearity, F IN=DC ADS-235 ADS-236, ADS-237 Differential Nonlinearity, FIN=DC ➃ Input Offset Error, FIN=DC ADS-235 ADS-236, ADS-237 Full Scale Error, FIN=DC ADS-235 ADS-236, ADS-237 Aperture Delay, tAP Aperture Uncertainty, tAJ Full Power Input Bandwidth Spurious Free Dynamic Range, SFDR, FIN=1MHz ADS-235 ADS-236 ADS-237 Total Harmonic Distortion, THD, FIN=1MHz ADS-235 ADS-236 ADS-237 12 — 5 9 — — — — — — — — — — — — — — — — — — 5 — — 0.5 ±2.0 ±1.0 ±0.5 12 19 24 32 5 5 100 73 83 77 –70 –80 –75 — — — — — — ±2.0 ±1.0 — — — — — — — — — — — — — Bits MHz MHz MHz MHz LSB LSB LSB LSB LSB LSB LSB ns ps(RMS) MHz dB dB dB dB dB dB — — — 3.5 7.8 450 — — — Volts kW µA — — — — — 3.5 — — 200 50 — 1 — — — Volts mA ppm/°C ppm/°C ppm/°C MIN. — — 1.0 –10 — 1.0 — TYP. ±2.0 4.0 2.3 — ±0.5 — 10 MAX. — — 4.0 10 — — — UNITS Volts Volts Volts µA µA MW pF PERFORMANCE (cont.) Second Harmonic, F IN=1MHz ADS-235 ADS-236 ADS-237 Third Harmonic, FIN=1MHz ADS-235 ADS-236 ADS-237 Effective Number Of Bits, ENOB, FIN=1MHz ADS-235 ADS-236 ADS-237 Signal to Noise Ratio and Distortion, SINAD, FIN=1MHz ADS-235 ADS-236 ADS-237 Signal to Noise Ratio, SNR, FIN=1MHz ADS-235 ADS-236 ADS-237 Intermodulation Distortion, IMD, F1=1MHz F2=1.02MHz ADS-235 ADS-236 ADS-237 Transient Response ➄ Over-Voltage Recovery, 0.2V Overdrive TIMING CHARACTERISTICS Data Output Hold, tH Data Output Delay, tOD Clock Pulse Width, TPWO, TPW1 ADS-235, ADS-236 ADS-237 Data Latency, tLAT DC BIAS VOLTAGE OUTPUT DC Bias Voltage Output,VDC DC Bias Voltage Current DIGITAL OUTPUTS Logic Levels Logic "1", +DVS2=5V, Logic "0", +DVS2=5V, Logic "1", +DVS2=3V, Logic "0", +DVS2=3V, Output Capacitance VOH=2.4V VOL=0.4V VOH=2.4V VOL=0.4V –0.2 1.6 — — — — — –0.2 1.6 5 — — — — — mA mA mA mA pF — — 2.3 — — 1.0 volts mA — — 90 106 — 8 8 100 111 — — — 110 116 3 ns ns ns ns Cycles MIN. — — — — — — — — — — — — — — — — — — — — TYP. –73 –86 –80 –73 –83 –77 10.3 11 10.8 64 68 66.5 65 68 67.3 –66 –68 –65 1 2 MAX. — — — — — — — — — — — — — — — — — — — — UNITS dB dB dB dB dB dB Bits Bits Bits dB dB dB dB dB dB dB dB dB Cycle Cycle
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ADS-235, ADS-236, ADS-237
POWER REQUIREMENTS Power Supply Ranges +5V Analog Supply, +AVS +5V Digital Supply, +DVS1 +3V Digital Supply, +DVS2 +5V Digital Supply, +DVS2 Power Supply Currents ADS-235, ADS-236 +AIS +DIS1 +DIS2 ADS-237 +AIS +DIS1 +DIS2 Power Dissipation ADS-235 ADS-236 ADS-237 Offset Error Sensitivity, 5V±5% ADS-235 ADS-236, ADS-237 Gain Error Sensitivity, 5V±5% ADS-235 ADS-236, ADS-237 MIN. +4.75 +4.75 +2.7 +4.75 — — — — — — — — — — — — — TYP. 5 5 3 5 46 13 1 46 17 2 300 300 325 ±16 2 ±16 30 MAX. +5.25 +5.25 +3.3 +5.25 — — — — — — — 350 365 — — — — UNITS Volts Volts Volts Volts mA mA mA mA mA mA mW mW mW LSB LSB LSB LSB
applied to the sampling capacitors, CS. At the same time the hold capacitors, CH, are discharged to analog ground. At the falling edge of Ø1 the input signal is sampled on the bottom plates of the sampling capacitors. In the next clock phase, Ø2, the two bottom plates of the sampling capacitors are connected together and the holding capacitors are switched to the op-amp output nodes. The charge then redistributes between CS and CH completing one sample and hold cycle. The sample and hold output is a fully differential representation of the sampled analog input. The circuit not only performs the sample-hold function but will also convert a single-ended input to a fully differential output. During the sampling phase, the VIN pins see only the on resistance of a switch and CS. The small values of these components result in a typical full power input bandwidth of 100MHz for the converters. As illustrated in the Functional Block Diagram, figure 1, and the Internal Timing Diagram, figure 2A, three identical pipeline sub-converter stages, each containing a four-bit flash converter and a four-bit multiplying digital-to-analog converter, follow the S/H with the fourth stage being a four-bit flash converter. Each converter stage in the pipeline will be sampling in one clock phase and amplifying in the other clock phase. Each subconverter clock signal is offset by 180 degrees from the previous stage clock signal resulting in alternate stages in the pipeline performing the same operation. The four-bit output of each of the sub-converter stages is used by the error correction logic. The output of each stage is input to a digital delay line which is controlled by the internal sampling clock. The function of the delay line is to align the digital outputs in time of the three identical stages with the output of the fourth stage flash converter before applying the sixteen bit result to the error correction logic. The error correction logic uses the supplementary bits to correct any error that may exist before generating the final twelve-bit digital data output. Due to the pipeline nature of this converter, the digital data representing an analog input sample is output to the digital
Footnotes: ➀ Differential Mode ➁ CLK off and Low ➂ Not specified ➃ No missing codes ➄ For FS step to settle to 12-bits accuracy
FUNCTIONAL DESCRIPTION
The ADS-235, ADS-236 and ADS-237 are 12-bit fully differential pipeline sampling A/D converters with digital error correction. Referring to the Functional Block Diagram shown in figure 1, figure 3.1 shows the circuit for the front end differential in and out sample-and-hold (S/H). The switches are controlled by an internal sampling clock which is a non-overlapping two phase signal, Ø1 and Ø2, derived from the master sampling clock. During the sampling phase, Ø1, the input signal is
Analog Input, VIN
A/D CLK SN–1 HN–1 SN HN SN+1 HN+1 SN+2 HN+2 SN+3 HN+3 SN+4 HN+4 SN+5 HN+5 SN+6 HN+6
1ST Stage
B1, N–1
B1, N
B1, N+1
B1, N+2
B1, N+3
B1, N+4
B1, N+5
2ND Stage
B2, N–2
B2, N–1
B2, N
B2, N+1
B2, N+2
B2, N+3
B2, N+4
B2, N+5
3RD Stage
B3, N–2
B3, N–1
B3, N
B3, N+1
B3, N+2
B3, N+3
B3, N+4
4TH Stage
B4, N–2
B4, N–1
B4, N
B4, N+1
B4, N+2
B4, N+3
B4, N+4
Data Output
DN–3
DN–2 tLAT
DN–1
DN
DN+1
DN+2
DN+3
Notes: 1. SN: N-th sampling period. 2. HN: N-th holding period. 3. BM, N: M-th stage digital output corresponding to N-th sampled input. 4. DN: Final data output corresponding to N-th sampled input.
Figure 2A. Internal Timing Diagram
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data bus on the third cycle of the clock after the analog sample is taken. After this latency delay, the digital data representing each successive sample of the analog input is output during the following clock cycle. The digital output data is synchronized to the external sampling clock through a double buffered latching circuit. The output of the digital error correction circuit is available in offset binary format. sufficient but the actual value must take into account the highest frequency component of the input signal.
Single-Ended Analog Input
The circuit in figure 3.4 may be used with a single-ended AC coupled input. Assuming again that the difference between the two internal voltage references is 2V and VIN is a 4Vp-p sinewave, then VIN+ is a 4Vp-p sinewave riding on a positive voltage equal to VDC. The converter will be at a positive full scale when VIN+ is at VDC+2V (VIN+ - VIN– = 2V) and will be equal to a negative full scale when VIN+ is equal toVDC-2V (VIN+ - VIN– = –2V). In this case, VDC could range between 2V and 3V without significant change in the converters performance. The simplest way to obtain a VDC voltage is to use the VDC output provided by the converters. The single-ended analog input can be DC coupled, as shown figure 3.5, as long as the input is within the analog input common mode voltage range. The resistor, R, shown is not absolutely necessary but may be used as a load setting resistor. A capacitor, C, connected between VIN+ and VIN– will help filter high frequency noise. A value of approximately 20pF is normally sufficient but the actual value must take into account the highest frequency component of the input signal.
Differential Analog Input
The analog input is a differential input that can be configured in various ways depending on the signal source and the level of performance desired. A fully differential connection as shown in figures 3.2 and 3.3 will give the best performance. The ADS-235, ADS-236 and ADS-237 are powered by a single +5V analog power supply which limits the analog input to between ground and +5V. For the differential input connection this implies that the analog input common mode voltage can range from 1.0V to 4.0V, see figure 3.6. Performance for the converter does not change significantly with the value of the analog input common mode voltage. A DC voltage source, VDC, equal to 2.3V, typical, is provided to help simplify circuit design when using an AC coupled differential input. This low impedance voltage source is not designed to be a reference voltage but makes an excellent DC bias source. This bias voltage source stays well within the analog input common mode voltage range over temperature. The difference between the converter's two internal reference voltages is 2V. For the AC coupled differential input, figure 3.2, if VIN is a 2Vp-p sinewave with –VIN 180 degrees out of phase with VIN, then VIN+ is a 2Vp-p sinewave riding on a DC bias voltage equal to VDC. Consequently, the converter will be at a positive full scale when the VIN+ input is at VDC+1V and the VIN– input is at VDC-1V (VIN+ - VIN– = 2V). Conversely, the ADS will be at negative full scale when the VIN+ input is equal to VDC-1V and VIN– is at VDC+1V (VIN+ - VIN– = –2V). Thus, the converter has a peak-to-peak differential analog input voltage range of ±2V. The analog input can be DC coupled, figure 3.3, as long as the inputs are within the analog input common mode voltage range (1.0V £ VDC £ 4.0V). The resistors, R, are not absolutely necessary but may be used as load setting resistors. A capacitor, C, connected from VIN+ to VIN– will help filter high frequency noise. Values of approximately 20pF are normally
INTERNAL REFERENCE GENERATOR, VROUT VRIN
The ADS-235/236/237 have an internal reference generator, therefore, an external voltage is not required. VROUT must be connected to VRIN when using the internal reference voltage. Two reference voltages are generated internally, 1.3V and 3.3V, for a fully differential input range of ±2V. An external reference may be used by connecting the external voltage reference to the VRIN pin with VROUT left open. These units are tested with VRIN equal to 3.5V. In order to minimize overall converter noise it is recommended that adequate high frequency decoupling be provided at the VRIN pin.
Digital I/O and Clock
The ADS-235, ADS-236 and ADS-237 provide a standard high-speed interface to external TTL/CMOS logic families. In order to ensure rated performance the duty cycle of the clock should be held at 50% ±5%, have low jitter and operate at standard TTL levels. Performance is guaranteed for conversion
Analog Input, VIN tAP tAJ TPWO A/D CLK 1.5V
5 n sec typ. 5 p sec typ. TPW1 1.5V tOD tH 8 n sec typ. 8 n sec typ. 2.0V 0.5V N
Data Output
N–1
Figure 2B. Input-to-Output Timing
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rates above 0.5MHz in order to ensure proper performance of the internal dynamic circuits. supplies and grounds. For best performance the supplies used should be clean, linear regulated supplies. All power supplies should be bypassed to ground with a 10uF tantalum capacitor in parallel with a 0.1uF ceramic capacitor. Locate the bypass capacitors as close to the converter as possible. If the converter is to be powered from one supply then the analog supply and ground pins should be isolated with ferrite beads from the digital supply and ground pins. See the Typical Connection Diagram, Figure 4. In order to minimize overall converter noise it is recommended that the VRIN pin be bypassed using a 4.7 uF tantalum capacitor in parallel with a 0.01 uF ceramic capacitor. Locate the bypass capacitors as close to the unit as possible.
Power Supplies and Grounding
The ADS-235, ADS-236 and ADS-237 have separate digital and analog power supply pins and grounds (refer to the Input/ Output Connections table for pin numbers) to reduce digital noise in the analog signal path. The digital data outputs also have a separate supply pin, +DVS2, which can be powered from either a 3.0V or 5.0V supply to allow the user the option of interfacing with 3.0V logic. The converters should be mounted on a board that provides separate low impedance paths for the analog and digital
Figure 3.1 Analog Input Sample-and-Hold
Ø1 VIN+ Ø1 Ø2 Ø1 VIN– CS Ø1 CH +– VOUT– CS –+ VOUT+ Ø1
Figure 3.2 AC Coupled Differential Input
VIN 8 R 10 VDC R –VIN VIN+
CH
Ø1
9
VIN–
Figure 3.3 DC Coupled Differential Input
VIN VDC R 8 VIN+
Figure 3.4 AC Coupled Single Ended Input
8 VIN R VIN+
10 C R –VIN VDC 9
VDC
10 VDC VDC VIN–
VIN–
9
Figure 3.5 DC Coupled Single Ended Input
VIN VDC R 10 VDC C 8 VIN+
Figure 3.6 Differential Analog Input Common Mode Voltage Range
+5V VIN+ VDC=+4.0V
2.0Vp-p
VIN–
Common Mode Voltage Range
VIN+ +1.0
