ADS-933

® ® ADS-933 16-Bit, 3MHz Sampling A/D Converters INNOVATION and EXCELLENCE PRELIMINARY PRODUCT DATA FEATURES • • • • • • • • • 16-bit resolution 3MHz sampling rate Functionally complete No missing codes over full military temperature range Edge-triggered ±5V supplies, 1.85 Watts Small, 40-pin, ceramic TDIP 85dB SNR, –84dB THD Ideal for both time and frequency-domain applications PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 INPUT/OUTPUT CONNECTIONS FUNCTION +3.2V REF. OUT UNIPOLAR ANALOG INPUT ANALOG GROUND OFFSET ADJUST GAIN ADJUST DIGITAL GROUND FIFO/DIR FIFO READ FSTAT1 FSTAT2 START CONVERT BIT 16 (LSB) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 PIN 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 FUNCTION NO CONNECTION NO CONNECTION +5V ANALOG SUPPLY –5V SUPPLY ANALOG GROUND COMP. BITS OUTPUT ENABLE OVERFLOW EOC +5V DIGITAL SUPPLY DIGITAL GROUND BIT 1 (MSB) BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 GENERAL DESCRIPTION The low-cost ADS-933 is a 16-bit, 3MHz sampling A/D converter. This device accurately samples full-scale input signals up to Nyquist frequencies with no missing codes. The dynamic performance of the ADS-933 has been optimized to achieve a signal-to-noise ratio (SNR) of 85dB and a total harmonic distortion (THD) of –84dB. Packaged in a 40-pin TDIP, the functionally complete ADS-933 contains a fast-settling sample-hold amplifier, a subranging (two-pass) A/D converter, an internal reference, timing/control logic, and error-correction circuitry. Digital input and output levels are TTL. The ADS-933 only requires the rising edge of the start convert pulse to operate. Requiring only ±5V supplies, the ADS-933 dissipates 1.85 Watts. The device is offered with a bipolar (±2.75V) analog input range and a unipolar 0 to –5.5V input range. Models are available for use in either commercial (0 to +70°C) or military (– 55 to +125°C) operating temperature ranges. A proprietary, autocalibrating, error-correcting circuit enables the device to achieve specified performance over the full military temperature range. Typical applications include medical imaging, radar, sonar, communications and instrumentation. 10 FSTAT1 11 FSTAT2 GAIN ADJUST 6 GAIN ADJUST CKT. 8 FIFO/DIR 9 FIFO/READ 29 BIT 1 (MSB) 28 BIT 1 (MSB) +3.2V REF. OUT 1 POWER AND GROUNDING +5V ANALOG SUPPLY +5V DIGITAL SUPPLY –5V SUPPLY ANALOG GROUND DIGITAL GROUND NO CONNECTION 38 31 37 4, 36 7, 30 39, 40 UNIPOLAR 2 OFFSET ADJUST 5 OFFSET ADJUST CKT. 2-PASS ANALOG-TO-DIGITAL CONVERTER PRECISION +3.2V REFERENCE 27 BIT 2 26 BIT 3 25 BIT 4 CUSTOM GATE ARRAY 3-STATE OUTPUT REGISTER 24 BIT 5 23 BIT 6 22 BIT 7 21 BIT 8 20 BIT 9 19 BIT 10 18 BIT 11 17 BIT 12 16 BIT 13 15 BIT 14 14 BIT 15 OFFSET ADJUST 5 13 BIT 16 (LSB) 34 OUTPUT ENABLE 33 OVERFLOW ANALOG INPUT 3 S/H START CONVERT 12 EOC 32 COMP. BITS 35 TIMING AND CONTROL LOGIC Figure 1. ADS-933 Functional Block Diagram DATEL, Inc., Mansfield, MA 02048 (USA) • Tel: (508)339-3000, (800)233-2765 Fax: (508) 339-6356 • E-mail: sales@datel.com • Internet: www.datel.com ® ® ADS-933 ABSOLUTE MAXIMUM RATINGS PARAMETERS LIMITS UNITS Volts Volts Volts Volts °C +5V Supply (Pins 31, 38) 0 to +6 –5V Supply (Pin 37) 0 to –6 Digital Inputs (Pins 8, 9, 12, 34, 35) –0.3 to +VDD +0.3 Analog Input (Pin 3) ±5 Lead Temperature (10 seconds) +300 PHYSICAL/ENVIRONMENTAL PARAMETERS Operating Temp. Range, Case ADS-933MC ADS-933MM Thermal Impedance θ jc θ ca Storage Temperature Range Package Type Weight MIN. 0 –55 — — –65 TYP. — — 4 18 — MAX. +70 +125 — — +150 UNITS °C °C °C/Watt °C/Watt °C FUNCTIONAL SPECIFICATIONS +25°C ANALOG INPUT Input Voltage Range Unipolar Bipolar Input Resistance Pin 3 Input ResistancePin 2 Input Capacitance DIGITAL INPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0"  Start Convert Positive Pulse Width Ž STATIC PERFORMANCE Resolution Integral Nonlinearity (fin = 10kHz) Differential Nonlinearity (fin = 10kHz) Full Scale Absolute Accuracy Bipolar Zero Error (Tech Note 2) (Unipolar offset spec same as Bipolar zero) Bipolar Offset Error (Tech Note 2) Gain Error (Tech Note 2) No Missing Codes (fin = 10kHz) DYNAMIC PERFORMANCE Peak Harmonics (–0.5dB) dc to 500kHz 500kHz to 1MHz Total Harmonic Distortion (–0.5dB) dc to 500kHz 500kHz to 1MHz Signal-to-Noise Ratio (w/o distortion, –0.5dB) dc to 500kHz 500kHz to 1MHz Signal-to-Noise Ratio  (& distortion, –0.5dB) dc to 500kHz 500kHz to 1MHz Noise Two-Tone Intermodulation Distortion (fin = 200kHz, 240kHz, fs = 3MHz, –0.5dB) Input Bandwidth (–3dB) Small Signal (–20dB input) Large Signal (–0.5dB input) Feedthrough Rejection (fin = 1MHz) Slew Rate Aperture Delay Time Aperture Uncertainty S/H Acquisition Time ( to ±0.001%FSR, 5.5V step) — — — — 81 81 78 78 — — — — — — — — — — –84 –84 –83 85 85 82 81 80 –87 9.8 10.2 90 ±120 +8 3 180 81 80 80 80 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — –0.95 — — — — 16 16 ±1 ±0.5 ±0.15 ±0.1 ±0.1 ±0.15 — — — +1.0 ±0.3 ±0.2 ±0.2 ±0.3 — +2.0 — — — 20 — — — — 50 — +0.8 +20 –20 — MIN. — — 655 418 — TYP. 0 to –5.5 ±2.75 687 426 10 MAX. — — — — 15 40-pin, metal-sealed, ceramic TDIP 0.56 ounces (16 grams) (TA = +25°C, ±VCC = ±5V, +VDD = +5V, 3MHz sampling rate, and a minimum 3 minute warm-up Œ unless otherwise specified.) 0 to +70°C MIN. — — 655 418 — TYP. 0 to –5.5 ±2.75 687 426 10 MAX. — — — — 15 –55 to +125°C MIN. — — 655 418 — TYP. 0 to –5.5 ±2.75 687 426 10 MAX. — — — — 15 UNITS Volts Volts Ω Ω pF +2.0 — — — 20 — — — — 50 — +0.8 +20 –20 — +2.0 — — — 20 — — — — 50 — +0.8 +20 –20 — Volts Volts µA µA ns — — –0.95 — — — — 16 16 ±1.5 ±0.5 ±0.3 ±0.2 ±0.2 ±0.3 — — — +1.0 ±0.5 ±0.4 ±0.4 ±0.5 — — — –0.95 — — — — 16 16 ±2 ±0.5 ±0.5 ±0.4 ±0.4 ±0.5 — — — +1.5 ±0.8 ±0.6 ±0.6 ±0.8 — Bits LSB LSB %FSR %FSR %FSR % Bits –86 –84 –84 –83 85 85 82 81 80 –87 9.8 10.2 90 ±120 +8 3 180 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — –86 –84 –84 –83 85 85 82 81 80 –87 9.8 10.2 90 ±120 +8 3 180 — — — — — — — — — — — — — — — — — dB dB dB dB dB dB dB dB µVrms dB MHz MHz dB V/µs ns psrms ns 2 ® ® ADS-933 DYNAMIC PERFORMANCE (Cont.) ANALOG OUTPUT Overvoltage Recovery Time  A/D Conversion Rate Internal Reference Voltage Drift External Current DIGITAL OUTPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Output Coding POWER REQUIREMENTS Power Supply Ranges } +5V Supply –5V Supply Power Supply Currents +5V Supply –5V Supply Power Dissipation Power Supply Rejection MIN. +25°C TYP. MAX. MIN. 0 TO +70°C TYP. MAX. –55 TO +125°C MIN. TYP. MAX. UNITS — 3 3.15 — — — — +3.2 ±30 5 333 — — — — — 3 — — — — — +3.2 ±30 5 333 — — — — — 3 — — — — — +3.2 ±30 5 333 — — — — ns MHz Volts ppm/°C mA +2.4 — — — — — +2.4 — — +2.4 — — — +0.4 — — +0.4 — — +0.4 — –4 — — –4 — — –4 — +4 — — +4 — — +4 Offset Binary / Complementary Offset Binary / Two's Complement / Complementary Two's Complement Volts Volts mA mA +4.75 –4.75 — –140 — — +5.0 –5.0 +220 –150 1.85 — +5.25 –5.25 260 — 2.0 ±0.07 +4.75 –4.75 — –140 — — +5.0 –5.0 +220 –150 1.85 — +5.25 –5.25 260 — 2.0 ±0.07 +4.9 –4.9 — –140 — — +5.0 –5.0 +220 –150 1.85 — +5.25 –5.25 260 — 2.0 ±0.07 Volts Volts mA mA Watts %FSR/%V Footnotes: Œ All power supplies must be on before applying a start convert pulse. All supplies and the clock (START CONVERT) must be present during warm-up periods. The device must be continuously converting during this time.  When COMP. BITS (pin 35) is low, logic loading "0" will be –350µA. Ž A 3MHz clock with a 50nsec positive pulse width is used for all production testing. See Timing Diagram for more details.  Effective bits is equal to: (SNR + Distortion) – 1.76 + 20 log 6.02 Full Scale Amplitude Actual Input Amplitude  This is the time required before the A/D output data is valid once the analog input is back within the specified range. ‘ The minimum supply voltages of +4.9V and –4.9V for ±VDD are required for –55°C operation only. The minimum limits are +4.75V and –4.75V when operating at +125°C. TECHNICAL NOTES 1. Obtaining fully specified performance from the ADS-933 requires careful attention to pc-card layout and power supply decoupling. The device's analog and digital ground systems are connected to each other internally. For optimal performance, tie all ground pins (2, 4, 7, 30 and 36) directly to a large analog ground plane beneath the package. Bypass all power supplies and the +3.2V reference output to ground with 4.7µF tantalum capacitors in parallel with 0.1µF ceramic capacitors. Locate the bypass capacitors as close to the unit as possible. 2. The ADS-933 achieves its specified accuracies without the need for external calibration. If required, the device's small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in Figure 2. When using this circuitry, or any similar offset and gain calibration hardware, make adjustments following warm-up. To avoid interaction, always adjust offset before gain. Tie pins 5 and 6 to ANALOG GROUND (pin 4) if not using offset and gain adjust circuits. 3. Pin 35 (COMP. BITS) is used to select the digital output coding format of the ADS-933. See Tables 2a and 2b. When this pin has a TTL logic "0" applied, it complements all of the ADS-933’s digital outputs. When pin 35 has a logic "1" applied, the output coding is complementary offset binary. Applying a logic "0" to pin 35 changes the coding to offset binary. Using the MSB output (pin 29) instead of the MSB output (pin 28) changes the respective output codings to complementary two's complement and two's complement. Pin 35 is TTL compatible and can be directly driven with digital logic in applications requiring dynamic control over its function. There is an internal pull-up resistor on pin 35 allowing it to be either connected to +5V or left open when a logic "1" is required. 4. To enable the three-state outputs, connect OUTPUT ENABLE (pin 34) to a logic "0" (low). To disable, connect pin 34 to a logic "1" (high). 3 ® ® ADS-933 5. Applying a start convert pulse while a conversion is in progress (EOC = logic "1") will initiate a new and probably inaccurate conversion cycle. Data from both the interrupted and subsequent conversions will be invalid. 6. Do not enable/disable or complement the output bits or read from the FIFO during the conversion process (from the rising edge of EOC to the falling edge of EOC). 7. The OVERFLOW bit (pin 33) switches from 0 to 1 when the input voltage exceeds that which produces an output of all 1’s or when the input equals or exceeds the voltage that produces all 0’s. When COMP BITS is activated, the above conditions are reversed. FIFO immediately after the first conversion has been completed and remains there until the FIFO is read. If the output three-state register has been enabled (logic "0" applied to pin 34), data from the first conversion will appear at the output of the ADS-933. Attempting to write a 17th word to a full FIFO will result in that data, and any subsequent conversion data, being lost. Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both equal to "1"), it can be read by dropping the FIFO READ line (pin 9) to a logic "0" and then applying a series of 15 rising edges to the read line. Since the first data word is already present at the FIFO output, the first read command (the first rising edge applied to FIFO READ) will bring data from the second conversion to the output. Each subsequent read command/rising edge brings the next word to the output lines. After the 15th rising edge brings the 16th data word to the FIFO output, the subsequent falling edge on READ will update the status outputs (after a 20ns maximum delay) to FSTAT1 = 0, FSTAT2 = 1 indicating that the FIFO is empty. If a read command is issued after the FIFO empties, the last word (the 16th conversion) will remain present at the outputs. INTERNAL FIFO OPERATION The ADS-933 contains an internal, user-initiated, 18-bit, 16word FIFO memory. Each word in the FIFO contains the 16 data bits as well as the MSB and overflow bits. Pins 8 (FIFO/ DIR) and 9 (FIFO READ) control the FIFO's operation. The FIFO's status can be monitored by reading pins 10 (FSTAT1) and 11 (FSTAT2). When pin 8 (FIFO/DIR) has a logic "1" applied, the FIFO is inserted into the digital data path. When pin 8 has a logic "0" applied, the FIFO is transparent and the output data goes directly to the output three-state register (whose operation is controlled by pin 34 (ENABLE)). Read and write commands to the FIFO are ignored when the ADS-933 is operated in the "direct" mode. It takes a maximum of 20ns to switch the FIFO in or out of the ADS-933’s digital data path. FIFO Reset Feature At any time, the FIFO can be reset to an empty state by putting the ADS-933 into its "direct" mode (logic "0" applied to pin 8, FIFO/DIR) and also applying a logic "0" to the FIFO READ line (pin 9). The empty status of the FIFO will be indicated by FSTAT1 going to a "0" and FSTAT2 going to a "1". The status outputs change 40ns after applying the control signals. FIFO Write and Read Modes Once the FIFO has been enabled (pin 8 high), digital data is automatically written to it, regardless of the status of FIFO READ (pin 9). Assuming the FIFO is initially empty, it will accept data (18-bit words) from the next 16 consecutive A/D conversions. As a precaution, pin 9 (which controls the FIFO's READ function) should not be low when data is first written to an empty FIFO. When the FIFO is initially empty, digital data from the first conversion (the "oldest" data) appears at the output of the FIFO Status, FSTAT1 and FSTAT2 Monitor the status of the data in the FIFO by reading the two status pins, FSTAT1 (pin 10) and FSTAT2 (pin 11). CONTENTS Empty (0 words)