ADS-935

16-Bit, 5MHz Sampling A/D Converters FEATURES INPUT/OUTPUT CONNECTIONS PIN FUNCTION PIN FUNCTION GENERAL DESCRIPTION POWER AND GROUNDING +5V ANALOG SUPPLY +5V DIGITAL SUPPLY –5V SUPPLY ANALOG GROUND DIGITAL GROUND –12/–15V ANALOG SUPPLY +12/+15V ANALOG SUPPLY 38 31 37 4, 36 7, 30 39 40 UNIPOLAR 2 Figure 1. ADS-935 Functional Block Diagram www.cd4power.com Page 1 of 8 ABSOLUTE MAXIMUM RATINGS PARAMETERS +5V Supply (Pins 31, 38) –5V Supply (Pin 37) +12V/+15V Supply (pin 40) –12V/–15V Supply (pin 39) Digital Inputs (Pins 8, 9, 12, 34, 35) Analog Input (Pin 3) Lead Temperature (10 seconds) LIMITS 0 to +6 0 to –6 0 to +16V 0 to +16V –0.3 to +VDD +0.3 ±5 +300 UNITS Volts Volts Volts Volts Volts Volts °C PHYSICAL/ENVIRONMENTAL PARAMETERS Operating Temp. Range, Case ADS-935MC ADS-935MM Thermal Impedance jc ca Storage Temperature Range Package Type Weight MIN. 0 –55 — — –65 TYP . — — MAX. +70 +125 UNITS °C °C 4 — °C/Watt 18 — °C/Watt — +150 °C 40-pin, metal-sealed, ceramic TDIP 0.56 ounces (16 grams) FUNCTIONAL SPECIFICATIONS (TA = +25°C, ±VCC = ±12/15V, +VDD = ±5V, 5MHz sampling rate, and a minimum 3 minute warm-up +25°C ANALOG INPUT Input Voltage Range Unipolar Bipolar Input Resistance (Pin 3) (Pin 2) Input Capacitance DIGITAL INPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Start Convert Positive Pulse Width STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity (fin = 10kHz) Full Scale Absolute Accuracy Bipolar Zero Error (Tech Note 2) Bipolar Offset Error (Tech Note 2) Gain Error (Tech Note 2) No Missing Codes (fin = 10kHz) DYNAMIC PERFORMANCE Peak Harmonics (–0.5dB) dc to 500kHz 500kHz to 2.45MHz Total Harmonic Distortion (–0.5dB) dc to 500kHz 500kHz to 2.45MHz Signal-to-Noise Ratio (w/o distortion, –0.5dB) dc to 500kHz 500kHz to 2.45MHz Signal-to-Noise Ratio (& distortion, –0.5dB) dc to 500kHz 500kHz to 2.45MHz Noise Two-Tone Intermodulation Distortion (fin = 200kHz, 240kHz, fs = 5MHz, –0.5dB) Input Bandwidth (–3dB) Small Signal (–20dB input) Large Signal (–0.5dB input) Feedthrough Rejection (fin = 1MHz) Slew Rate Aperture Delay Time Aperture Uncertainty S/H Acquisition Time ( to ±0.001%FSR, 5.5V step) Overvoltage Recovery Time A/D Conversion Rate — — — — 84 83 80 79 — — — — — — — — — — 5 –87 –82 –86 –81 86 85 82 81 80 –87 25 15 90 ±400 4 2 80 200 — –82 –80 –81 –80 — — — — — –85 — — — — — — — — — — — — — 84 83 80 79 — — — — — — — — — — 5 –87 –82 –86 –81 86 85 82 81 80 –87 25 25 90 ±400 4 2 80 200 — –82 –80 –81 –80 — — — — — –85 — — — — — — — — — — — — — 77 77 76 76 — — — — — — — — — — 5 –82 –78 –81 –77 80 80 78 75 80 –87 25 15 90 ±400 4 2 90 200 — –78 –78 –76 –76 — — — — — –82 — — — — — — — — — dB dB dB dB dB dB dB dB μVrms dB MHz MHz dB V/μs ns ps rms ns ns MHz Page 2 of 8 — — –0.95 — — — — 16 16 ±1 ±0.5 ±0.15 ±0.1 ±0.1 ±0.15 — — — +1.0 ±0.3 ±0.2 ±0.2 ±0.3 — — — –0.95 — — — — 16 16 ±1.5 ±0.5 ±0.3 ±0.2 ±0.2 ±0.3 — — — +1.0 ±0.5 ±0.4 ±0.4 ±0.5 — — — –0.95 — — — — 16 16 ±2 ±0.5 ±0.5 ±0.4 ±0.4 ±0.5 — — — +1.5 ±0.8 ±0.6 ±0.6 ±0.8 — Bits LSB LSB %FSR %FSR %FSR % Bits +2.0 — — — 20 — — — — 50 — +0.8 +20 –20 — +2.0 — — — 20 — — — — 50 — +0.8 +20 –20 — +2.0 — — — 20 — — — — 50 — +0.8 +20 –20 — Volts Volts μA μA ns MIN. — — — — — TYP . 0 to –5.5V ±2.75 400 480 10 MAX. — — — — 15 MIN. — — — — — unless otherwise specified.) –55 to +125°C MAX. — — — — 15 MIN. — — — — — TYP . 0 to –5.5V ±2.75 400 480 10 MAX. — — — — 15 UNITS Volts Volts pF TYP . 0 to –5.5V ±2.75 400 480 10 0 to +70°C www.cd4power.com DYNAMIC PERFORMANCE (Cont.) ANALOG OUTPUT Internal Reference Voltage Drift External Current DIGITAL OUTPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Output Coding POWER REQUIREMENTS Power Supply Ranges +5V Supply –5V Supply +12V Supply –12V Supply +15V Supply –15V Supply Power Supply Currents +5V Supply –5V Supply –12/15V Supply +12/15V Supply Power Dissipation Power Supply Rejection MIN. +25°C TYP . MAX. MIN. 0 TO +70°C TYP . MAX. –55 TO +125°C MIN. TYP . MAX. UNITS — — — +3.2 ±30 5 — — — — — — +3.2 ±30 5 — — — — — — +3.2 ±30 5 — — — Volts ppm/°C mA +2.4 — — +2.4 — — +2.4 — — — — +0.4 — — +0.4 — — +0.4 — — –4 — — –4 — — –4 — — +4 — — +4 — — +4 (Offset) Binary / Complementary (Offset) Binary / Two's Complement / Complementary Two's Complement Volts Volts mA mA +4.75 –4.75 +11.5 –11.5 +14.5 –14.5 — — — — — — +5.0 –5.0 +12.0 –12.0 +15.0 –15.0 +200 –100 –65 +85 2.85 — +5.25 –5.25 +12.5 –12.5 +15.5 –15.5 — — — — 3.1 ±0.07 +4.75 –4.75 +11.5 –11.5 +14.5 –14.5 — — — — — — +5.0 –5.0 +12.0 –12.0 +15.0 –15.0 +220 –150 –65 +85 2.85 — +5.25 –5.25 +12.5 –12.5 +15.5 –15.5 — — — — 3.5 ±0.07 +4.9 –4.9 +11.5 –11.5 +14.5 –14.5 — — — — — — +5.0 –5.0 +12.0 –12.0 +15.0 –15.0 +220 –150 — — 2.85 — +5.25 –5.25 +12.5 –12.5 +15.5 –15.5 — — — — 3.5 ±0.07 Volts Volts Volts Volts Volts Volts mA mA mA mA Watts %FSR/%V Footnotes: All power supplies must be on before applying a start convert pulse. All supplies and the clock (START CONVERT) must be present during warm-up periods. The device must be continuously converting during this time. When COMP BITS (pin 35) is low, logic loading "0" will be –350μA. . A 5MHz clock with a 50nsec positive pulse width is used for all production testing. See Timing Diagram for more details. Effective bits is equal to: (SNR + Distortion) – 1.76 + 20 log 6.02 Full Scale Amplitude Actual Input Amplitude This is the time required before the A/D output data is valid once the analog input is back within the specified range. See table 2a, Setting Output Coding Selection. The minimum supply voltages of +4.9V and –4.9V for ±VDD are required for –55°C operation only. The minimum limits are +4.75V and –4.75V when operating at +125°C. ±12V only or ±15V only required. TECHNICAL NOTES 1. Obtaining fully specified performance from the ADS-935 requires careful attention to pc-card layout and power supply decoupling. The device's analog and digital ground systems are connected to each other internally. For optimal performance, tie all ground pins (4, 7, 30 and 36) directly to a large analog ground plane beneath the package. For the best performance it is recommended to use a single power source for both the +5V analog and +5V digital supplies. Bypass all power supplies and the +3.2V reference output to ground with 4.7μF tantalum capacitors in parallel with 0.1μF ceramic capacitors. Locate the bypass capacitors as close to the unit as possible. 2. The ADS-935 achieves its specified accuracies without the need for external calibration. If required, the device's small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in Figure 2. When using this circuitry, or any similar offset and gain calibration hardware, make adjustments following warm-up. To avoid interaction, always adjust offset before gain. Tie pins 5 and 6 to ANALOG GROUND (pin 4) if not using offset and gain adjust circuits. 3. Pin 35 (COMP BITS) is used to select the digital output . coding format of the ADS-935. See Tables 2a and 2b. When this pin has a TTL logic "0" applied, it complements all of the ADS-935’s digital outputs. When pin 35 has a logic "1" applied, the output coding is complementary (offset) binary. Applying a logic "0" to pin 35 changes the coding to (offset) binary. Using the MSB output (pin 29) instead of the MSB output (pin 28) changes the respective output codings to complementary two's complement and two's complement. Pin 35 is TTL compatible and can be directly driven with digital logic in applications requiring dynamic control over its function. There is an internal pull-up resistor on pin 35 allowing it to be either connected to +5V or left open when a logic "1" is required. 4. To enable the three-state outputs, connect OUTPUT ENABLE (pin 34) to a logic "0" (low). To disable, connect pin 34 to a logic "1" (high). www.cd4power.com Page 3 of 8 5. Applying a start convert pulse while a conversion is in progress (EOC = logic "1") will initiate a new and probably inaccurate conversion cycle. Data from both the interrupted and subsequent conversions will be invalid. 6. Do not enable/disable or complement the output bits or read from the FIFO during the conversion process (from the rising edge of EOC to the falling edge of EOC). 7. The OVERFLOW bit (pin 33) switches from 0 to 1 when the input voltage exceeds that which produces an output of all 1’s or when the input equals or exceeds the voltage that produces all 0’s. When COMP BITS is activated, the above conditions are reversed. the FIFO immediately after the first conversion has been completed and remains there until the FIFO is read. If the output three-state register has been enabled (logic "0" applied to pin 34), data from the first conversion will appear at the output of the ADS-935. Attempting to write a 17th word to a full FIFO will result in that data, and any subsequent conversion data, being lost. Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both equal to "1"), it can be read by dropping the FIFO READ line (pin 9) to a logic "0" and then applying a series of 15 rising edges to the read line. Since the first data word is already present at the FIFO output, the first read command (the first rising edge applied to FIFO READ) will bring data from the second conversion to the output. Each subsequent read command/rising edge brings the next word to the output lines. After the 15th rising edge brings the 16th data word to the FIFO output, the subsequent falling edge on READ will update the status outputs (after a 20ns maximum delay) to FSTAT1 = 0, FSTAT2 = 1 indicating that the FIFO is empty. If a read command is issued after the FIFO empties, the last word (the 16th conversion) will remain present at the outputs. INTERNAL FIFO OPERATION The ADS-935 contains an internal, user-initiated, 18-bit, 16word FIFO memory. Each word in the FIFO contains the 16 data bits as well as the MSB and overflow bits. Pins 8 (FIFO/ DIR) and 9 (FIFO READ) control the FIFO's operation. The FIFO's status can be monitored by reading pins 10 (FSTAT1) and 11 (FSTAT2). When pin 8 (FIFO/DIR) has a logic "1" applied, the FIFO is inserted into the digital data path. When pin 8 has a logic "0" applied, the FIFO is transparent and the output data goes directly to the output three-state register (whose operation is controlled by pin 34 (ENABLE)). Read and write commands to the FIFO are ignored when the ADS-935 is operated in the "direct" mode. It takes a maximum of 20ns to switch the FIFO in or out of the ADS-935’s digital data path. FIFO Reset Feature At any time, the FIFO can be reset to an empty state by putting the ADS-935 into its "direct" mode (logic "0" applied to pin 8, FIFO/DIR) and also applying a logic "0" to the FIFO READ line (pin 9). The empty status of the FIFO will be indicated by FSTAT1 going to a "0" and FSTAT2 going to a "1". The status outputs change 40ns after applying the control signals. FIFO Write and Read Modes Once the FIFO has been enabled (pin 8 high), digital data is automatically written to it, regardless of the status of FIFO READ (pin 9). Assuming the FIFO is initially empty, it will accept data (18-bit words) from the next 16 consecutive A/D conversions. As a precaution, pin 9 (which controls the FIFO's READ function) should not be low when data is first written to an empty FIFO. When the FIFO is initially empty, digital data from the first conversion (the "oldest" data) appears at the output of FIFO Status, FSTAT1 and FSTAT2 Monitor the status of the data in the FIFO by reading the two status pins, FSTAT1 (pin 10) and FSTAT2 (pin 11). CONTENTS Empty (0 words)