AMIS-30622
I2C Micro-Stepping Motor
Driver
INTRODUCTION
The AMIS−30622 is a single−chip micro−stepping motor driver
with a position controller and control/diagnostic interface. It is ready
to build intelligent peripheral systems where up to 32 drivers can be
connected to one I2C master. This significantly reduces system
complexity.
The chip receives positioning instructions through the bus and
subsequently drives the stator coils so the two−phase stepper motor
moves to the desired position. The on−chip position controller is
configurable (OTP or RAM) for different motor types, positioning
ranges and parameters for speed, acceleration and deceleration.
Micro−stepping allows silent motor operation and increased
positioning resolution. The advanced motion qualification mode
enables verification of the complete mechanical system in function of
the selected motion parameters. The AMIS−30622 can easily be
connected to an I2C bus where the I2C master can fetch specific status
information like actual position, error flags, etc. from each individual
slave node.
The chip is implemented in I2T100 technology, enabling both high
voltage analog circuitry and digital functionality on the same chip.
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SOIC−20
3 or 7 SUFFIX
CASE 751AQ
NQFP−32
8 SUFFIX
CASE 560AA
PRODUCT FEATURES
Motor Driver
•
•
•
•
•
•
Micro−Stepping Technology
Peak Current Up to 800 mA
Fixed Frequency PWM Current−Control
Automatic Selection of Fast and Slow Decay Mode
No external Fly−back Diodes Required
14 V/24 V Compliant
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Controller with RAM and OTP Memory
• Position Controller
• Configurable Speeds and Acceleration
• Input to Connect Optional Motion Switch
I2C Interface
• Bi−Directional 2−Wire Bus for Inter IC Control
• Field Programmable Node Addresses
• Full Diagnostics and Status Information
Protection
•
•
•
•
•
Overcurrent Protection
Undervoltage Management
Open−circuit Detection
High Temperature Warning and Management
Low Temperature Flag
© Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 5
EMI Compatibility
• High Voltage Outputs with Slope Control
• This is a Pb−Free Device
1
Publication Order Number:
AMIS−30622/D
AMIS−30622
APPLICATIONS
The AMIS−30622 is ideally suited for small positioning
applications. Target markets include: automotive (headlamp
alignment, HVAC, idle control, cruise control), industrial
equipment (lighting, fluid control, labeling, process control,
XYZ tables, robots) and building automation (HVAC,
surveillance, satellite dish, renewable energy systems).
Suitable applications typically have multiple axes or require
mechatronic solutions with the driver chip mounted directly
on the motor.
Table 1. ORDERING INFORMATION
Part No.
Peak Current
AMIS30622C6223G
800 mA
AMIS30622C6223RG
800 mA
AMIS30622C6227G
800 mA
AMIS30622C6227RG
800 mA
AMIS30622C6228G
800 mA
AMIS30622C6228RG
800 mA
Package*
Shipping†
SOIC−20
(Pb−Free)
38 Rail
SOIC−20
(Pb−Free)
1500 Tape & Reel
SOIC−20
(Pb−Free)
38 Rail
SOIC−20
(Pb−Free)
1500 Tape & Reel
NQFP−32 (7 x 7 mm)
(Pb−Free)
40 Rail
NQFP−32 (7 x 7 mm)
(Pb−Free)
2500 Tape & Reel
End Market/Version
Automotive
High Voltage Version
Industrial
High Voltage Version
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
QUICK REFERENCE DATA
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max
Unit
VBB, VHW, VSWI
Supply voltage, hardwired address and SWI pins
−0.3
+40 (Note 1)
V
TJ
Junction temperature range (Note 2)
−50
+175
°C
Tst
Storage temperature
−55
+160
°C
Vesd (Note 3)
Human Body Model (HBM) Electrostatic discharge voltage on pins
−2
+2
kV
−200
+200
V
Machine Model (MM) Electrostatic discharge voltage on pins
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. For limited time: VBB < 0.5 s, SWI and HW pins Data valid
Change of
data allowed
START
condition
Figure 23. Bit Transfer on the I2C−bus
STOP
condition
Figure 24. START and STOP Conditions
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AMIS−30622
Transferring Data
most significant bit (MSB) first (See Figure 25). If a slave
can’t receive or transmit another complete byte of data, it can
hold the clock line SCK LOW to force the master into a wait
state. Data transfer then continues when the slave is ready for
another byte of data and releases clock line SCK.
Byte Format
Every byte put on the SDA line must be 8−bits long. The
number of bytes that can be transmitted per transfer to
AMIS−30622 is restricted to eight. Each byte has to be
followed by an acknowledge bit. Data is transferred with the
START
STOP
SDA
MSB
Acknowledgement
signal from slave
SCK
1
7
2
8
Clock line held
low by slave
9
1
2
3−8
9
ACK
START
condition
STOP
condition
Aknowledge related
clock puse from master
Figure 25. Data Transfer on the I2C−bus
Acknowledge
If AMIS−30622 as slave−receiver does acknowledge the
slave address but later in the transfer cannot receive any
more data bytes, this is indicated by generating a
not−acknowledge on the first byte to follow. The master
generates than a STOP or a repeated START condition.
If a master−receiver is involved in the transfer, it must
signal the end of data to the slave−transmitter by not
generating an acknowledge on the last byte that was clocked
out of the slave. AMIS−30622 as slave−transmitter shall
release the data line to allow the master to generate STOP or
repeated START condition.
Data transfer with acknowledge is obligatory. The
acknowledge−related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the
acknowledge clock pulse. The receiver must pull down the
SDA line during the acknowledge clock pulse so that it
remains stable LOW during the HIGH period of this clock
pulse (see Figure 26). Of course, set−up and hold times must
also taken into account (see Table 6). When AMIS−30622
doesn’t acknowledge the slave address, the data line will be
left HIGH. The master can than generate either a STOP
condition to abort the transfer, or a repeated START
condition to start a new transfer.
START
Master releases the Data line
SDA by master
transmitter
MSB
Not acknowledged
SDA by slave
receiver
Acknowledged
SCK from
master
1
START
condition
8
2
Slave pulls data line
low if Acknowledged
9
Aknowledge related
clock puse from master
Figure 26. Acknowledge on the I2C−bus
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AMIS−30622
Clock Generation
address is 7−bit long followed by an eighth bit which is a data
direction bit (R/W) − a ‘zero’ indicates a transmission
(WRITE), a ‘one’ indicates a request for data (READ). A
data transfer is always terminated by a STOP condition (P)
generated by the master.
The master generates the clock on the SCK line to transfer
messages on the I2C−bus. Data is only valid during the
HIGH period of the clock.
Data Formats with 7−bit Addresses
Data transfers follow the format shown in Figure 27. After
the START condition (S), a slave address is sent. This
START
STOP
SDA
SCK
1−7
START
condition
ADDRESS
8
9
R/W
ACK
8
1−7
9
DATA
1−7
ACK
9
8
DATA
ACK
STOP
condition
Figure 27. A Complete Data Transfer
However, if a master still wishes to communicate on the
bus, it can generate a repeated START (Sr) and address
another slave without first generating a STOP condition.
Various combinations of read/write formats are then
possible within such a transfer.
♦
♦
♦
Data Transfer Formats
Writing Data to AMIS−30622
When writing to AMIS−30622, the master−transmitter
transmits to slave−receiver and the transfer direction is not
changed. A complete transmission consists of:
♦ Start condition
♦ The slave address (7−bit)
S
Slave Address
R/W
A
♦
Data
AMIS−30624 to Master
A
Data
A
P
N bytes + Acknowledge
”0” = WRITE
Master to AMIS−30624
Read/Write bit (‘0’ = write)
Acknowledge bit
Any further data bytes are followed by an
acknowledge bit. The acknowledge bit is used to
signal a correct reception of the data to the
transmitter. In this case the AMIS−30622 pulls the
SDA line to ‘0’. The AMIS−30622 reads the
incoming data at SDA on every rising edge of the
SCK signal
Stop condition to finish the transmission
S = Start condition
P = Stop condition
A = Acknowledge (SDA = LOW)
A = No Acknowledge (SDA = HIGH)
Figure 28. Master Writing Data to AMIS−30622
Some commands for the AMIS−30622 are supporting
eight bytes of data, other commands are transmitting two
bytes of data. See Table 25.
1. The first transmission consists of two bytes of
data:
♦ The first byte contains the slave address and the
write bit.
♦ The second byte contains the address of an
internal register in the
AMIS−30622. This internal
register address is stored in the circuit RAM.
Reading Data to AMIS−30622
When reading data from AMIS−30622 two transmissions
are needed:
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AMIS−30622
S
Slave Address
R/W
A
Internal Address
A
P
”0” = WRITE
Figure 29. Master Reading Data from AMIS−30622: First Transmission is Addressing
2. The second transmission consists of the slave
address and the read bit. Then the master can read
the data bits on the SDA line on every rising edge
of signal SCK. After each byte of data the master
has to acknowledge correct data reception by
S
Slave Address
R/W
A
pulling SDA LOW. The last byte is not
acknowledged by the master and therefore the
slave knows the end of transmission.
Data
Data
A
P
N bytes + Acknowledge
”0” = WRITE
Master to AMIS−30624
A
S = Start condition
P = Stop condition
A = Acknowledge (SDA = LOW)
A = No Acknowledge (SDA = HIGH)
AMIS−30624 to Master
Figure 30. Master Reading Data from AMIS−30622: Second Transmission is Reading Data
Notes:
1. Each byte is followed by an acknowledgment bit as indicated by the A or A in the sequence.
2. I2C−bus compatible devices must reset their bus logic on receipt of a START condition such that they all anticipate the sending of a
slave address, even if these START conditions are not positioned according to the proper format.
3. A START condition immediately followed by a STOP condition (void message) is an illegal format.
7−bit Addressing
The addressing procedure for the I2C−bus is such that the
first byte after the START condition usually determines
which slave will be selected by the master. The exception is
the general call address which can call all devices. When this
address is used all devices should respond with an
acknowledge. The second byte of the general call address
then defines the action to be taken.
AMIS−30622 is provided with a physical address in order
to discriminate this circuit from other circuits on the I2C bus.
This address is coded on seven bits (two bits being internally
hardwired to ‘1’), yielding the theoretical possibility of 32
different circuits on the same bus. It is a combination of four
OTP memory bits (OTP Memory Structure OPEN) and of
the externally hardwired address bits (pin HW). HW must
either be connected to ground or to Vbat. When HW is not
connected and is left floating, correct functionality of the
positioner is not guaranteed. The motor will be driven to the
programmed secure position (See Hardwired Address –
OPEN).
Definition of Bits in the First Byte
The first seven bits of the first byte make up the slave
address. The eighth bit is the least significant bit (LSB). It
determines the direction of the message. If the LSB is a
“zero” it means that the master will write information to a
selected slave. A “one” in this position means that the master
will read information from the slave. When an address is
sent, each device in a system compares the first seven bits
after the START condition with its address. If they match,
the device considers itself addressed by the master as a
slave−receiver or slave−transmitter, depending on the R/W
bit.
MSB
LSB
MSB
1
1
PA3 PA2 PA1 PA0 HW R/W
OTP memory
Hardwired Address Bit
Figure 32. First Byte after START Procedure
LSB
General Call Address
R/W
The AMIS−30622 supports also a “general call” address
“000 0000”, which can address all devices. When this
address is used all devices should respond with an
acknowledge. The second byte of the general call address
then defines the action to be taken.
SLAVE ADDRESS
Figure 31. First Byte after START Procedure
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AMIS−30622
I2C APPLICATION COMMANDS
Introduction
Communications between the AMIS−30622 and a 2−wire
serial bus interface master takes place via a large set of
commands.
Reading commands are used to:
♦ Get actual status information, e.g. error flags
♦ Get actual position of the stepper motor
♦ Verify the right programming and configuration of
the AMIS−30622.
Writing commands are used to:
♦ Program the OTP memory
♦ Configure the positioner with motion parameters
(max/min speed, acceleration, stepping mode, etc.)
♦ Provide target positions to the Stepper motor
The I2C−bus master will have to use commands to manage
the different application tasks the AMIS−30622 can feature.
The commands summary is given in Table 25.
Commands Table
Table 25. I2C COMMANDS WITH CORRESPONDING ROM POINTER
Command Byte
Command Mnemonic
Function
Binary
Hexadecimal
GetFullStatus1
Returns complete status of the chip
“1000 0001”
0x81
GetFullStatus2
Returns actual, target and secure position
“1111 1100”
0xFC
GetOTPParam
Returns OTP parameter
“1000 0010”
0x82
GotoSecurePosition
Drives motor to secure position
“1000 0100”
0x84
HardStop
Immediate full stop
“1000 0101”
0x85
ResetPosition
Sets actual position to zero
“1000 0110”
0x86
ResetToDefault
Overwrites the chip RAM with OTP contents
“1000 0111”
0x87
SetDualPosition
Drives the motor to two different positions with
different speed
“1000 1000”
0x88
SetMotorParam
Sets motor parameter
“1000 1001”
0x89
SetOTP
Zaps the OTP memory
“1001 0000”
0x90
SetPosition
Programs a target and secure position
“1000 1011”
0x8B
SoftStop
Motor stopping with deceleration phase
“1000 1111”
0x8F
These commands are described hereafter, with their
corresponding I2C frames. Refer to Data Transfer Formats
for more details. A color coding is used to distinguish
between master and slave parts within the frames. An
example is shown below.
Light Gray: Master Data
White: Slave Response
Figure 33. Color Code Used in the Definition of I2C Frames
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AMIS−30622
Application Commands
Note: A GetFullStatus1 command will attempt to
reset flags , , , ,
, , , , and
.
GetFullStatus1
This command is provided to the circuit by the master to
get a complete status of the circuit and of the stepper motor.
Refer to Tables 19 and 20 to see the meaning of the
parameters sent back to the I2C master.
GetFullStatus1 corresponds to the following I2C command frame:
Table 26. GetFullStatus1 COMMAND FRAME
Structure
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
0
0
0
1
Byte
Table 27. GetFullStatus1 RESPONSE FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
1
1
Address
1
1
1
OTP3
OTP2
OTP1
OTP0
HW
2
Data 1
Irun[3:0]
Ihold[3:0]
3
Data 2
Vmax[3:0]
Vmin[3:0]
4
Data 3
AccShape
5
Data 4
VddReset
6
Data 5
7
Data 6
1
1
8
Data 7
1
1
Where:
OTP(n)
HW
Irun[3:0]
Ihold[3:0]
Vmax[3:0]
Vmin[3:0]
AccShape
StepMode[1:0]
Shaft
Acc[3:0]
VddReset
StepMode[1:0]
StepLoss
ElDef
Shaft
UV2
TSD
TW
ESW
OVC1
OVC2
1
CPFail
1
1
1
1
1
1
1
1
1
1
1
1
Motion[2:0]
StepLoss
ElDef
UV2
TSD
TW
Tinfo[1:0]
Motion[2:0]
ESW
OVC1
OVC2
CPFail
OTP address bits PA[3:0]
Hardwired address bit
Operating current in the motor coil
Standstill current in the motor coil
Maximum velocity
Minimum velocity
Enables motion without acceleration
Step mode definition
Direction of movement
Acceleration form minimum to
maximum velocity
Reset of digital supply
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Acc[3:0]
Tinfo[1:0]
Step loss occurred
Electrical defect
Battery under voltage detected
Thermal shutdown
Thermal warning
Temperature Info
Motion status
External switch status
Over current in X−coil detected
Over current in Y−coil detected
Charge pump failure
AMIS−30622
GetFullStatus2
stepping mode the LSBs of ActPos[15:0] and
TagPos[15:0] may have no meaning and should be
assumed to be ‘0’. This command also gives additional
information concerning stall detection. Refer to Tables 19
and 20 to see the meaning of the parameters sent back to the
I2C master.
This command is provided to the circuit by the master to
get the actual, target and secure position of the stepper
motor. Both the actual and target position are returned in
signed two’s complement 16−bit format. Secure position is
coded in 10−bit format. According to the programmed
GetFullStatus2 corresponds to the following I2C command frame:
Table 28. GetFullStatus2 COMMAND FRAME
Structure
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
1
1
1
1
1
0
0
Byte
Table 29. GetFullStatus2 RESPONSE FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
1
1
Address
1
1
1
OTP3
OTP2
OTP1
OTP0
HW
2
Data 1
ActPos[15:8]
3
Data 2
ActPos[7:0]
4
Data 3
TagPos[15:8]
5
Data 4
TagPos[7:0]
6
Data 5
SecPos[7:0]
7
Data 6
1
1
1
1
1
8
Data 7
1
1
1
1
1
Where:
OTP(n)
HW
ActPos[15:0]
OTP address bits PA[3:0]
Hardwired address bit
Actual position
TagPos[15:0]
SecPos[10:0]
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SecPos[10:8]
1
Target position
Secure position
1
1
AMIS−30622
GetOTPParam
This command is provided to the circuit by the I2C master
to read the content of the OTP memory. More information
can be found in OTP Memory Structure corresponds to the
following I2C command frame:.
GetOTPParam
Table 30. GetOTPParam COMMAND FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
0
0
1
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OTP2
OTP1
OTP0
HW
1
Table 31. GetOTPParam RESPONSE FRAME
Structure
Content
Bit 7
Bit 6
Bit 5
0
Address
1
1
OTP3
1
OTP byte 0
OTP byte @0x00
2
OTP byte 1
OTP byte @0x01
3
OTP byte 2
OTP byte @0x02
4
OTP byte 3
OTP byte @0x03
5
OTP byte 4
OTP byte @0x04
6
OTP byte 5
OTP byte @0x05
7
OTP byte 6
OTP byte @0x06
8
OTP byte 7
OTP byte @0x07
Byte
the following I2C command frame: description for more
details. The priority encoder table also acknowledges the
cases where a GotoSecurePosition command will be
ignored.
GotoSecurePosition
This command is provided by the I2C master to one or all
the stepper motors to move to the secure position
SecPos[10:0]. See the priority encoder corresponds to
GotoSecurePosition
Table 32. GotoSecurePosition COMMAND FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
0
1
0
0
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AMIS−30622
HardStop
master at the next GetStatus1 command that steps may
have been lost. Once the motor is stopped, ActPos register
is copied into TagPos register to ensure keeping the stop
position. The I2C master for some safety reasons can also
issue a HardStop command.
This command will be internally triggered when an
electrical problem is detected in one or both coils, leading to
shutdown mode. If this occurs while the motor is moving,
the flag is raised to allow warning of the I2C
HardStop corresponds to the following I2C command frame:
Table 33. HardStop COMMAND FRAME
Structure
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
0
1
0
1
Byte
ResetPosition
This command is provided to the circuit by the I2C master
to reset ActPos and TagPos registers to zero. This can be
helpful to prepare for instance a relative positioning.
ResetPosition corresponds to the following I2C command frame:
Table 34. ResetPosition COMMAND FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
0
1
1
0
Note: ActPos and TagPos are not modified by a
ResetToDefault command.
Important: Care should be taken not to send a
ResetToDefault command while a motion is ongoing,
since this could modify the motion parameters in a way
forbidden by the position controller.
ResetToDefault
This command is provided to the circuit by the I2C master
in order to reset the whole slave node into the initial state.
ResetToDefault will, for instance, overwrite the RAM
with the reset state of the registers parameters (see Table 19).
This is another way for the I2C master to initialize a slave
node in case of emergency, or simply to refresh the RAM
content.
ResetToDefault corresponds to the following I2C command frame:
Table 35. ResetToDefault COMMAND FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
0
1
1
1
RunVelocity
This command is provided to the circuit by the I2C master
in order to put the motor in continuous motion state.
RunVelocity corresponds to the following I2C command frame:
Table 36. RunVelocity COMMAND FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
1
0
1
1
1
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AMIS−30622
SetDualPosition
command is issued, the circuit will enter in deadlock state.
Therefore, the application should check the actual position
by a GetFullStatus2 corresponds to the following I2C
command frame command prior to starting a dual
positioning. Another solution may consist of programming
a value out of the stepper motor range for Pos1[15:0].
For the same reason Pos2[15:0] should not be equal to
Pos1[15:0].
This command is provided to the circuit by the I2C master
in order to perform a positioning of the motor using two
different velocities. See Section Dual Positioning.
Note: This sequence cannot be interrupted by another
positioning command.
Important: If for some reason ActPos equals
Pos1[15:0] at the moment the SetDualPosition
SetDualPosition
Table 37. SetDualPosition COMMAND FRAME
Structure
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
1
0
0
0
2
Data 1
1
1
1
1
1
1
1
1
3
Data 2
1
1
1
1
1
1
1
1
4
Data 3
5
Data 4
6
Data 5
Pos1[7:0]
7
Data 6
Pos2[15:8]
8
Data 7
Pos2[7:0]
Byte
Where:
Vmax[3:0]
Vmin[3:0]
Vmax[3:0]
Vmin[3:0]
Pos1[15:8]
Max. velocity for first motion
Min. velocity for first motion and
velocity for the second motion
Pos1[15:0]
Pos2[15:0]
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45
First position to be reached during the
first motion
Relative position of the second motion
AMIS−30622
SetMotorParam
This command is provided to the circuit by the I2C master
to set the values for the stepper motor parameters (listed
below) in RAM. Refer to Table 19 to see the meaning of the
parameters sent by the I2C master.
Important: If a SetMotorParam occurs while a motion
is ongoing, it will modify at once the motion parameters (see
Position Controller corresponds to the following I2C
command frame:). Therefore the application should not
change parameters other than Vmax while a motion is
running, otherwise correct positioning cannot be
guaranteed.
SetMotorParam
Table 38. SetMotorParam COMMAND FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
1
0
0
1
2
Data 1
1
1
1
1
1
1
1
1
3
Data 2
1
1
1
1
1
1
1
1
4
Data 3
Irun[3:0]
Ihold[3:0]
5
Data 4
Vmax[3:0]
Vmin[3:0]
6
Data 5
7
Data 6
8
Data 7
SecPos[10:8]
Shaft
Acc[3:0]
SecPos[7:0]
1
1
1
AccShape
StepMode[1:0]
1
1
SetOTPParam
This command is provided to the circuit by the I2C master
to program and zap the OTP data D[7:0] in OTP address
OTPA[2:0].
Important: This command must be sent under a specific
VBB voltage value. See parameter VBBOTP in Table 5. This
is a mandatory condition to ensure reliable zapping.
SetOTPParam corresponds to the following I2C command frame:
Table 39. SetOTPParam COMMAND FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
1
0
0
0
0
2
Data 1
1
1
1
1
1
1
1
1
3
Data 2
1
1
1
1
1
1
1
1
4
Data 3
1
1
1
1
1
5
Data 4
Where:
OTPA[2:0]:
D[7:0]:
D[7:0]
OTP address
Corresponding OTP data
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46
OTPA[2:0]
AMIS−30622
SetPosition
This command is provided to the circuit by the I2C master
to drive the motor to a given absolute position. See
Positioning (see Priority Encoder) for more details. The
priority encoder table acknowledges the cases where a
SetPosition command will be ignored.
SetPosition corresponds to the following I2C command frame:
Table 40. SetPosition COMMAND FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
1
0
1
1
2
Data 1
1
1
1
1
1
1
1
1
3
Data 2
1
1
1
1
1
1
1
1
4
Data 3
Pos[15:8]
5
Data 4
Pos[7:0]
Where:
Pos [15:0]
Signed 16−bit position set−point for motor.
SoftStop
This command will be internally triggered when the chip
temperature rises above the thermal shutdown threshold (see
Table 5 and the Temperature Management Section). It
provokes an immediate deceleration to Vmin (see
Minimum Velocity corresponds to the following I2C
command frame:) followed by a stop, regardless of the
position reached. Once the motor is stopped, TagPos
register is overwritten with value in ActPos register to
ensure keeping the stop position. The I2C Master for some
safety reasons can also issue a SoftStop command.
SoftStop
Table 41. SoftStop COMMAND FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
1
1
1
1
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47
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN32, 7x7
CASE 560AA
ISSUE A
DOCUMENT NUMBER:
DESCRIPTION:
98AON30885E
QFN32, 7X7
DATE 23 SEP 2015
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
QFN32, 7x7
CASE 560AA
ISSUE A
DOCUMENT NUMBER:
DESCRIPTION:
98AON30885E
QFN32, 7X7
DATE 23 SEP 2015
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC 20 W
CASE 751AQ−01
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON30891E
SOIC 20 W
DATE 19 JUN 2008
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
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the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
ON Semiconductor and
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