SoC Ultra-Low Power
RF-Microcontroller for RF
Carrier Frequencies in the
Range 27 - 1050 MHz
AXM0F243
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OVERVIEW
Features
System−on−Chip (SoC) Ultra−low Power Advanced
Narrow−band
RF−microcontroller
for
Wireless
Communication Applications
• QFN40 Package
• Supply Range 1.8 V − 3.6 V
• −40°C to 85°C
• Deep Sleep Mode with Operational Analog and 2.5 mA
Digital System Current
• Radio RX−mode
6.5 mA @ 169 MHz
9.5 mA @ 868 MHz and 433 MHz
• Radio TX−mode at 868 MHz
7.6 mA @ 0 dBm
21 mA @ 10 dBm
55 mA @ 15 dBm
• This is a Pb−Free Device
1 40
QFN40 7x5, 0.5P
CASE 485EG
ORDERING INFORMATION
See detailed ordering and shipping information in Table 59 of
this data sheet.
Programmable Digital
• Programmable logic blocks allowing Boolean
operations to be performed on port inputs and outputs
Low−Power 1.8 V to 3.6 V Operation
• Deep Sleep mode with operational analog and 2.5 mA
digital system current
32−bit MCU Subsystem
• 48−MHz ARM Cortex−M0+ CPU
• Up to 64 KB of Flash with Read Accelerator
• Up to 8 KB of SRAM
Serial Communication
• Two independent run−time reconfigurable Serial
Communication Blocks (SCBs) with re−configurable
I2C, SPI, or UART functionality
Programmable Analog
• Two opamps with reconfigurable high−drive external
and high−bandwidth internal drive and Comparator
modes and ADC input buffering capability. Opamps
can operate in Deep Sleep low−power mode.
• 12−bit 1−Msps SAR ADC with differential and
single−ended modes
• Single−slope 10−bit ADC function
• Two current DACs (IDACs) for general−purpose
applications on any pin
• One low−power comparator that operates in Deep Sleep
low−power mode
• Five 16−bit timer/counter/pulse−width modulator
© Semiconductor Components Industries, LLC, 2018
March, 2020 − Rev. 2
Timing and Pulse−Width Modulation
•
•
(TCPWM) blocks, of which three PWMs can be
connected to GPIO Pins
Center−aligned, Edge, and Pseudo−random modes
Comparator−based triggering of Kill signals for motor
drive and other high−reliability digital logic
applications
Up to 19 Programmable GPIO Pins
• Any GPIO pin can be analog, or digital
• Drive modes, strengths, and slew rates are
programmable
1
Publication Order Number:
AXM0F243/D
AXM0F243
High Performance Narrow−band RF Transceiver
compatible to AX5043 (FSK/MSK/4−FSK/GFSK/GMSK/
ASK/AFSK/FM/PSK)
• Receiver
♦ Carrier Frequencies from 27 to 1050 MHz
♦ Data Rates from 0.1 kbps to 125 kbps
♦ Optional Forward Error Correction (FEC)
♦ Sensitivity without FEC
−135 dBm @ 0.1 kbps, 868 MHz, FSK
−126 dBm @ 1 kbps, 868 MHz, FSK
−117 dBm @ 10 kbps, 868 MHz, FSK
−107 dBm @ 100 kbps, 868 MHz, FSK
−105 dBm @ 125 kbps, 868 MHz, FSK
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
• Flexible Antenna Interface
−138 dBm @ 0.1 kbps, 868 MHz, PSK
−130 dBm @ 1 kbps, 868 MHz, PSK
−120 dBm @ 10 kbps, 868 MHz, PSK
−109 dBm @ 100 kbps, 868 MHz, PSK
−108 dBm @ 125 kbps, 868 MHz, PSK
Sensitivity with FEC
−137 dBm @ 0.1 kbps, 868 MHz, FSK
−122 dBm @ 5 kbps, 868 MHz, FSK
−111 dBm @ 50 kbps, 868 MHz, FSK
High Selectivity Receiver with up to 47 dB Adjacent
Channel Rejection
0 dBm Maximum Input Power
±10% Data−rate Error Tolerance
Support for Antenna Diversity with External
Antenna Switch
Short Preamble Modes allow the Receiver to work
with as little as 16 Preamble Bits
Fast State Switching Times
200 ms TX → RX Switching Time
62 ms RX → TX Switching Time
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
640 Hz or 10 kHz Lowest Power Wake−up Timer
Wake−up Time Interval programmable between
98 ms and 102 s
• Sophisticated Radio Controller
♦
♦
♦
♦
♦
♦
Carrier Frequencies from 27 to 1050 MHz
Data−rates from 0.1 kbps to 125 kbps
High Efficiency, High Linearity Integrated Power
Amplifier
Maximum Output Power
16 dBm @ 868 MHz
16 dBm @ 433 MHz
16 dBm @ 169 MHz
Power Level programmable in 0.5 dB Steps
GFSK Shaping with BT=0.3 or BT=0.5
Unrestricted Power Ramp Shaping
♦
♦
♦
Antenna Diversity and RX/TX Switch Control
Fully Automatic Packet Reception and Transmission
without Micro−controller Intervention
Supports HDLC, Raw, Wireless M−Bus Frames and
Arbitrary Defined Frames
Automatic Channel Noise Level Tracking
ms Resolution Timestamps for Exact Timing (eg. for
Frequency Hopping Systems)
256 Byte Micro−programmable FIFO, optionally
supports Packet Sizes > 256 Bytes
Three Matching Units for Preamble Byte,
Sync−word and Address
Ability to store RSSI, Frequency Offset and
Data−rate Offset with the Packet Data
Multiple Receiver Parameter Sets allow the use of
more aggressive Receiver Parameters during
Preamble, dramatically shortening the Required
Preamble Length at no Sensitivity Degradation
• Advanced Crystal Oscillator (RF Reference Oscillator)
♦
• RF Frequency Generation
♦
Integrated RX/TX Switching with Differential
Antenna Pins
Mode with Differential RX Pins and Single−ended
TX Pin for Usage with External PAs and for
Maximum PA Efficiency at Low Output Power
• Wakeup−on−Radio
• Transmitter
♦
Ultra Fast Settling RF Frequency Synthesizer for
Low−power Consumption
Fully Integrated RF Frequency Synthesizer with
VCO Auto−ranging and Band−width Boost Modes
for Fast Locking
Configurable for either Fully Integrated VCO,
Internal VCO with External Inductor or Fully
External VCO
Configurable for either Fully Integrated or External
Synthesizer Loop Filter for a Large Range of
Bandwidths
Channel Hopping up to 2000 hops/s
Automatic Frequency Control (AFC)
♦
Configurable for Usage in 27 MHz −1050 MHz
Bands
RF Carrier Frequency and FSK Deviation
Programmable in 1 Hz Steps
♦
Fast Start−up and Lowest Power Steady−state XTAL
Oscillator for a Wide Range of Crystals
Integrated Tuning Capacitors
Possibility of Applying an External Clock Reference
(TCXO)
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2
AXM0F243
• Messaging Paging
• Compatible with: Wireless M−Bus, POCSAG, FLEX,
Applications
27 − 1050 MHz Licensed and Unlicensed Radio Systems
• Internet of Things
• Automatic meter reading (AMR)
• Security applications
• Building automation
• Wireless networks
KNX, Sigfox, Z−Wave, enocean
• Regulatory Regimes: EN 300 220 V2.3.1 including the
Narrow−band 12.5 kHz, 20 kHz and 25 kHz
Definitions; EN 300 422; FCC Part 15.247; FCC Part
15.249; FCC Part 90 6.25 kHz, 12.5 kHz and 25 kHz
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3
AXM0F243
GPADC1
GPADC2
BLOCK DIAGRAM
AXM0F243
VSSA
VSSD
Modulator
Radio configuration
ANTP1
PA
se
L1
L2
FILT
RF Frequency
Generation
Subsystem
CLK16P
CLK16N
VDDA
VDDD
VCCD
VDDD
Communication Controller &
Radio Interface Controller
POR, references
FOUT
low power
oscillator
640 Hz/ 10 kHz
Wake on Radio
FXTAL
Crystal
Oscillator
typ. 16MHz
CPU Subsystem
SWD/TC
SPCIF
Cortex
M0+
Divider
Voltage
Regulator
FLASH
64 KB
48 MHz
FAST MUL
NVIC, IRQMUX
Voltage
Regulator
SRAM
8 KB
Read Accelerator
SRAM Controller
System Interconnect (Single Layer AHB)
SYSCLK
System Resources
Lite
Peripherals
Peripheral Interconnect (MMIO)
PCLK
Reset Control
XRES
Power Modes
Active/ Sleep
DeepSleep
x1
WCO
5x TCPWM
SAR ADC
(12−bit)
1x LP Comparator
Reset
CTBm
2x Opamp x1
I/O Subsystem
High Speed I/O Matrix & 2 x Programmable I/O
Figure 1. Functional Block Diagram of the AXM0F243
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4
P3.7
P4.0
P4.1
P4.2
P4.3
P1.7
P3.2
P3.3
P3.6
P1.0
P1.1
P1.2
P1.3
19x GPIOs, LCD
P0.0
P0.1
P0.2
P0.4
P0.5
P0.6
XRES
IOSS GPIO (4x ports)
Clock
Clock Control
WDT
ILO
IMO
Programmable
Analog
2x SCB−I2C/SPI/UART
Power
Sleep Control
WIC
POR
REF
PWRSYS
FIFO/packet buffer
AGC
PA
diff
Radio controller
timing and packet
handling
RSSI
ANTN
Demodulator
Framing
ANTP
Digital IF
Channel
Filter
ADC
Encoder
IF Filter
& AGC
PGAs
LNA
Forward error
correction
Mixer
AXM0F243
Table 1. PIN FUNCTION DESCRIPTION
Symbol
Pin(s)
Type
VDDA
1
P
Analog power output, decouple to neighboring VSSA
VSSA
2
P
Ground, decouple to neighboring VDDA
ANTP
3
A
Differential antenna input/output
ANTN
4
A
Differential antenna input/output
ANTP1
5
A
Single−ended antenna output
VSSA
6
P
Ground, decouple to neighboring VDDA
VDDA
7
P
Analog power output, decouple to neighboring VSSA
VSSA
8
P
Ground
FILT
9
A
Optional synthesizer filter
L2
10
A
Optional synthesizer inductor
L1
11
A
Optional synthesizer inductor
VSSD
12
P
Ground
SYSCLK
13
I/O/PU
P3.2
14
I/O/PU/PD/A
General purpose IO
P3.3
15
I/O/PU/PD/A
General purpose IO
P3.6
16
I/O/PU/PD/A
General purpose IO
P3.7
17
I/O/PU/PD/A
General purpose IO
P4.0
18
I/O/PU/PD/A
General purpose IO
P4.1
19
I/O/PU/PD/A
General purpose IO
P4.2
20
I/O/PU/PD/A
General purpose IO
P4.3
21
I/O/PU/PD/A
General purpose IO
P0.0
22
I/O/PU/PD/A
General purpose IO
P0.1
23
I/O/PU/PD/A
General purpose IO
P0.2
24
I/O/PU/PD/A
General purpose IO
P0.4
25
I/O/PU/PD/A
General purpose IO
P0.5
26
I/O/PU/PD/A
General purpose IO
P0.6
27
I/O/PU/PD/A
General purpose IO
XRES
28
I/PU
VCCD
29
P
Regulated digital supply, decouple to ground
VDDD
30
P
Unregulated power supply
P1.0
31
I/O/PU/PD/A
General purpose IO
P1.1
32
I/O/PU/PD/A
General purpose IO
P1.2
33
I/O/PU/PD/A
General purpose IO
P1.3
34
I/O/PU/PD/A
General purpose IO
P1.7
35
I/O/PU/PD/A
General purpose IO
VDDD
36
P
Unregulated power supply
GPADC1
37
A
GPADC input, must be connected to GND if not used
GPADC2
38
A
GPADC input, must be connected to GND if not used
CLK16N
39
A
Crystal oscillator input/output (RF reference oscillator)
CLK16P
40
A
Crystal oscillator input/output (RF reference oscillator)
Center pad
P
Ground on center pad of QFN, must be connected
GND
Description
Default functionality: system clock output
Reset pin
N = not to be connected
P = power or ground
PD = pull−down
A = analog input
I = digital input signal
O = digital output signal
PU = pull−up
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5
AXM0F243
Alternate Pin Functions
Each Port pin has can be assigned to one of multiple
functions; it can, for instance, be an analog I/O or a digital
peripheral function. The pin assignments are shown in the
following table.
Table 2. ALTERNATE PIN FUNCTIONS
HSIOM_PORT_SEL[x].SELy (*5)
Active
ACTIVE #1
ACTIVE #2
ACTIVE #3
Deep Sleep #2
Deep Sleep #3
P0.0
scb[2].uart_cts:0
dsi_sar_data_vali
d:0
tcpwm.tr_in[0]
scb[2].i2c_scl:0
scb[0].spi_select1:0
P0.1
scb[2].uart_rts:0
tr_sar_out
tcpwm.tr_in[1]
scb[2].i2c_sda:0
scb[0].spi_select2:0
Pin
ACTIVE #0
DeepSleep
P0.2
dsi_sar_sample_d
one
P0.4
dsi_sar_data[0]:0
scb[2].uart_rx:0
P0.5
dsi_sar_data[1]:0
scb[2].uart_tx:0
P0.6
srss.ext_clk
scb[0].spi_select3:0
scb[2].uart_tx:1
P1.0
tcpwm.line[2]:1
scb[0].uart_rx:1
scb[0].i2c_scl:0
scb[0].spi_mosi:1
P1.1
tcpwm.line_compl
[2]:1
scb[0].uart_tx:1
scb[0].i2c_sda:0
scb[0].spi_miso:1
P1.2
tcpwm.line[3]:1
scb[0].uart_cts:1
dsi_sar_data[3]:0
tcpwm.tr_in[2]
scb[2].i2c_scl:1
scb[0].spi_clk:1
P1.3
tcpwm.line_compl
[3]:1
scb[0].uart_rts:1
dsi_sar_data[4]:0
tcpwm.tr_in[3]
scb[2].i2c_sda:1
scb[0].spi_select0:1
P1.7
scb[2].spi_clk
P3.2
tcpwm.line[1]:0
cpuss.swd_data
P3.3
tcpwm.line_compl
[1]:0
cpuss.swd_clk
P3.6
tcpwm.line[3]:0
dsi_ctb_cmp0
P3.7
tcpwm.line_compl
[3]:0
dsi_ctb_cmp1
P4.0
scb[0].uart_rx:0
P4.1
scb[0].uart_tx:0
dsi_sar_data[9]:0
P4.2
scb[0].uart_cts:0
dsi_sar_data[10]:0
P4.3
scb[0].uart_rts:0
dsi_sar_data[11]:0
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6
scb[2].spi_miso
scb[0].i2c_scl:1
scb[0].spi_mosi:0
scb[0].i2c_sda:1
scb[0].spi_miso:0
lpcomp.comp[0]:0
scb[0].spi_clk:0
scb[0].spi_select0:0
AXM0F243
Table 3. ANALOG PIN FUNCTION
Pin
Analog
P0.0
lpcomp[0].vplus
P0.1
lpcomp[0].vminus
P0.2
P0.4
wco[0].wco_in
P0.5
wco[0].wco_out
P0.6
srss[0].adft_por_pad_hv
P1.0
ctb0_oa[0].vplus
P1.1
ctb0_oa[0].vminus
P1.2
ctb0_oa[0].vout10x
P1.3
ctb0_oa[1].vout10x
P1.5
ctb0_oa[1].vplus
P1.7
ctb0_oa[1].vplus
sar_ext_vref
P3.2
P3.3
P3.6
ctb0_oa[0].dsi_comp
P3.7
ctb0_oa[1].dsi_comp
P4.0
P4.1
P4.2
P4.3
GPADC2
GPADC1
VDDD
P1.7
P1.3
P1.2
P1.1
P1.0
39
38
37
36
35
34
33
32
31
30
VCCD
CLK16N
40
VDDD
CLK16P
PINOUT DRAWING
29
VDDA
1
28
XRES
VSSA
2
27
P0.6
ANTP
3
26
P0.5
ANTN
4
25
P0.4
ANTP1
5
24
P0.2
VSSA
6
23
P0.1
VDDA
7
22
P0.0
VSSA
8
21
P4.3
AXM0F243
SYSCLK
P3.2
16
17
18
19
20
P4.2
VSSD
15
P4.1
14
P4.0
13
P3.7
12
P3.6
11
P3.3
10
L1
FILT
9
L2
QFN40
Figure 2. Pinout Drawing (Top View)
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7
AXM0F243
SPECIFICATIONS
Table 4. ABSOLUTE MAXIMUM RATINGS (Note 1)
Symbol
Description
Condition
VDDD
Supply voltage
IDD
Supply current
Ptot
Total power consumption
Pi
Absolute maximum input power at receiver input
II1
DC current into pin SYSCLK
II2
DC current into GPIO
II3
Via
Min
Max
Units
−0.5
5.5
V
200
mA
800
mW
10
dBm
−10
10
mA
−25
25
mA
DC current into pins ANTP, ANTN, ANTP1
−100
100
mA
Input voltage ANTP, ANTN, ANTP1 pins
−0.5
5.5
V
Input voltage GPIO pins
−0.5
VDDD + 0.5
V
−2000
2000
V
ANTP and ANTN
pins in RX mode
Ves
Electrostatic handling
HBM
Lu
GPIO pin current for latch−up
−140
140
mA
Tamb
Operating temperature
−40
85
°C
Tstg
Storage temperature
−65
150
°C
Tj
Junction Temperature
150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics
Table 5. SUPPLIES
Sym
Description
Condition
Min
Typ
Max
Units
TAMB
Operational ambient temperature
−40
27
85
°C
VDDD
I/O and voltage regulator supply voltage
1.8
3.0
3.6
V
IDDsleep1
Sleep mode
I2C wakeup, WDT and Comparators on
6 MHz. Max is at 85°C and 3.6 V
1.7
mA
IDDsleep2
Sleep mode
I2C wakeup, WDT and Comparators on
12 MHz. Max is at 85°C and 3.6 V
2.2
mA
IDDdeepsleep
Deep Sleep current
I2C wakeup and WDT on
Max is at 85°C and 3.6 V
2.5
mA
IDD6
CPU at 6 MHz, execute from flash
Max is at 85°C and 3.6 V
1.8
mA
IDD24
CPU at 24 MHz, execute from flash
Max is at 85°C and 3.6 V
3.0
mA
IDD48
CPU at 48 MHz, execute from flash
Max is at 85°C and 3.6 V
5.4
mA
IDDxres
Supply current while XRES asserted
2
mA
IRX
Current consumption RX
RF frequency generation subsystem:
Internal VCO and internal loop−fiter
868 MHz, datarate 6 kbps
9.5
mA
169 MHz, datarate 6 kbps
6.5
868 MHz, datarate 100 kbps
11
169 MHz, datarate 100 kbps
7.5
868 MHz, 15 dBm, CW, Note 2
RF frequency generation subsystem:
Internal VCO and internal loop−filter
Antenna configuration:
Differential PA, internal RX/TX switch
55
ITX−DIFF
Current consumption TX
differential
2. Measured with optimized matching networks.
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8
mA
AXM0F243
Table 5. SUPPLIES
Sym
Description
Condition
Min
ITX_SE
Current consumption TX
single ended
868 MHz, 0 dBm, FSK, Note 2
RF frequency generation subsystem:
Internal VCO and internal loop−filter
Antenna configuration:
Single ended PA, external RX/TX
switching
IWOR
Typical wake−on−radio duty cycle current
1 s, 100 kbps
Typ
Max
Units
7.6
mA
6
mA
2. Measured with optimized matching networks.
For information on current consumption in complex
modes of operation tailored to your application, see the
software AX−RadioLab.
Both AXM0F243 power amplifiers run from the
regulated VDDA supply and not directly from the battery.
This has the advantage that the current and output power do
not vary much over supply voltage and temperature.
Table 6. AC SPECIFICATIONS
Parameter
Description
Min
Typ
Max
Units
FCPU
CPU frequency
DC
–
48
MHz
TSLEEP [3]
CPU Wakeup from Sleep mode
–
0
–
ms
TDEEPSLEEP [3]
CPU Wakeup from Deep Sleep mode
–
35
–
3. Guaranteed by characterization.
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9
Details/
Conditions
AXM0F243
GPIO
Table 7. GPIO DC SPECIFICATIONS
Parameter
Description
Min
Typ
Max
Units
0.7 x VDDD
–
–
V
Input voltage low threshold
–
–
0.3 x VDDD
LVTTL input, VDDD < 2.7 V
0.7 x VDDD
–
–
–
LVTTL input, VDDD < 2.7 V
–
–
0.3 x VDDD
–
LVTTL input, VDDD ≥ 2.7 V
2.0
–
–
–
VIL
LVTTL input, VDDD ≥ 2.7 V
–
–
0.8
–
VOH
Output voltage high level
VDDD – 0.6
–
–
IOH = 4 mA at 3 V VDDD
VOH
Output voltage high level
VDDD – 0.5
–
–
IOH = 1 mA at 1.8 V VDDD
VOL
Output voltage low level
–
–
0.6
IOL = 4 mA at 1.8 V VDDD
VOL
Output voltage low level
–
–
0.6
IOL = 10 mA at 3 V VDDD
VOL
Output voltage low level
–
–
0.4
IOL = 3 mA at 3 V VDDD
RPULLUP
Pull−up resistor
3.5
5.6
8.5
RPULLDOWN
Pull−down resistor
3.5
5.6
8.5
IIL
Input leakage current (absolute value)
–
–
1
CIN
Input capacitance
–
–
VHYSTTL [5]
Input hysteresis LVTTL
25
40
VHYSCMOS [5]
Input hysteresis CMOS
0.05 x VDDD
–
–
ITOT_GPIO [5]
Maximum total source or sink chip current
–
–
Min
2
VIH [4]
Input voltage high threshold
VIL
VIH [4]
VIL
VIH [4]
Details/ Conditions
CMOS Input
CMOS Input
kW
–
–
mA
25°C, VDDD = 3.0 V
7
pF
–
–
mV
VDDD ≥ 2.7 V
200
mA
–
Typ
Max
Units
Details/ Conditions
–
12
ns
3.3 V VDDD, Cload = 25 pF
4. VIH must not exceed VDDD + 0.2 V
5. Guaranteed by characterization.
Table 8. GPIO AC SPECIFICATIONS *
Parameter
Description
TRISEF
Rise time in fast strong mode
TFALLF
Fall time in fast strong mode
2
–
12
TRISES
Rise time in slow strong mode
10
–
60
−
3.3 V VDDD, Cload = 25 pF
TFALLS
Fall time in slow strong mode
10
–
60
−
3.3 V VDDD, Cload = 25 pF
FGPIOUT1
GPIO FOUT; 3.3 V ≤ VDDD ≤ 3.6 V
Fast strong mode
−
–
33
MHz
FGPIOUT2
GPIO FOUT; 1.8 V ≤ VDDD ≤ 3.3 V
Fast strong mode
−
–
16.7
90/10%, 25 pF load,
60/40 duty cycle
FGPIOUT3
GPIO FOUT; 3.3 V ≤ VDDD ≤ 3.6 V
Slow strong mode
−
–
7
90/10%, 25 pF load,
60/40 duty cycle
FGPIOUT4
GPIO FOUT; 1.8 V ≤ VDDD ≤ 3.3 V
Slow strong mode
−
–
3.5
90/10%, 25 pF load,
60/40 duty cycle
FGPIOIN
GPIO input operating frequency;
1.8 V ≤ VDDD ≤ 3.6 V
−
–
48
90/10% VIO
*Guaranteed by characterization.
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10
3.3 V VDDD, Cload = 25 pF
90/10%, 25 pF load,
60/40 duty cycle
AXM0F243
XRES
Table 9. XRES DC SPECIFICATIONS
Min
Typ
Max
Units
VIH
Parameter
Input voltage high threshold
Description
0.7 x VDDD
–
–
V
VIL
Input voltage low threshold
–
–
0.3 x VDDD
RPULLUP
Pull−up resistor
−
60
−
CIN
Input capacitance
–
–
7
pF
VHYSXRES [6]
Input voltage hysteresis
−
100
–
mV
Min
Typ
Max
Units
Details/ Conditions
CMOS Input
CMOS Input
kW
Table 10. XRES AC SPECIFICATIONS
Parameter
Description
TRESETWIDTH [6]
Reset pulse width
1
–
–
ms
TRESETWAKE [6]
Wake−up time from reset release
–
–
2.7
ms
Details/ Conditions
6. Guaranteed by characterization.
Table 11. SYSCLK DC SPECIFICATIONS
Min
Typ
Max
Units
VIL
Parameter
Input voltage low threshold
Description
–
–
0.8
V
at 3.3 V VDDD
Details/ Conditions
VIH
Input voltage high threshold
2.0
–
–
V
at 3.3 V VDDD
RPULLUP
Pull−up resistor
−
65
−
kW
VOL
Output voltage low level
−
−
0.4
V
IOL = 4 mA at 3 V VDDD
VOH
Output voltage high level
2.4
–
−
V
IOH = 4 mA at 3 V VDDD
Analog Peripherals
Table 12. CTBm OPAMP SPECIFICATIONS
Description
Parameter
IDD
Min
Typ
Max
Units
mA
Details/ Conditions
Opamp block current, External load
IDD_HI
power=hi
–
1100
−
IDD_MED
power=med
–
550
−
–
IDD_LOW
power=lo
–
150
−
–
GBW
–
Load = 20 pF, 0.1 mA VDDD = 2.7 V
MHz
Input and output are
0.2 V to VDDD−0.2 V
GBW_HI
power=hi
6
–
–
GBW_MED
power=med
3
–
–
Input and output are
0.2 V to VDDD−0.2 V
GBW_LO
power=lo
–
1
–
Input and output are
0.2 V to VDDD−0.2 V
IOUT_MAX
VDDD = 2.7 V, 500 mV from rail
IOUT_MAX_HI
power=hi
10
–
–
IOUT_MAX_MID
power=mid
10
–
–
Output is 0.5 V
VDDD−0.5 V
IOUT_MAX_LO
power=lo
–
5
–
Output is 0.5 V
VDDD−0.5 V
IOUT
VDDD = 1.8 V, 500 mV from rail
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11
mA
Output is 0.5 V
VDDD−0.5 V
AXM0F243
Table 12. CTBm OPAMP SPECIFICATIONS
Description
Parameter
Min
Typ
Max
Units
Details/ Conditions
Output is 0.5 V
VDDD−0.5 V
IOUT_MAX_HI
power=hi
4
–
–
IOUT_MAX_MID
power=mid
4
–
–
IOUT_MAX_LO
power=lo
–
2
–
IDD_Int
Opamp block current Internal Load
IDD_HI_Int
power=hi
–
1500
−
IDD_MED_Int
power=med
–
700
−
–
IDD_LOW_Int
power=lo
–
–
–
–
GBW
VDDD = 2.7 V
–
–
–
–
GBW_HI_Int
power=hi
8
–
–
MHz
V
mA
Output is 0.5 V
VDDD−0.5 V
Output is 0.5 V
VDDD−0.5 V
mA
–
Output is 0.25 V to
VDDD−0.25 V
General opamp specs for both internal and external modes
VIN
Charge−pump on, VDDD = 2.7 V
–0.05
–
VDDD−0.2
VCM
Charge−pump on, VDDD = 2.7 V
–0.05
–
VDDD−0.2
VOUT
VDDD = 2.7 V
VOUT_1
power=hi, Iload=10 mA
0.5
–
VDDD −0.5
VOUT_2
power=hi, Iload=1 mA
0.2
–
VDDD −0.2
–
VOUT_3
power=med, Iload=1 mA
0.2
–
VDDD −0.2
–
VOUT_4
power=lo, Iload=0.1 mA
0.2
–
VDDD −0.2
–
Offset voltage, trimmed
–1.0
VOS_TR
VOS_TR
VOS_TR
Offset voltage, trimmed
Offset voltage, trimmed
±0.5
1.0
–
–
V
mV
–
High mode, input 0 V to
VDDD−0.2 V
–
±1
–
Medium mode, input 0 V
to VDDD−0.2 V
–
±2
–
Low mode, input 0 V to
VDDD−0.2 V
VOS_DR_TR
Offset voltage drift, trimmed
–10
±3
10
mV/C
VOS_DR_TR
Offset voltage drift, trimmed
–
±10
–
mV/C
VOS_DR_TR
Offset voltage drift, trimmed
–
±10
–
CMRR
DC
70
80
–
PSRR
At 1 kHz, 10−mV ripple
70
85
–
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12
High mode
Medium mode
Low mode
dB
Input is 0 V to VDDD−0.2
V, Output is 0.2 V to
VDDD−0.2 V
VDDD = 3.6 V, high−power
mode, input is 0.2 V to
VDDD−0.2 V
AXM0F243
Table 12. CTBm OPAMP SPECIFICATIONS
Description
Units
Min
Typ
Max
Input−referred, 1 kHz, power=Hi
–
72
–
Input−referred, 10 kHz, power=Hi
–
28
–
Input and output are at
0.2 V to VDDD−0.2 V
Input−referred, 100 kHz, power=Hi
–
15
–
Input and output are at
0.2 V to VDDD−0.2 V
Stable up to max. load. Performance specs at
50 pF.
–
–
125
pF
–
6
–
–
V/ms
–
–
Parameter
Details/ Conditions
Noise
VN2
VN3
VN4
CLOAD
SLEW_RATE
Cload = 50 pF, Power = High, VDDD = 2.7 V
nV/rtHz
T_OP_WAKE
From disable to enable, no external RC dominating
–
–
25
ms
OL_GAIN
Open Loop Gain
–
90
–
dB
3
Comparator mode; 50 mV drive, Trise=Tfall (apCOMP_MODE prox.)
ns
Input is 0.2 V to
VDDD−0.2 V
TPD1
Response time; power=hi
–
150
–
TPD2
Response time; power=med
–
500
–
Input is 0.2 V to
VDDD−0.2 V
TPD3
Response time; power=lo
–
2500
–
Input is 0.2 V to
VDDD−0.2 V
VHYST_OP
Hysteresis
–
10
–
mV
–
Wake−up time from Enabled to Usable
–
–
25
ms
–
WUP_CTB
Deep Sleep
Mode
Mode 2 is lowest current range. Mode 1 has
higher GBW.
IDD_HI_M1
Mode 1, High current
–
1400
–
IDD_MED_M1
Mode 1, Medium current
–
700
–
25°C
IDD_LOW_M1
Mode 1, Low current
–
200
–
25°C
IDD_HI_M2
Mode 2, High current
–
120
–
25°C
IDD_MED_M2
Mode 2, Medium current
–
60
–
25°C
IDD_LOW_M2
Mode 2, Low current
–
15
–
25°C
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13
mA
25°C
AXM0F243
Table 12. CTBm OPAMP SPECIFICATIONS
Parameter
Description
Min
Typ
Max
Units
MHz
Details/ Conditions
GBW_HI_M1
Mode 1, High current
–
4
–
GBW_MED_M1
Mode 1, Medium current
–
2
–
GBW_LOW_M1
Mode 1, Low current
–
0.5
–
GBW_HI_M2
Mode 2, High current
–
0.5
–
GBW_MED_M2
Mode 2, Medium current
–
0.2
–
GBW_Low_M2
Mode 2, Low current
–
0.1
–
VOS_HI_M1
Mode 1, High current
–
5
–
VOS_MED_M1
Mode 1, Medium current
–
5
–
With trim 25°C, 0.2 V to
VDDD−0.2 V
VOS_LOW_M2
Mode 1, Low current
–
5
–
With trim 25°C, 0.2 V to
VDDD−0.2 V
VOS_HI_M2
Mode 2, High current
–
5
–
With trim 25°C, 0.2V to
VDDD−0.2 V
VOS_MED_M2
Mode 2, Medium current
–
5
–
With trim 25°C, 0.2 V to
VDDD−0.2 V
VOS_LOW_M2
Mode 2, Low current
–
5
–
With trim 25°C, 0.2 V to
VDDD−0.2 V
IOUT_HI_M!
Mode 1, High current
–
10
–
IOUT_MED_M1
Mode 1, Medium current
–
10
–
Output is 0.5 V to
VDDD−0.5 V
IOUT_LOW_M1
Mode 1, Low current
–
4
–
Output is 0.5 V to
VDDD−0.5 V
IOUT_HI_M2
Mode 2, High current
–
1
–
IOU_MED_M2
Mode 2, Medium current
–
1
–
IOU_LOW_M2
Mode 2, Low current
–
0.5
–
20−pF load, no DC load
0.2 V to VDDD−0.2 V
20−pF load, no DC load
0.2 V to VDDD−0.2 V
20−pF load, no DC load
0.2 V to VDDD−0.2 V
20−pF load, no DC load
0.2 V to VDDD−0.2 V
20−pF load, no DC load
0.2 V to VDDD−0.2 V
20−pF load, no DC load
0.2 V to VDDD−0.2 V
mV
With trim 25°C, 0.2 V to
VDDD−0.2 V
mA
Output is 0.5 V to
VDDD−0.5 V
Table 13. COMPARATOR DC SPECIFICATIONS
Parameter
Description
Min
Typ
Max
Units
mV
VOFFSET1
Input offset voltage, Factory trim
–
–
±10
VOFFSET2
Input offset voltage, Custom trim
–
–
±4
VHYST
Hysteresis when enabled
–
10
35
VICM1
Input common mode voltage in normal mode
0
–
VDDD−0.1
VICM2
Input common mode voltage in low power mode
0
–
VDDD
0
–
VDDD−1.15
VICM3
Input common mode voltage in ultra low power mode
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14
V
Details/ Conditions
Modes 1 and 2
VDDD ≥ 2.2 V at
–40°C
AXM0F243
Table 13. COMPARATOR DC SPECIFICATIONS
CMRR
Common mode rejection ratio
50
–
–
CMRR
Common mode rejection ratio
42
–
–
ICMP1
Block current, normal mode
–
–
400
ICMP2
Block current, low power mode
–
–
100
ICMP3
Block current in ultra low−power mode
–
–
6
ZCMP
DC Input impedance of comparator
35
–
–
dB
VDDD ≥ 2.7 V
VDDD ≤ 2.7 V
mA
VDDD ≥ 2.2 V at
–40°C
MW
Table 14. COMPARATOR AC SPECIFICATIONS
Description
Parameter
Min
Typ
Max
Units
ns
TRESP1
Response time, normal mode, 50 mV overdrive
–
38
110
TRESP2
Response time, low power mode, 50 mV overdrive
–
70
200
TRESP3
Response time, ultra−low power mode, 200 mV overdrive
−
2.3
15
ms
Min
Typ
Max
Units
–5
±1
5
°C
Min
Typ
Max
Units
bits
Details/ Conditions
VDDD ≥ 2.2 V at
–40°C
Table 15. TEMPERATURE SENSOR SPECIFICATIONS
Description
Parameter
TSENSACC Temperature sensor accuracy
Details/ Conditions
−40 to +85°C
Table 16. SAR SPECIFICATIONS
Parameter
Description
Details/ Conditions
SAR ADC DC Specifications
A_RES
Resolution
–
–
12
A−MONO
Monotonicity
–
–
–
A_GAINERR
Gain error
–
–
±0.1
%
With external reference.
A_OFFSET
Input offset voltage
–
–
2
mV
Measured with 1−V
reference
A_ISAR
Current consumption
–
–
1
mA
A_VINS
Input voltage range − single ended
VSS
–
VDDD
V
A_VIND
Input voltage range − differential[
VSS
–
VDDD
V
A_INRES
Input resistance
–
–
2.2
KW
A_INCAP
Input capacitance
–
–
10
pF
dB
Yes.
SAR ADC AC Specifications
A_PSRR
Power supply rejection ratio
70
–
–
A_CMRR
Common mode rejection ratio
66
–
–
dB
A_SAMP
Sample rate
–
–
1
Msps
A_SNR
Signal−to−noise and distortion ratio (SINAD)
65
–
–
dB
A_BW
Input bandwidth without aliasing
–
–
A_samp/2
kHz
A_INL
Integral non linearity VDD = 1.8 V to 3.6 V, 1 Msps
–1.7
–
2
LSB
VREF = 1 V to VDD
A_INL
Integral non linearity. VDD = 1.8 V to 3.6 V, 1 Msps
–1.5
–
1.7
LSB
VREF = 1.8 V to VDD
A_INL
Integral non linearity. VDD = 1.8 V to 3.6 V, 500 ksps
–1.5
–
1.7
LSB
VREF = 1 V to VDD
A_DNL
Differential non linearity. VDD = 1.8 V to 3.6 V, 1 Msps
–1
2.2
LSB
VREF = 1 V to VDD
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15
–
Measured at 1 V
FIN = 10 kHz
AXM0F243
Table 16. SAR SPECIFICATIONS
A_DNL
Differential non linearity. VDD = 1.8 V to 3.6 V, 1 Msps
–1
A_DNL
Differential non linearity. VDD = 1.8 V to 3.6 V, 500 ksps
–1
A_THD
Total harmonic distortion
–
–
–
–
FSARINTRE F SAR operating speed without external ref. bypass
2
LSB
VREF = 1.8 V to VDD
2.2
LSB
VREF = 1 V to VDD
–65
dB
100
ksps
–
–
Fin = 10 kHz
12−bit resolution
Table 17. CSD AND IDAC SPECIFICATIONS
Parameter
Min
Typ
Max
Units
Max allowed ripple on power supply, DC to 10
MHz
–
–
±50
mV
VDD > 2 V (with ripple),
25°C TA, Sensitivity =
0.1 pF
VDD_RIPPLE_1.8 Max allowed ripple on power supply, DC to 10
MHz
–
–
±25
mV
VDD > 1.75 V (with ripple),
25°C TA, Parasitic Capaci−
tance (CP) < 20 pF, Sensitivity ≥ 0.4 pF
–
–
4000
mA
Maximum block current for
both IDACs in dynamic
(switching) mode including
comparators, buffer, and
reference generator.
1.2
VDDD − 0.6
V
VDDD − 0.06 or 4.4,
whichever is lower
VDDD − 0.6
V
VDDD − 0.06 or 4.4,
whichever is lower
VDD_RIPPLE
Description
Details / Conditions
ICSD
Maximum block current
VREF
Voltage reference for CSD and Comparator
0.6
VREF_EXT
External Voltage reference for CSD and Comparator
0.6
IDAC1IDD
IDAC1 (7−bits) block current
–
–
1750
mA
IDAC2IDD
IDAC2 (7−bits) block current
–
–
1750
mA
Voltage range of operation
1.8
–
3.6
V
Voltage compliance range of IDAC
0.6
–
VDDD –0.6
V
IDAC1DNL
DNL
–1
–
1
LSB
IDAC1INL
INL
–2
–
2
LSB
IDAC2DNL
DNL
–1
–
1
LSB
IDAC2INL
INL
–2
–
2
LSB
INL is ±5.5 LSB for VDDD
2 V.
VCSD
VCOMPIDAC
SNR
VDDD − 0.06 or 4.4,
whichever is lower
INL is ±5.5 LSB for VDDD
