CAT93C46BXI-T2

CAT93C46B EEPROM Serial 1-Kb Microwire Description The CAT93C46B is a 1−Kb Microwire Serial EEPROM memory device which is configured as either 64 registers of 16 bits (ORG pin at VCC) or 128 registers of 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C46B features a self−timed internal write with auto−clear. On−chip Power−On Reset circuit protects the internal logic against powering up in the wrong state. Features • • • • • • • • • • • • • High Speed Operation: 4 MHz 1.8 V (1.65 V*) to 5.5 V Supply Voltage Range Selectable x8 or x16 Memory Organization Self−Timed Write Cycle with Auto−Clear Sequential Read Software Write Protection Power−up Inadvertant Write Protection Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial and Extended Temperature Ranges 8−pin PDIP, SOIC, TSSOP and 8−pad UDFN and TDFN Packages This Device is Pb−Free, Halogen Free/BFR Free and RoHS Compliant† www.onsemi.com PDIP−8 L SUFFIX CASE 646AA TSSOP−8 Y SUFFIX CASE 948AL SOIC−8 V, W** SUFFIX CASE 751BD SOIC−8 X SUFFIX CASE 751BE UDFN−8 HU4 SUFFIX CASE 517AZ TDFN−8** VP2 SUFFIX CASE 511AK PIN CONFIGURATIONS CS SK DI DO 1 VCC NC NC VCC ORG CS SK GND PDIP (L), SOIC (V, X), TSSOP (Y), UDFN (HU4), TDFN (VP2)** (Top View) 1 ORG GND DO DI SOIC (W)** (Top View) ** Not recommended for new designs. VCC PIN FUNCTION Pin Name ORG CS SK CAT93C46B DO DI GND Figure 1. Functional Symbol CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output VCC Power Supply GND Ground ORG Memory Organization NC *CAT93C46Bxx−xxL (TA = −205C to +855C) †For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Function No Connection Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 organization is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2014 May 2018 − Rev. 4 1 Publication Order Number: CAT93C46B/D CAT93C46B Table 1. ABSOLUTE MAXIMUM RATINGS Parameter Value Units Storage Temperature −65 to +150 °C Voltage on Any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter NEND (Note 3) TDR Endurance Min Units 1,000,000 Program / Erase Cycles 100 Years Data Retention 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Block Mode, VCC = 5 V, 25°C Table 3. D.C. OPERATING CHARACTERISTICS (VCC = +1.8 V to +5.5 V, TA = −40°C to +125°C, VCC = +1.65 V to +5.5 V, TA = −20°C to +85°C unless otherwise specified.) Symbol Parameter ICC1 Supply Current (Write) Write, VCC = 5.0 V ICC2 Supply Current (Read) Read, DO open, fSK = 2 MHz, VCC = 5.0 V ISB1 Standby Current (x8 Mode) VIN = GND or VCC CS = GND, ORG = GND TA = −40°C to +85°C TA = −40°C to +125°C 5 Standby Current (x16 Mode) VIN = GND or VCC CS = GND, ORG = Float or VCC TA = −40°C to +85°C 1 TA = −40°C to +125°C 3 VIN = GND to VCC TA = −40°C to +85°C 1 TA = −40°C to +125°C 2 TA = −40°C to +85°C 1 TA = −40°C to +125°C 2 ISB2 ILI Input Leakage Current ILO Test Conditions Output Leakage Current VOUT = GND to VCC CS = GND Min Max Units 1 mA 500 mA 2 mA mA mA mA VIL1 Input Low Voltage 4.5 V ≤ VCC < 5.5 V −0.1 0.8 V VIH1 Input High Voltage 4.5 V ≤ VCC < 5.5 V 2 VCC + 1 V VIL2 Input Low Voltage 1.65 V ≤ VCC < 4.5 V 0 VCC x 0.2 V VIH2 Input High Voltage 1.65 V ≤ VCC < 4.5 V VCC x 0.7 VCC + 1 V VOL1 Output Low Voltage 4.5 V ≤ VCC < 5.5 V, IOL = 3 mA 0.4 V VOH1 Output High Voltage 4.5 V ≤ VCC < 5.5 V, IOH = −400 mA VOL2 Output Low Voltage 1.65 V ≤ VCC < 4.5 V, IOL = 1 mA VOH2 Output High Voltage 1.65 V ≤ VCC < 4.5 V, IOH = −100 mA 2.4 V 0.2 VCC − 0.2 V V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 4. PIN CAPACITANCE (TA = 25°C, f = 1 MHz, VCC = 5 V) Symbol COUT (Note 4) CIN (Note 4) Test Conditions Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG) Min Typ Max Units VOUT = 0 V 5 pF VIN = 0 V 5 pF 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. www.onsemi.com 2 CAT93C46B Table 5. A.C. CHARACTERISTICS (VCC = +1.8 V to +5.5 V, TA = −40°C to +125°C, VCC = +1.65 V to +5.5 V, TA = −20°C to +85°C unless otherwise specified.) VCC < 3.3 V Symbol Min Parameter Max VCC > 3.3 V TA = −405C to +855C Min Max Units tCSS CS Setup Time 50 50 ns tCSH CS Hold Time 0 0 ns tDIS DI Setup Time 100 50 ns tDIH DI Hold Time 100 50 ns tPD1 Output Delay to 1 0.25 0.1 ms tPD0 Output Delay to 0 0.25 0.1 ms Output Delay to High−Z 100 100 ns 3 3 ms tHZ (Note 5) tEW Program / Erase Cycle Time WRITE, ERASE WRAL, ERAL 5 5 tCSMIN Minimum CS Low Time 0.25 0.1 ms tSKHI Minimum SK High Time 0.25 0.1 ms tSKLOW Minimum SK Low Time 0.25 0.1 ms tSV Output Delay to Status Valid SKMAX Maximum Clock Frequency 0.25 DC 2000 DC 0.1 ms 4000 kHz 5. This parameter is tested initially and after a design or process change that affects the parameter. Table 6. POWER−UP TIMING (Notes 6 and 7) Parameter Symbol Max Units tPUR Power−up to Read Operation 0.1 ms tPUW Power−up to Write Operation 0.1 ms 6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 7. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Table 7. A.C. TEST CONDITIONS Input Rise and Fall Times v 50 ns Input Pulse Voltages 0.4 V to 2.4 V 4.5 V v VCC v 5.5 V 0.8 V, 2.0 V 4.5 V v VCC v 5.5 V 0.2 VCC to 0.7 VCC 1.65 V v VCC v 4.5 V 0.5 VCC 1.65 V v VCC v 4.5 V Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages Output Load Current Source IOLmax/IOHmax; CL = 100 pF www.onsemi.com 3 CAT93C46B Device Operation The CAT93C46B is a 1024−bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C46B can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 9−bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 10−bit instructions control the reading, writing and erase operations of the device. The CAT93C46B operates on a single power supply and will generate on chip the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status during a write operation. The serial communication protocol follows the timing shown in Figure 2. The ready/busy status can be determined after the start of internal write cycle by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the rising edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The Ready/Busy flag can be disabled only in Ready state; no change is allowed in Busy state. The format for all instructions sent to the device is a logical “1” start bit, a 2−bit (or 4−bit) opcode, 6−bit address (an additional bit when organized X8) and for write operations a 16−bit data field (8−bit for X8 organization). Read Upon receiving a READ command (Figure 3) and an address (clocked into the DI pin), the DO pin of the CAT93C46B will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). After the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is proceeded by a dummy zero bit. All sunsequent data words will follow without a dummy zero bit. Erase/Write Enable and Disable The CAT93C46B powers up in the write disable state. Any writing after power−up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C46B write and erase instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. The EWEN and EWDS instructions timing is shown in Figure 4. Table 8. INSTRUCTION SET Address Data Instruction Start Bit Opcode x8 x16 x8 x16 Comments READ 1 10 A6−A0 A5−A0 Read Address AN–A0 ERASE 1 11 A6−A0 A5−A0 Clear Address AN–A0 WRITE 1 01 A6−A0 A5−A0 EWEN 1 00 11XXXXX 11XXXX Write Enable EWDS 1 00 00XXXXX 00XXXX Write Disable ERAL* 1 00 10XXXXX 10XXXX Clear All Addresses WRAL* 1 00 01XXXXX 01XXXX D7−D0 D7−D0 * Not available at VCC < 1.8 V www.onsemi.com 4 D15−D0 D15−D0 Write Address AN–A0 Write All Addresses CAT93C46B tSKHI tSKLOW tCSH SK tDIS tDIH VALID DI VALID tCSS CS tDIS tPD0, tPD1 DO tCSMIN DATA VALID Figure 2. Synchronous Data Timing SK CS AN DI 1 1 AN−1 Don’t Care A0 0 tPD0 HIGH−Z DO Dummy 0 D15 . . . D0 or D7 . . . D0 Address + 1 D15 . . . D0 or D7 . . . D0 Address + 2 D15 . . . D0 or D7 . . . D0 Figure 3. Read Instruction Timing SK STANDBY CS DI 1 0 0 * * ENABLE = 11 DISABLE = 00 Figure 4. EWEN/EWDS Instruction Timing www.onsemi.com 5 Address + n D15 . . . or D7 . . . CAT93C46B Write Erase All After receiving a WRITE command (Figure 5), address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking for auto−clear and data store cycles on the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46B can be determined by selecting the device and polling the DO pin. Since this device features Auto−Clear before write, it is NOT necessary to erase a memory location before it is written into. Upon receiving an ERAL command (Figure 7), the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46B can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN (Figure 8). The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46B can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be de−asserted for a minimum of tCSMIN (Figure 6). The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46B can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. SK tCSMIN CS AN DI STANDBY STATUS VERIFY 1 0 AN−1 A0 DN D0 1 tSV DO tHZ HIGH−Z READY BUSY tEW Figure 5. Write Instruction Timing www.onsemi.com 6 HIGH−Z CAT93C46B SK CS STANDBY STATUS VERIFY AN DI 1 AN−1 tCS MIN A0 1 1 tSV tHZ HIGH−Z DO BUSY READY HIGH−Z tEW Figure 6. Erase Instruction Timing SK CS STATUS VERIFY STANDBY tCS MIN DI 1 0 1 0 0 tSV tHZ HIGH−Z DO BUSY READY HIGH−Z tEW Figure 7. ERAL Instruction Timing SK CS STATUS VERIFY STANDBY tCSMIN DI 1 0 0 0 1 DN D0 tSV tHZ BUSY DO tEW Figure 8. WRAL Instruction Timing www.onsemi.com 7 READY HIGH−Z CAT93C46B Example of Ordering Information Specific Device Marking Package Type Temperature Range CAT93C46BLI−G 93C46P PDIP−8 CAT93C46BLE−G 93C46P CAT93C46BVE−GT3 Device Order Number Lead Finish Shipping I = Industrial (−40°C to +85°C) NiPdAu Tube, 50 Units / Tube PDIP−8 E = Extended (−40°C to +125°C) NiPdAu Tube, 50 Units / Tube 93C46P SOIC−8, JEDEC E = Extended (−40°C to +125°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C46BVI−GT3 93C46P SOIC−8, JEDEC I = Industrial (−40°C to +85°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C46BVI−GT3L 93C46P SOIC−8, JEDEC I = Industrial (−20°C to +85°C) NiPdAu Tape & Reel, 3,000 Units / Reel M0T TDFN−8 I = Industrial (−40°C to +85°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C46BWI−GT3 (Note 8) 93C46P SOIC−8, JEDEC I = Industrial (−40°C to +85°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C46BXI−T2 93C46P SOIC−8, EIAJ I = Industrial (−40°C to +85°C) Matte−Tin Tape & Reel, 2,000 Units / Reel CAT93C46BXE−T2 93C46P SOIC−8, EIAJ E = Extended (−40°C to +125°C) Matte−Tin Tape & Reel, 2,000 Units / Reel CAT93C46BYI−GT3 M46P TSSOP−8 I = Industrial (−40°C to +85°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C46BYI−GT3L M46P TSSOP−8 I = Industrial (−20°C to +85°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C46BYE−GT3 M46P TSSOP−8 E = Extended (−40°C to +125°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C46BHU4I−GT3 M0U UDFN−8 I = Industrial (−40°C to +85°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C46BHU4E−GT3 M0U UDFN−8 E = Extended (−40°C to +125°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C46BVP2I−GT3 (Note 8) 8. Not recommended for new designs. 9. All packages are RoHS−compliant (Lead−free, Halogen−free). 10. The standard lead finish is NiPdAu. 11. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 12. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 13. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device Nomenclature document, TND310/D, available at www.onsemi.com www.onsemi.com 8 CAT93C46B PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL MIN NOM A E1 5.33 A1 0.38 A2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 D 9.02 9.27 10.16 E 7.62 7.87 8.25 E1 6.10 6.35 7.11 e PIN # 1 IDENTIFICATION MAX 2.54 BSC eB 7.87 L 2.92 10.92 3.30 3.80 D TOP VIEW E A2 A A1 c b2 L e eB b SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. www.onsemi.com 9 CAT93C46B PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 MAX 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. www.onsemi.com 10 CAT93C46B PACKAGE DIMENSIONS SOIC−8, 208 mils CASE 751BE−01 ISSUE O SYMBOL MIN NOM 2.03 A E1 E MAX A1 0.05 0.25 b 0.36 0.48 c 0.19 0.25 D 5.13 5.33 E 7.75 8.26 E1 5.13 5.38 1.27 BSC e L 0.51 0.76 θ 0º 8º PIN#1 IDENTIFICATION TOP VIEW D A e b q L A1 SIDE VIEW c END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320. www.onsemi.com 11 CAT93C46B PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O b SYMBOL MIN NOM E1 E MAX 1.20 A A1 0.05 0.15 A2 0.80 b 0.19 0.30 c 0.09 0.20 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 0.90 e 0.65 BSC L 1.00 REF L1 0.50 θ 0º 0.60 1.05 0.75 8º e TOP VIEW D A2 c q1 A A1 L1 SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. www.onsemi.com 12 CAT93C46B PACKAGE DIMENSIONS UDFN8, 2x3 EXTENDED PAD CASE 517AZ−01 ISSUE O D b A e L DAP SIZE 1.8 x 1.8 E2 E PIN #1 IDENTIFICATION A1 PIN #1 INDEX AREA D2 TOP VIEW SIDE VIEW SYMBOL MIN NOM MAX A 0.45 0.50 0.55 A1 0.00 0.02 0.05 A3 b 0.127 REF 0.20 0.25 0.30 D 1.95 2.00 2.05 D2 1.35 1.40 1.45 E 2.95 3.00 3.05 E2 1.25 1.30 1.35 e L BOTTOM VIEW DETAIL A 0.065 REF A3 A FRONT VIEW 0.50 REF 0.25 0.30 0.35 A3 Notes: (1) All dimensions are in millimeters. (2) Refer JEDEC MO-236/MO-252. 0.0 - 0.05 DETAIL A www.onsemi.com 13 0.065 REF Copper Exposed CAT93C46B PACKAGE DIMENSIONS TDFN8, 2x3 CASE 511AK−01 ISSUE A D e A b E2 E PIN#1 IDENTIFICATION A1 PIN#1 INDEX AREA D2 TOP VIEW SIDE VIEW SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A2 0.45 0.55 0.65 A3 A2 A3 0.20 0.25 0.30 D 1.90 2.00 2.10 D2 1.30 1.40 1.50 E 2.90 3.00 3.10 E2 1.20 1.30 1.40 L BOTTOM VIEW 0.20 REF b e FRONT VIEW 0.50 TYP 0.20 0.30 L 0.40 Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-229. www.onsemi.com 14 CAT93C46B ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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