CS51021A, CS51022A,
CS51023A, CS51024A
Enhanced Current Mode
PWM Controller
The CS51021A/2A/3A/4A Fixed Frequency PWM Current Mode
Controller family provides all necessary features required for AC−DC
or DC−DC primary side control. Several features are included
eliminating the additional components needed to implement them
externally. In addition to low startup current (75 mA) and high
frequency operation capability, the CS51021A/2A/3A/4A family
includes overvoltage and undervoltage monitoring, externally
programmable dual threshold overcurrent protection, current sense
leading edge blanking, current slope compensation, accurate duty cycle
control and an externally available 5.0 V reference. The CS51021A
and CS51023A feature bidirectional synchronization capability, while
the CS51022A and CS51024A offer a sleep mode with 100 mA
maximum IC current consumption. The CS51021A/2A/3A/4A family
is available in a 16 lead narrow body SOIC package.
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SOIC−16
D SUFFIX
CASE 751B
16
1
TSSOP−16
DTB SUFFIX
CASE 948F
16
1
Device
Sleep/Synch
VCC Start/Stop
CS51021A
Synch
8.25 V/7.7 V
CS51022A
Sleep
8.25 V/7.7 V
CS51023A
Synch
13 V/7.7 V
CS51024A
Sleep
13 V/7.7 V
1
GATE
ISENSE
SLEEP or SYNC
SLOPE
UV
OV
RTCT
ISET
CS5102xAG
AWLYWW
1
16
VC
PGND
VCC
VREF
LGND
SS
COMP
VFB
16
CS51
022A
ALYW G
G
Features
• 75 mA Max. Startup Current
• Fixed Frequency Current Mode Control
• 1.0 MHz Switching Frequency
• Undervoltage Protection Monitor
• Overvoltage Protection Monitor with Programmable Hysteresis
• Programmable Dual Threshold Overcurrent Protection with
Delayed Restart
• Programmable Soft Start
• Accurate Maximum Duty Cycle Limit
• Programmable Slope Compensation
• Leading Edge Current Sense Blanking
• 1.0 A Sink/Source Gate Drive
• Bidirectional Synchronization (CS51021A/3A)
• 50 ns PWM Propagation Delay
• 100 mA Max Sleep Current (CS51022A/4A)
• Pb−Free Packages are Available*
PIN CONNECTIONS AND
MARKING DIAGRAMS
x
A
WL, L
Y
WW, W
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 8
1
Publication Order Number:
CS51021A/D
CS51021A, CS51022A, CS51023A, CS51024A
100
VIN
(36 V to 72 V)
51 k
PGND
SYNC/SLEEP
1.0 mF
BAS21
18 V
22 mF
11 V
100:1
FZT688
24.3 k,
1.0%
4700 pF
22 k
10 k
51 k
330 pF
VC
VREF
COMP
VFB
RTCT
SYNC/
SLEEP
CSS
LGND
CS51021A/2A
10
0.01 mF
VCC
UV
OV
ISET
SLOPE
GATE
ISENSE
PGND
0.01 mF
2:5
200 k,
1.0%
10 k
4:1
VOUT
(5 V/5 A)
2.49 k,
1.0%
10
BA521
100 mF 100 mF
680 pF
IRF6345
6.98 k,
1.0%
6.98 k,
1.0%
470 pF
SGND
100
62
100 p
0.1 mF
5.1 k
TL431
2.0 k, 1.0%
1000 pF
180
1.0 k
2.0 k,
1.0%
MOC81025
10 K
1.0 K
Figure 1. Typical Application Diagram, 36−72 V to 5.0 V, 5.0 A DC−DC Converter
MAXIMUM RATINGS*
Rating
Value
Unit
Power Supply Voltage, VCC
−0.3, 20
V
Driver Supply Voltage, VC
−0.3, 20
V
0.25 to VREF
V
Peak GATE Output Current
1.0
A
Steady State Output Current
±0.2
A
Operating Junction Temperature, TJ
150
°C
−65 to +150
°C
2.0
kV
230 peak
°C
SYNC, SLEEP, RTCT, SOFT−START, VFB, SLOPE, ISENSE, UV, OV, ISET (Logic Pins)
Storage Temperature Range, TS
ESD (Human Body Model)
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1)
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
*The maximum package power dissipation must be observed.
1. 60 second maximum above 183°C.
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2
CS51021A, CS51022A, CS51023A, CS51024A
ELECTRICAL CHARACTERISTICS (Unless otherwise stated, specifications apply for −40°C < TA < 85°C, −40°C < TJ < 150°C,
3.0 V < VC < 20 V, 8.2 V < VCC < 20 V, RT = 12 kW, CT = 390 pF)
Characteristic
Test Conditions
Min
Typ
Max
Unit
START Threshold (CS51021A/2A)
−
7.95
8.25
8.8
V
START Threshold (CS51023A/4A)
−
12.4
13
13.4
V
STOP Threshold
−
7.4
7.7
8.2
V
Hysteresis (CS51021A/2A)
−
0.50
0.75
1.00
V
Hysteresis (CS51023A/4A)
−
4.0
5.0
6.0
V
Under Voltage Lockout
ICC @ Startup (CS51021A/2A)
VCC < UVSTART Threshold
−
40
75
mA
ICC @ Startup (CS51023A/4A)
VCC < UVSTART Threshold
−
45
75
mA
ICC Operating (CS51021A/3A)
−
−
7.0
9.0
mA
ICC Operating (CS51022A/4A)
−
−
6.0
8.0
mA
−
7.0
12
mA
ICC Operating
Includes 1.0 nF Load
Voltage Reference
Initial Accuracy
TA = 25°C, IREF = 2.0 mA, VCC = 14 V, (Note 2)
4.95
5.0
5.05
V
Total Accuracy
1.0 mA < IREF < 10 mA
4.9
5.0
5.15
V
Line Regulation
8.2 V < VCC < 18 V, IREF = 2.0 mA
−
6.0
20
mV
Load Regulation
1.0 mA < IREF < 10 mA
−
6.0
15
mV
NOISE Voltage
(Note 2)
−
50
−
mV
OP Life Shift
T = 1000 Hours, (Note 2)
−
4.0
20
mV
FAULT Voltage
Force VREF
0.90 × VREF
0.93 × VREF
0.95 × VREF
V
OK Voltage
Force VREF
0.94 × VREF
0.96 × VREF
0.985 × VREF
V
OK Hysteresis
Force VREF
75
165
250
mV
Current Limit
Force VREF
−20
−
−
mA
Error Amplifier
Initial Accuracy
TA = 25°C, IREF = 2.0 mA, VCC = 14 V,
VFB = COMP, (Note 2)
2.465
2.515
2.565
V
Reference Voltage
VFB = COMP
2.440
2.515
2.590
V
VFB Leakage Current
VFB = 0 V
−
−0.2
−2.0
mA
Open Loop Gain
1.4 V < COMP < 4.0 V, (Note 2)
60
90
−
dB
Unity Gain Bandwidth
(Note 2)
1.5
2.5
−
MHz
COMP Sink Current
COMP = 1.5 V, VFB = 2.7 V
2.0
6.0
−
mA
COMP Source Current
COMP = 1.5 V, VFB = 2.3 V
−0.2
−0.5
−
mA
COMP High Voltage
VFB = 2.3 V
4.35
4.8
5.0
V
COMP Low Voltage
VFB = 2.7 V
0.4
0.8
1.2
V
PS Ripple Rejection
FREQ = 120 Hz, (Note 2)
60
85
−
dB
SS Clamp, VCOMP
VSS = 2.5 V, VFB = 0 V, ISET = 2.0 V
2.4
2.5
2.6
V
ILIM(SET) Clamp
(Note 2)
0.95
1.0
1.15
V
2. Guaranteed by design, not 100% tested in production.
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3
CS51021A, CS51022A, CS51023A, CS51024A
ELECTRICAL CHARACTERISTICS (Unless otherwise stated, specifications apply for −40°C < TA < 85°C, −40°C < TJ < 150°C,
3.0 V < VC < 20 V, 8.2 V < VCC < 20 V, RT = 12 kW, CT = 390 pF)
Characteristic
Test Conditions
Min
Typ
Max
Unit
230
255
280
kHz
Oscillator
Accuracy
RT = 12 k, CT = 390 pF
Voltage Stability
Delta Frequency 8.2 V < VCC < 20 V
−
2.0
3.0
%
Temperature Stability
TMIN < TA < TMAX, (Note 3)
−
8.0
−
%
Min Charge & Discharge Time
(Note 3)
0.333
−
−
ms
Duty Cycle Accuracy
RT = 12 k, CT = 390 pF
70
77
83
%
Peak Voltage
(Note 3)
−
3.0
−
V
Valley Voltage
(Note 3)
−
1.5
−
V
Valley Clamp Voltage
10 k Resistor to ground on RTCT
1.2
1.4
1.6
V
0.8
1.0
1.2
mA
0.925
1.0
1.075
mA
Discharge Current
Discharge Current
−
TA = 25°C, Note 3
Synchronization (CS51021A/3A)
Input Threshold
−
1.0
1.5
2.7
V
Output Pulsewidth
−
160
260
400
ns
Output High Voltage
ISYNC = 100 mA
3.5
4.3
4.8
V
Input Resistance
(Note 3)
35
70
140
kW
Drive Delay
SYNC to GATE RESET
80
120
150
ns
Output Drive Current
1.0 k Load
1.25
2.0
3.5
mA
SLEEP Input Threshold
Active High
1.0
1.5
2.7
V
SLEEP Input Current
VSLEEP = 4.0 V
11
25
46
mA
ICC @ SLEEP
VCC ≤ 15 V
−
50
100
mA
HIGH Voltage
Measure VC − GATE, VC = 10 V, 150 mA Load
−
1.5
2.2
V
LOW Voltage
Measure GATE − PGND, 150 mA SINK
−
1.2
1.5
V
HIGH Voltage Clamp
VC = 20 V, 1.0 nF
11
13.5
16
V
LOW Voltage Clamp
Measured at 10 mA Output Current
−
0.6
0.8
V
Peak Current
VC = 20 V, 1.0 nF, (Note 3)
−
1.0
−
A
UVL Leakage
VC = 20 V measured at 0 V
−
−1.0
−50
mA
RISE Time
Load = 1.0 nF, 1.0 V < GATE < 9.0 V,
VC = 20 V, TA = 25°C
−
60
100
ns
FALL Time
Load = 1.0 nF, 9.0 V > GATE > 1 .0 V,
VC = 20 V
−
15
40
ns
−63
−53
−43
mA
0.095
0.100
0.105
V/V
−
0.1
0.2
V
SLEEP (CS51022A/4A)
GATE Driver
SLOPE Compensation
Charge Current
SLOPE = 2.0 V
COMP Gain
Fraction of slope voltage added to ISENSE,
(Note 3)
Discharge Voltage
SYNC = 0 V
3. Guaranteed by design, not 100% tested in production.
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4
CS51021A, CS51022A, CS51023A, CS51024A
ELECTRICAL CHARACTERISTICS (Unless otherwise stated, specifications apply for −40°C < TA < 85°C, −40°C < TJ < 150°C,
3.0 V < VC < 20 V, 8.2 V < VCC < 20 V, RT = 12 kW, CT = 390 pF)
Characteristic
Test Conditions
Min
Typ
Max
Unit
0.09
0.10
0.11
V
−
55
160
ns
1.8
2.0
2.2
V
Current Sense
OFFSET Voltage
(Note 4)
Blanking Time
−
Blanking Disable Voltage
Adjust VFB
Second Current Threshold Gain
−
1.21
1.33
1.45
V/V
ISENSE Input Resistance
−
−
5.0
−
kW
30
70
110
ns
0.78
0.80
0.82
V/V
Minimum On Time
GATE High to Low
Gain
(Note 4)
OV & UV Voltage Monitors
OV Monitor Threshold
−
2.4
2.5
2.6
V
OV Hysteresis Current
−
−10
−12.5
−15
mA
UV Monitor Threshold
−
1.38
1.45
1.52
V
UV Monitor Hysteresis
−
25
75
100
mV
SOFT START (SS)
Charge Current
SS = 2.0 V
−70
−55
−40
mA
Discharge Current
SS = 2.0 V
250
1000
−
mA
Charge Voltage, VSS
−
4.4
4.7
5.0
V
Discharge Voltage, VSS
−
0.25
0.27
0.30
V
4. Guaranteed by design, not 100% tested in production.
PACKAGE PIN DESCRIPTION
PIN #
PIN SYMBOL
FUNCTION
16 Lead SO Narrow
1
GATE
External power switch driver with 1.0 A peak capability.
2
ISENSE
Current sense amplifier input.
3
SYNC (CS51021A/3A)
Bi−directional synchronization. Locks to the highest frequency.
3
SLEEP (CS51022A/4A)
Active high chip disable. In sleep mode, VREF and GATE are turned off.
4
SLOPE
5
UV
Undervoltage protection monitor.
6
OV
Overvoltage protection monitor.
7
RTCT
Timing resistor RT and capacitor CT determine oscillator frequency and maximum duty cycle, DMAX.
8
ISET
Voltage at this pin sets pulse−by−pulse overcurrent threshold, and second threshold (1.33 times
higher) with Soft Start retrigger (hiccup mode).
9
VFB
Feedback voltage input. Connected to the error amplifier inverting input.
10
COMP
11
SS
12
LGND
Logic ground.
13
VREF
5.0 V reference voltage output.
14
VCC
Logic supply voltage.
15
PGND
16
VC
Additional slope to the current sense signal. Internal current source charges the external capacitor.
Error amplifier output. Frequency compensation network is usually connected between COMP and
VFB pins.
Charging external capacitor restricts error amplifier output voltage during the start or fault
conditions (hiccup).
Output power stage ground connection.
Output power stage supply voltage.
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5
CS51021A, CS51022A, CS51023A, CS51024A
VCC
−
LGND
+
VREF
VCC_OK
+
Start
Stop
−
VREF = 5.0 V
VREF_OK
−
+
+
SLEEP
4.75 V
200 ns
−
VC
4.3 V
SYNC
OSC
S
RTCT
+
−
D2
G1
+
+
PGND
VREF
PWM
Comp
D1
10 k
+
−
VFB
Monitor
−
R
−
E/A
55 mA
−
SS
SS
Monitor
+
+
ZD1
D3
20 k
−
53 mA
D4
ISET
Clamp
COMP
VREF
GATE
13.5 V
−
VFB
G2
F1
SS
Clamp
+
2.5 V
−
Q
+
G4
2.0 V
+
−
4.7 V
DISABLE
0.1 V
SLOPE
0.1
ISENSE
Σ
−
55 ns
Blank
+
VISENSE
0.8
Q2
+
2nd
ISET
Threshold
1.33
−
VREF
12.5 mA
+
OV
−
Discharge
Latch
−
OV
Monitor
UV
UV
Monitor
−
+
G3
FAULT
+
2.5 V
1.45 V
Figure 2. Block Diagram
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6
+
−
CS51021A, CS51022A, CS51023A, CS51024A
CIRCUIT DESCRIPTION
Current Sense and Protection
200 ns
The current is monitored at the ISENSE pin. The
CS51021A/2A/3A/4A has leading edge blanking circuitry
that ignores the first 55 ns of each switching period.
Blanking is disabled when VFB is less than 2.0 V so that the
minimum on−time of the controller does not have an
additional 55 ns of delay time during fault conditions. For
the remaining portion of the switching period, the current
sense signal, combined with a fraction of the slope
compensation voltage, is applied to the positive input of the
PWM comparator where it is compared with the divided by
three error amplifier output voltage. The pulse−by−pulse
overcurrent protection threshold is set by the voltage at the
ISET pin. This voltage is passed through the ISET Clamp and
appears at the non−inverting input of the PWM comparator,
limiting its dynamic range according to the following
formula:
4.3 V
SYNC
RTCT
0V
TCH
TDIS
VSLOPE
SLOP
E
0V
IS
0V
IS + 0.1 SLOPE
IS
0V
VCOMP
55 ns
Blanking
PWM COMP
Overcurrent Threshold + 0.8 VI(SENSE)
) 0.1 V ) 0.1 VSLOPE
GATE
0V
where
VI(SENSE) is voltage at the ISENSE pin.
VDS
VIN
and
VSLOPE is voltage at the SLOPE pin.
0V
During extreme overcurrent or short circuit conditions,
the slope of the current sense signal will become much
steeper than during normal operation. Due to loop
propagation delay, the sensed signal will overshoot the
pulse−by−pulse threshold eventually reaching the second
overcurrent protection threshold which is 1.33 times higher
than the first threshold and is described by the following
equation:
Figure 3. Typical Waveforms
THEORY OF OPERATION
Powering the IC
The IC has two supply and two ground pins. VC and
PGND pins provide high speed power drive for the external
power switch. VCC and LGND pins power the control
portion of the IC. The internal logic monitors the supply
voltage, VCC. During abnormal operating conditions, the
output is held low. The CS51021A/2A/3A/4A requires only
75 mA of startup current.
2nd Threshold + 1.33
VI(SET)
Exceeding the second threshold will reset the Soft Start
capacitor CSS and reinitiate the Soft Start sequence,
repeating for as long as the fault condition persists.
Soft Start
Voltage Feedback
During power up, when the output filter capacitor is
discharged and the output voltage is low, the voltage across
the Soft Start capacitor (VSS) controls the duty cycle. An
internal current source of 55 mA charges CSS. The maximum
error amplifier output voltage is clamped by the SS Clamp.
When the Soft Start capacitor voltage exceeds the error
amplifier output voltage, the feedback loop takes over the
duty cycle control. The Soft Start time can be estimated with
the following formula:
The output voltage is monitored via the VFB pin and is
compared with the internal 2.5 V reference. The error
amplifier output minus one diode drop is divided by 3 and
connected to the negative input of the PWM comparator.
The positive input of the PWM comparator is connected to
the modified current sense signal. The oscillator turns the
external power switch on at the beginning of each cycle.
When current sense ramp voltage exceeds the reference side
of PWM comparator, the output stage latches off. It is turned
on again at the beginning of the next oscillator cycle.
tSS + 9
10 4
CSS
The Soft Start voltage, VSS, charges and discharges
between 0.25 V and 4.7 V.
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7
CS51021A, CS51022A, CS51023A, CS51024A
Slope Compensation
where R3 is a resistor connected from the OV pin to ground.
When the monitored voltage is low and the UV pin is less
than 1.45 V, GATE shuts down. The UV pin has fixed 75 mV
hysteresis.
Both OV and UV conditions are latched until the Soft Start
capacitor is discharged. This way, every time a fault
condition is detected the controller goes through the power
up sequence.
DC−DC converters with current mode control require a
current sense signal with slope compensation to avoid
instability at duty cycles greater than 50%. Slope capacitor
CS is charged by an internal 53 mA current source and is
discharged during the oscillator discharge time. The slope
compensation voltage is divided by 10 and is added to the
current sense voltage, VI(SENSE). The signal applied to the
input of the PWM comparator is a combination of these two
voltages. The slope compensation, dVSLOPE/dt, is
calculated using the following formula:
dVSLOPE
+ 0.1
dt
R1
R3
VIN
53 mA
CS
VUV
It should be noted that internal capacitance of the IC will
cause an error when determining slope compensation
capacitance CS. This error is typically small for large values
of CS, but increases as CS becomes small and comparable to
the internal capacitance. The effect is apparent as a reduction
in charging current due to the need to charge the internal
capacitance in parallel with CS.Figure 4 shows a typical
curve indicating this decrease in available charging current.
VOV
Figure 5. UV/OV Monitor Divider
To calculate the OV?UV resistor divider :
1. Solve for R3, based on OV hysteresis requirements.
R3 +
VOV(HYST) 2.5 V
VMAX 12.5 mA
where VOV(HYST) is the desired amount of
overvoltage hysteresis, and VMAX is the input voltage
at which the supply will shut down.
60
55
Charging Current (mA)
R2
50
2. Find the total impedance of the divider.
V
R3
RTOT + R1 ) R2 ) R3 + MAX
2.5
45
40
3. Determine the value of R2 from the UV threshold
conditions.
35
30
R2 +
25
where VMIN is the UV voltage at which the supply
will shut down.
20
10
100
1000
Compensation Cap (pF)
4. Calculate R1.
Figure 4. The Slope Compensation Pin Charge
Current Reduces When a Small Capacitor Is Used.
R1 + RTOT * R2 * R3
5. The undervoltage hysteresis is given by :
V
0.075
VUV(HYST) + MIN
1.45
Undervoltage (UV) and Overvoltage (OV) Monitor
Two independent comparators monitor OV and UV
conditions. A string of three resistors is connected in series
between the monitored voltage (usually the input voltage)
and ground (see Figure 5). When voltage at the OV pin
exceeds 2.5 V, an overvoltage condition is detected and
GATE shuts down. An internal 12.5 mA current source turns
on and feeds current into the external resistor, R3, creating
a hysteresis determined by the value of this resistor (the
higher the value, the greater the hysteresis). The hysteresis
voltage of the OV monitor is determined by the following
formula:
VOV(HYST) + 12.5 mA
1.45 RTOT
* R3
VMIN
VREF Monitor
The 5.0 V reference voltage is internally monitored to
ensure that it remains within specifications. The monitor,
which outputs a fault, can be tripped by two methods:
• If the reference voltage drops below 4.75 V
• If VCC falls below the STOP threshold
As indicated in the block diagram, any fault causes the
output to stop switching and begins the discharge of the Soft
Start capacitor CSS.
R3
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8
CS51021A, CS51022A, CS51023A, CS51024A
Synchronization
Oscillator and Duty Cycle Limit
A bi−directional synchronization is provided to synchronize
several controllers. When SYNC pins are connected together,
the converters will lock to the highest switching frequency. The
fastest controller becomes the master, producing a 4.3 V, 200
ns pulse train. Only one, the highest frequency SYNC signal,
will appear on the SYNC line.
The switching frequency is set by RT and CT connected to
the RTCT pin. CT charges and discharges between 3.0 V and
1.5 V.
The maximum duty cycle is set by the ratio of the on time,
tON, and the whole period, T = tON + tOFF. Because the timing
capacitor’s discharge current is trimmed, the maximum duty
cycle is well defined. It is determined by the ratio between the
timing resistor RT and the timing capacitor CT. Refer to figures
6 and 7 to select appropriate values for RT and CT.
Sleep
The sleep input is an active high input. The CS51022A/4A
is placed in sleep mode when SLEEP is driven high. In sleep
mode, the controller and MOSFET are turned off. Connect
to GND for normal operation. The sleep mode operates at
VCC ≤ 15 V.
fSW +
2500
100
7
1. CT = 47 pF
2. CT = 100 pF
3. CT = 150 pF
4. CT = 220 pF
5. CT = 390 pF
6. CT = 470 pF
7. CT = 560 pF
8. CT = 680 pF
1
1500
2
1000
3
8
6
90
Duty Cycle (%)
2000
Frequency (kHz)
1 ; T
SW + tCH ) tDIS
TSW
80
5
4
1. CT = 47 pF
2. CT = 100 pF
3. CT = 150 pF
4. CT = 220 pF
5. CT = 390 pF
6. CT = 470 pF
7. CT = 560 pF
8. CT = 680 pF
3
70
2
1
60
4
500
5
8
0
5
50
6
7
10
40
15
20
25
30
35
40
45
50
5
10
15
20
25
30
35
40
45
50
RT (kW)
RT (kW)
Figure 6. Frequency vs. RT for Discrete
Capacitor Values
Figure 7. Duty Cycle vs. RT for Discrete
Capacitor Values
55
ORDERING INFORMATION
Device
Package
CS51021AED16
CS51021AEDR16
CS51021AEDR16G
Shipping †
48 Units / Rail
SOIC−16
SOIC−16
(Pb−Free)
2500 Tape & Reel
CS51022ADBG
TSSOP−16*
48 Units / Rail
CS51022ADBR2G
TSSOP−16*
2500 Tape & Reel
CS51022AED16
CS51022AEDR16
CS51022AEDR16G
48 Units / Rail
SOIC−16
SOIC−16
(Pb−Free)
CS51023AED16
CS51023AEDR16
CS51023AEDR16G
2500 Tape & Reel
48 Units / Rail
SOIC−16
SOIC−16
(Pb−Free)
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
9
CS51021A, CS51022A, CS51023A, CS51024A
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
16
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
S
PACKAGE THERMAL DATA
Parameter
SOIC−16
Unit
RqJC
Typical
28
°C/W
RqJA
Typical
115
°C/W
http://onsemi.com
10
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
CS51021A, CS51022A, CS51023A, CS51024A
TSSOP−16
CASE 948F−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
S
V
S
S
2X
L/2
16
9
B
−U−
L
PIN 1
IDENT.
8
1
0.15 (0.006) T U
S
A
−V−
N
J1
K
0.25 (0.010)
K1
M
ÉÉ
ÇÇÇ
ÇÇÇ
ÉÉ
ÇÇÇ
N
F
SECTION N−N
J
DETAIL E
PLANE
H
D
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
−W−
C
0.10 (0.004)
−T− SEATING
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
DETAIL E
G
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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11
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