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EFR32MG14 Mighty Gecko Multi-Protocol
Wireless SoC Family Data Sheet
D
The Mighty Gecko multi-protocol family of SoCs is part of the
Wireless Gecko portfolio. Mighty Gecko SoCs are ideal for enabling energy-friendly multi-protocol, multi-band networking for IoT
devices.
KEY FEATURES
N
ew
• 32-bit ARM® Cortex®-M4 core with 40
MHz maximum operating frequency
• 256 kB of flash and 32 kB of RAM
The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup
times, a scalable power amplifier, and no-compromise MCU features.
Mighty Gecko applications include:
Core / Memory
ARM CortexTM M4 processor
with DSP extensions, FPU and MPU
RAM Memory
LDMA Controller
BALUN
I
LNA
RF Frontend
Q
FRC
To Sub GHz
receive I/Q
mixers and PA
AGC
Frequency
Synthesizer
MOD
To 2.4 GHz receive
I/Q mixers and PA
Voltage
Regulator
Voltage Monitor
CRYPTO
Auxiliary H-F RC
Oscillator
L-F
RC Oscillator
DC-DC
Converter
Power-On Reset
CRC
L-F Crystal
Oscillator
Ultra L-F RC
Oscillator
Brown-Out
Detector
SMU
I/O Ports
Timers and Triggers
USART
External
Interrupts
Timer/Counter
Protocol Timer
Low Energy
UARTTM
General
Purpose I/O
Low Energy
Timer
Low Energy
Sensor Interface
I2C
Pin Reset
Pulse Counter
Watchdog Timer
Pin Wakeup
Real Time
Counter and
Calendar
Cryotimer
IFADC
Q
2.4 GHz
PA
DEMOD
PGA
Other
H-F
RC Oscillator
Analog I/F
ADC
Analog
Comparator
IDAC
RAC
N
ot
RFSENSE
PA
Energy Management
H-F Crystal
Oscillator
Serial
Interfaces
CRC
R
I
LNA
RF Frontend
• Robust peripheral set and up to 31 GPIO
32-bit bus
BUFC
ec
Sub GHz
• Integrated PA with up to 19 dBm (2.4
GHz) or 20 dBm (Sub-GHz) tx power
Peripheral Reflex System
Radio Transceiver
RFSENSE
• Autonomous Hardware Crypto Accelerator
• Integrated balun for 2.4 GHz
Clock Management
Flash Program
Memory
om
Debug Interface
• 12-channel Peripheral Reflex System
enabling autonomous interaction of MCU
peripherals
fo
r
IoT Multi-Protocol Devices
Connected Home
Lighting
Health and Wellness
Metering
Home and Building Automation and Security
m
en
de
d
•
•
•
•
•
•
• Pin-compatible across EFR32MG families
(exceptions apply for 5V-tolerant pins)
VDAC
To Sub GHz
and 2.4 GHz PA
Op-Amp
Lowest power mode with peripheral operational:
EM0—Active
EM1—Sleep
silabs.com | Building a more connected world.
EM2—Deep Sleep
EM3—Stop
EM4—Hibernate
EM4—Shutoff
Rev. 1.4
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Feature List
1. Feature List
The EFR32MG14 highlighted features are listed below.
N
ew
D
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• Wide selection of MCU peripherals
• 12-bit 1 Msps SAR Analog to Digital Converter (ADC)
• 2 × Analog Comparator (ACMP)
• 2 × Digital to Analog Converter (VDAC)
• 2 × Operational Amplifier (Opamp)
• Digital to Analog Current Converter (IDAC)
• Low-Energy Sensor Interface (LESENSE)
• Up to 31 pins connected to analog channels (APORT)
shared between analog peripherals
• Up to 31 General Purpose I/O pins with output state retention and asynchronous interrupts
• 8 Channel DMA Controller
• 12 Channel Peripheral Reflex System (PRS)
• 2 × 16-bit Timer/Counter
• 3 or 4 Compare/Capture/PWM channels
• 1 × 32-bit Timer/Counter
• 3 Compare/Capture/PWM channels
• 32-bit Real Time Counter and Calendar
• 16-bit Low Energy Timer for waveform generation
• 32-bit Ultra Low Energy Timer/Counter for periodic wake-up
from any Energy Mode
• 16-bit Pulse Counter with asynchronous operation
• 2 × Watchdog Timer with dedicated RC oscillator
• 2 × Universal Synchronous/Asynchronous Receiver/Transmitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I2S)
• Low Energy UART (LEUART™)
om
m
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fo
r
• Low Power Wireless System-on-Chip
• High Performance 32-bit 40 MHz ARM Cortex®-M4 with
DSP instruction and floating-point unit for efficient signal
processing
• 256 kB flash program memory
• 32 kB RAM data memory
• 2.4 GHz and Sub-GHz radio operation
• Transmit power:
• 2.4 GHz radio: Up to 19 dBm
• Sub-GHz radio: Up to 20 dBm
• Low Energy Consumption
• 10.2 mA RX current at 250 kbps, DSSS-OQPSK, 2.4 GHz
• 8.8 mA RX current at 1 Mbps, GFSK, 2.4 GHz
• 8.4 mA RX current at 38.4 kbps, GFSK, 169 MHz
• 8.5 mA TX current at 0 dBm output power at 2.4 GHz
• 35.3 mA TX current at 14 dBm output power at 868 MHz
• 67 μA/MHz in Active Mode (EM0)
• 1.3 μA EM2 DeepSleep current (16 kB RAM retention and
RTCC running from LFRCO)
• High Receiver Performance
• -93.8 dBm sensitivity at 1 Mbit/s GFSK, 2.4 GHz
• -103.3 dBm sensitivity at 250 kbps DSSS-OQPSK, 2.4 GHz
• -126.2 dBm sensitivity at 600 bps, GFSK, 915 MHz
• -120.6 dBm sensitivity at 2.4 kbps, GFSK, 868 MHz
• -109.9 dBm sensitivity at 4.8 kbps, OOK, 433 MHz
• -112.2 dBm sensitivity at 38.4 kbps, GFSK, 169 MHz
• Supported Modulation Formats
• 2/4 (G)FSK with fully configurable shaping
• BPSK / DBPSK TX
• OOK / ASK
• Shaped OQPSK / (G)MSK
• Configurable DSSS and FEC
• Supported Protocols
• Zigbee
• Thread
• Bluetooth® Low Energy (Bluetooth 5)
•
•
•
N
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• Proprietary Protocols
• Wireless M-Bus
• Selected IEEE 802.15.4g SUN-FSK PHYs
• Low Power Wide Area Networks
• Suitable for Systems Targeting Compliance With:
• FCC Part 90.210 Mask D, FCC part 15.247, 15.231, 15.249
• ETSI Category I Operation, EN 300 220, EN 300 328
• ARIB T-108, T-96
• China regulatory
•
• I2C interface with SMBus support and address recognition
in EM3 Stop
Wide Operating Range
• 1.8 V to 3.8 V single power supply
• Integrated DC-DC, down to 1.8 V output with up to 200 mA
load current for system
• Standard (-40 °C to 85 °C) and Extended (-40 °C to 125 °C)
temperature grades available
Support for Internet Security
• General Purpose CRC
• Random Number Generator
• Hardware Cryptographic Acceleration for AES 128/256,
SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC
QFN32 5x5 mm Package
QFN48 7x7 mm Package
silabs.com | Building a more connected world.
Rev. 1.4 | 2
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Ordering Information
2. Ordering Information
Table 2.1. Ordering Information
EFR32MG14P733F256GM48-B
Frequency Band
@ Max TX Power
Flash
(kB)
RAM
(kB)
GPIO
Package
Temp Range
Bluetooth LE
2.4 GHz @ 19 dBm
256
32
28
QFN48
-40 to +85°C
Zigbee
Sub-GHz @ 20 dBm
256
32
28
QFN48
-40 to +125°C
Thread
EFR32MG14P733F256IM48-B
Bluetooth LE
2.4 GHz @ 19 dBm
Zigbee
Sub-GHz @ 20 dBm
D
Proprietary
EFR32MG14P732F256GM48-B
Bluetooth LE
2.4 GHz @ 19 dBm
32
31
QFN48
-40 to +85°C
256
32
31
QFN48
-40 to +125°C
2.4 GHz @ 19 dBm
256
32
16
QFN32
-40 to +85°C
2.4 GHz @ 19 dBm
256
32
16
QFN32
-40 to +125°C
2.4 GHz @ 10 dBm
256
32
31
QFN48
-40 to +85°C
2.4 GHz @ 10 dBm
256
32
16
QFN32
-40 to +85°C
Zigbee
EFR32MG14P732F256IM48-B
Bluetooth LE
256
fo
r
Thread
Proprietary
N
ew
Thread
Proprietary
es
ig
ns
Ordering Code
Protocol
Stack
2.4 GHz @ 19 dBm
m
en
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Zigbee
Thread
Proprietary
EFR32MG14P732F256GM32-B
Bluetooth LE
Zigbee
Thread
om
Proprietary
EFR32MG14P732F256IM32-B
Bluetooth LE
ec
Zigbee
N
ot
R
EFR32MG14P632F256GM48-B
EFR32MG14P632F256GM32-B
Thread
Proprietary
Bluetooth LE
Zigbee
Thread
Proprietary
Bluetooth LE
Zigbee
Thread
Proprietary
silabs.com | Building a more connected world.
Rev. 1.4 | 3
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Ordering Information
EFR32 X G 1 4 P 733 F 256 G M 48 – A R
Tape and Reel (Optional)
es
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ns
Revision
Pin Count
Package – M (QFN)
Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C)
Flash Memory Size in kB
Memory Type (Flash)
D
Feature Set Code – r2r1r0
r2: Reserved
r1: RF Type – 3 (TRX), 2 (RX), 1 (TX)
r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band)
N
ew
Performance Grade – P (Performance), B (Basic), V (Value)
Device Configuration
Series
Gecko
Family – M (Mighty), B (Blue), F (Flex)
fo
r
Wireless Gecko 32-bit
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Figure 2.1. Ordering Code Key
silabs.com | Building a more connected world.
Rev. 1.4 | 4
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
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3.2 Radio . . . . . . . . . . . .
3.2.1 Antenna Interface . . . . . .
3.2.2 Fractional-N Frequency Synthesizer
3.2.3 Receiver Architecture . . . . .
3.2.4 Transmitter Architecture . . . .
3.2.5 Wake on Radio . . . . . . .
3.2.6 RFSENSE . . . . . . . . .
3.2.7 Flexible Frame Handling . . . .
3.2.8 Packet and State Trace . . . .
3.2.9 Data Buffering . . . . . . . .
3.2.10 Radio Controller (RAC) . . . .
3.2.11 Random Number Generator . .
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3.3 Power . . . . . . . . . . .
3.3.1 Energy Management Unit (EMU)
3.3.2 DC-DC Converter . . . . .
3.3.3 Power Domains . . . . . .
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3.1 Introduction .
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3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 General Purpose Input/Output (GPIO) .
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3.5 Clocking . . . . . . . . . .
3.5.1 Clock Management Unit (CMU) .
3.5.2 Internal and External Oscillators.
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.13
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.13
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.14
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.14
3.7 Communications and Other Digital Peripherals . . . . . . . . . .
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) .
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) .
3.7.3 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . .
3.7.4 Peripheral Reflex System (PRS) . . . . . . . . . . . . .
3.7.5 Low Energy Sensor Interface (LESENSE) . . . . . . . . . .
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.14
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.15
3.8 Security Features . . . . . . . . . . . . . .
3.8.1 General Purpose Cyclic Redundancy Check (GPCRC)
3.8.2 Crypto Accelerator (CRYPTO) . . . . . . . .
3.8.3 Security Management Unit (SMU) . . . . . . .
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3.6 Counters/Timers and PWM . . . . . . . . .
3.6.1 Timer/Counter (TIMER) . . . . . . . .
3.6.2 Wide Timer/Counter (WTIMER) . . . . . .
3.6.3 Real Time Counter and Calendar (RTCC) . .
3.6.4 Low Energy Timer (LETIMER) . . . . . .
3.6.5 Ultra Low Power Wake-up Timer (CRYOTIMER)
3.6.6 Pulse Counter (PCNT) . . . . . . . . .
3.6.7 Watchdog Timer (WDOG) . . . . . . . .
silabs.com | Building a more connected world.
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Rev. 1.4 | 5
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3.10 Reset Management Unit (RMU) .
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3.11 Core and Memory . . . . . . . . . . . .
3.11.1 Processor Core . . . . . . . . . . . .
3.11.2 Memory System Controller (MSC) . . . . .
3.11.3 Linked Direct Memory Access Controller (LDMA)
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3.12 Memory Map .
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3.13 Configuration Summary
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4. Electrical Specifications
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3.9 Analog. . . . . . . . . . . . . .
3.9.1 Analog Port (APORT) . . . . . . .
3.9.2 Analog Comparator (ACMP) . . . . .
3.9.3 Analog to Digital Converter (ADC) . . .
3.9.4 Digital to Analog Current Converter (IDAC)
3.9.5 Digital to Analog Converter (VDAC) . .
3.9.6 Operational Amplifiers . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 19
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4.1 Electrical Characteristics . . . . . . . .
4.1.1 Absolute Maximum Ratings . . . . . .
4.1.2 Operating Conditions . . . . . . . .
4.1.3 Thermal Characteristics . . . . . . .
4.1.4 DC-DC Converter . . . . . . . . .
4.1.5 Current Consumption . . . . . . . .
4.1.6 Wake Up Times . . . . . . . . . .
4.1.7 Brown Out Detector (BOD) . . . . . .
4.1.8 Frequency Synthesizer . . . . . . . .
4.1.9 2.4 GHz RF Transceiver Characteristics . .
4.1.10 Sub-GHz RF Transceiver Characteristics .
4.1.11 Modem. . . . . . . . . . . . .
4.1.12 Oscillators . . . . . . . . . . .
4.1.13 Flash Memory Characteristics . . . . .
4.1.14 General-Purpose I/O (GPIO) . . . . .
4.1.15 Voltage Monitor (VMON) . . . . . . .
4.1.16 Analog to Digital Converter (ADC) . . .
4.1.17 Analog Comparator (ACMP) . . . . .
4.1.18 Digital to Analog Converter (VDAC) . . .
4.1.19 Current Digital to Analog Converter (IDAC)
4.1.20 Operational Amplifier (OPAMP) . . . .
4.1.21 Pulse Counter (PCNT) . . . . . . .
4.1.22 Analog Port (APORT) . . . . . . . .
4.1.23 I2C . . . . . . . . . . . . . .
4.1.24 USART SPI . . . . . . . . . . .
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.19
.20
.22
.24
.25
.27
.37
.38
.39
.40
.49
.74
.75
.79
.80
.82
.83
.85
.88
.91
.93
.96
.96
.97
.100
4.2 Typical Performance Curves
. . . . . . . . . . . . . . . . . . . . . . . .101
4.2.1 Supply Current
. . . . . . . . . . . . . . . . . . . . . . . . . . 1. 02
4.2.2 DC-DC Converter
. . . . . . . . . . . . . . . . . . . . . . . . . 107
.
4.2.3 2.4 GHz Radio
. . . . . . . . . . . . . . . . . . . . . . . . . . 109
.
5. Typical Connection Diagrams
silabs.com | Building a more connected world.
. . . . . . . . . . . . . . . . . . . . . . . .111
Rev. 1.4 | 6
5.1 Power .
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5.2 RF Matching Networks
5.3 Other Connections.
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. 111
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.113
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. 114
6.1 QFN48 2.4 GHz and Sub-GHz Device Pinout.
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6.2 QFN48 2.4 GHz Device Pinout
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6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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6.5 Alternate Functionality Overview .
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6.6 Analog Port (APORT) Client Maps
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6.4 GPIO Functionality Table
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.155
7. QFN48 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 162
7.2 QFN48 PCB Land Pattern
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7.3 QFN48 Package Marking
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7.1 QFN48 Package Dimensions
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.166
8. QFN32 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 167
8.2 QFN32 PCB Land Pattern
8.3 QFN32 Package Marking
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9. Revision History
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8.1 QFN32 Package Dimensions
silabs.com | Building a more connected world.
Rev. 1.4 | 7
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
System Overview
3. System Overview
3.1 Introduction
es
ig
ns
The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for
any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a
short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG14 Wireless
Gecko Reference Manual.
A block diagram of the EFR32MG14 family is shown in Figure 3.1 Detailed EFR32MG14 Block Diagram on page 8. The diagram
shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult
Ordering Information.
Radio Transceiver
Port I/O Configuration
PA
Frequency
Synthesizer
To RF
Frontend
Circuits
Q
AGC
MOD
D
PCNT
Port
Mapper
Brown Out /
Power-On
Reset
ARM Cortex-M4 Core
Up to 32 KB RAM
Memory Protection Unit
Energy Management
PAVDD
Voltage
Monitor
AVDD
DVDD
bypass
VREGVDD
DC-DC
Converter
VREGSW
DECOUPLE
PBn
Port C
Drivers
PCn
Port D
Drivers
PDn
Port F
Drivers
PFn
ULFRCO
CRC
LESENSE
Analog Peripherals
IDAC
VDAC
Internal
Reference
12-bit ADC
Op-Amp
VDD
Temp
Sense
LFXO
HFRCO
+
Analog Comparator
Figure 3.1. Detailed EFR32MG14 Block Diagram
ec
om
HFXO
R
3.2 Radio
Clock Management
LFRCO
LFXTAL_N
HFXTAL_P
HFXTAL_N
Voltage
Regulator
Watchdog
Timer
AUXHFRCO
LFXTAL_P
A A
H P
B B
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IOVDD
CRYPTO
Floating Point Unit
DMA Controller
RFVDD
I2C
Up to 256 KB ISP Flash
Program Memory
Mux & FB
Debug Signals
(shared w/GPIO)
LEUART
Input Mux
Serial Wire
Debug /
Programming
Port B
Drivers
RTC / RTCC
fo
r
RESETn
PAn
CRYOTIMER
USART
Reset
Management
Unit
Port A
Drivers
APORT
I
N
ew
BALUN
2G4RF_ION
TIMER
2.4 GHz RF
LNA
2G4RF_IOP
IFADC
PGA
Q
Digital Peripherals
LETIMER
RAC
RFSENSE
CRC
PA
FRC
DEMOD
LNA
IOVDD
+
-
SUBGRF_IP
SUBGRF_IN
SUBGRF_OP
SUBGRF_ON
BUFC
Sub-GHz RF
I
N
ot
The Mighty Gecko family features a highly configurable radio transceiver supporting a wide range of wireless protocols.
silabs.com | Building a more connected world.
Rev. 1.4 | 8
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
System Overview
3.2.1 Antenna Interface
The EFR32MG14 family includes devices which support both single-band and dual-band RF communication over separate physical RF
interfaces.
The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The
2G4RF_ION pin should be grounded externally.
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The sub-GHz antenna interface consists of a differential transmit interface (pins SUBGRF_OP and SUBGRF_ON) and a differential receive interface (pinsSUBGRF_IP and SUBGRF_IN).
The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching
Networks section.
3.2.2 Fractional-N Frequency Synthesizer
D
The EFR32MG14 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is
used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly
generate the modulated RF carrier.
N
ew
The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with
low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to
optimize system energy consumption.
3.2.3 Receiver Architecture
fo
r
The EFR32MG14 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion
mixer, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital
converter (IFADC).
The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, providing flexibility with respect to known interferers at the image frequency.
m
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The Automatic Gain Control (AGC) block adjusts the receiver gain to optimize performance and avoid saturation for excellent selectivity
and blocking performance. The 2.4 GHz radio is calibrated at production to improve image rejection performance. The sub-GHz radio
can be calibrated on-demand by the user for the desired frequency band.
Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow receive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and
compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by
block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS) for 2.4 GHz and sub-GHz bands.
A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF channel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received
frame and the dynamic RSSI measurement can be monitored throughout reception.
ec
om
The EFR32MG14 features integrated support for antenna diversity to mitigate the problem of frequency-selective fading due to multipath propagation and improve link budget. Support for antenna diversity is available for specific PHY configurations in 2.4 GHz and
sub-GHz bands. Internal configurable hardware controls an external switch for automatic switching between antennae during RF receive detection operations.
R
Note: Due to the shorter preamble of 802.15.4 and BLE packets, RX diversity is not supported.
3.2.4 Transmitter Architecture
N
ot
The EFR32MG14 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls
phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping
filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shaping.
Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by
the EFR32MG14. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth between devices that otherwise lack synchronized RF channel access.
silabs.com | Building a more connected world.
Rev. 1.4 | 9
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
System Overview
3.2.5 Wake on Radio
The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, using a subsystem of the EFR32MG14 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripherals.
3.2.6 RFSENSE
es
ig
ns
The RFSENSE peripheral generates a system wakeup interrupt upon detection of wideband RF energy at the antenna interface, providing true RF wakeup capabilities from low energy modes including EM2, EM3 and EM4.
RFSENSE triggers on a relatively strong RF signal and is available in the lowest energy modes, allowing exceptionally low energy consumption. RFSENSE does not demodulate or otherwise qualify the received signal, but software may respond to the wakeup event by
enabling normal RF reception.
D
Various strategies for optimizing power consumption and system response time in presence of false alarms may be employed using
available timer peripherals.
3.2.7 Flexible Frame Handling
om
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N
ew
EFR32MG14 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols.
The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodulator:
• Highly adjustable preamble length
• Up to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts
• Frame disassembly and address matching (filtering) to accept or reject frames
• Automatic ACK frame assembly and transmission
• Fully flexible CRC generation and verification:
• Multiple CRC values can be embedded in a single frame
• 8, 16, 24 or 32-bit CRC value
• Configurable CRC bit and byte ordering
• Selectable bit-ordering (least significant or most significant bit first)
• Optional data whitening
• Optional Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding
• Half rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing
• Optional symbol interleaving, typically used in combination with FEC
• Symbol coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware
• UART encoding over air, with start and stop bit insertion / removal
• Test mode support, such as modulated or unmodulated carrier output
• Received frame timestamping
3.2.8 Packet and State Trace
N
ot
R
ec
The EFR32MG14 Frame Controller has a packet and state trace unit that provides valuable information during the development phase.
It features:
• Non-intrusive trace of transmit data, receive data and state information
• Data observability on a single-pin UART data output, or on a two-pin SPI data output
• Configurable data output bitrate / baudrate
• Multiplexed transmitted data, received data and state / meta information in a single serial data stream
3.2.9 Data Buffering
The EFR32MG14 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64
bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.
silabs.com | Building a more connected world.
Rev. 1.4 | 10
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
System Overview
3.2.10 Radio Controller (RAC)
The Radio Controller controls the top level state of the radio subsystem in the EFR32MG14. It performs the following tasks:
• Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry
• Run-time calibration of receiver, transmitter and frequency synthesizer
• Detailed frame transmission timing, including optional LBT or CSMA-CA
es
ig
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3.2.11 Random Number Generator
The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.
The data is suitable for use in cryptographic applications.
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D
Output from the random number generator can be used either directly or as a seed or entropy source for software-based random number generator algorithms such as Fortuna.
silabs.com | Building a more connected world.
Rev. 1.4 | 11
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
System Overview
3.3 Power
The EFR32MG14 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only
a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator
can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capacitor.
es
ig
ns
The EFR32MG14 device family includes support for internal supply voltage scaling, as well as two different power domains groups for
peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.
AVDD and VREGVDD need to be 1.8 V or higher for the MCU to operate across all conditions; however the rest of the system will
operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.
Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB
components, supplying up to a total of 200 mA.
3.3.1 Energy Management Unit (EMU)
N
ew
D
The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and
features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM
blocks, and it contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is used to monitor multiple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has
fallen below a chosen threshold.
3.3.2 DC-DC Converter
3.3.3 Power Domains
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The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2
and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Patented RF noise mitigation allows operation
of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting,
short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low
for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance
switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current transients.
The EFR32MG14 has two peripheral power domains for operation in EM2 and EM3. If all of the peripherals in a peripheral power domain are configured as unused, the power domain for that group will be powered off in the low-power mode, reducing the overall current consumption of the device.
Table 3.1. Peripheral Power Subdomains
om
Peripheral Power Domain 1
ACMP0
ADC0
ec
PCNT0
Peripheral Power Domain 2
ACMP1
CSEN
VDAC0
LEUART0
LESENSE
I2C0
APORT
IDAC
N
ot
R
LETIMER0
3.4 General Purpose Input/Output (GPIO)
EFR32MG14 has up to 31 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or
input. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO
pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to
several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripherals. The GPIO subsystem supports asynchronous external pin interrupts.
silabs.com | Building a more connected world.
Rev. 1.4 | 12
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
System Overview
3.5 Clocking
3.5.1 Clock Management Unit (CMU)
es
ig
ns
The Clock Management Unit controls oscillators and clocks in the EFR32MG14. Individual enabling and disabling of clocks to all peripherals is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility allows
software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and oscillators.
3.5.2 Internal and External Oscillators
3.6 Counters/Timers and PWM
3.6.1 Timer/Counter (TIMER)
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D
The EFR32MG14 supports two crystal oscillators and fully integrates four RC oscillators, listed below.
• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing reference for the MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can
also be applied to the HFXO input for improved accuracy over temperature.
• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.
• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The
HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.
• An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial
Wire Viewer port with a wide frequency range.
• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crystal accuracy is not required.
• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy consumption in low energy modes.
m
en
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TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one
of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output
reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width
modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional
dead-time insertion available in timer unit TIMER_0 only.
3.6.2 Wide Timer/Counter (WTIMER)
ec
om
WTIMER peripherals function just as TIMER peripherals, but are 32 bits wide. They keep track of timing, count events, generate PWM
outputs and trigger timed actions in other peripherals through the PRS system. The core of each WTIMER is a 32-bit counter with up to
4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a
buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. In PWM mode, the WTIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by
the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit WTIMER_0 only.
3.6.3 Real Time Counter and Calendar (RTCC)
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The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a
Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscillators with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving
frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy
and convenient data storage in all energy modes down to EM4H.
A secondary RTC is used by the RF protocol stack for event scheduling, leaving the primary RTCC block available exclusively for application software.
silabs.com | Building a more connected world.
Rev. 1.4 | 13
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
System Overview
3.6.4 Low Energy Timer (LETIMER)
The unique LETIMER is a 16-bit timer that is available in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop. This
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be
configured to start counting on compare matches from the RTCC.
es
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3.6.5 Ultra Low Power Wake-up Timer (CRYOTIMER)
The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal
oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events
and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of interrupt periods, facilitating flexible ultra-low energy operation.
3.6.6 Pulse Counter (PCNT)
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The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The
clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from
among any of the internal oscillators, except the AUXHFRCO. The peripheral may operate in energy mode EM0 Active, EM1 Sleep,
EM2 Deep Sleep, and EM3 Stop.
3.6.7 Watchdog Timer (WDOG)
3.7 Communications and Other Digital Peripherals
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The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous systems driven by PRS.
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3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O interface. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices supporting:
• ISO7816 SmartCards
• IrDA
• I2S
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
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The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow
UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication
possible with a minimum of software intervention and energy consumption.
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3.7.3 Inter-Integrated Circuit Interface (I2C)
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The I2C interface enables communication between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave
and supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates
from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system.
The interface provided to software by the I2C peripheral allows precise timing control of the transmission process and highly automated
transfers. Automatic recognition of slave addresses is provided in active and low energy modes.
3.7.4 Peripheral Reflex System (PRS)
The Peripheral Reflex System provides a communication network between different peripherals without software involvement. Peripherals producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer peripherals, which in
turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT) can be applied
by the PRS to the signals. The PRS allows peripheral to act autonomously without waking the MCU core, saving power.
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Rev. 1.4 | 14
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
System Overview
3.7.5 Low Energy Sensor Interface (LESENSE)
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The Low Energy Sensor Interface LESENSETM is a highly configurable sensor interface with support for up to 16 individually configurable sensors. By controlling the analog comparators, ADC, and DAC, LESENSE is capable of supporting a wide range of sensors and
measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a
programmable finite state machine which enables simple processing of measurement results without CPU intervention. LESENSE is
available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy
budget.
3.8 Security Features
3.8.1 General Purpose Cyclic Redundancy Check (GPCRC)
D
The GPCRC block implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The supported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the
needs of the application.
3.8.2 Crypto Accelerator (CRYPTO)
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The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices support AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), SHA-1 and SHA-2 (SHA-224 and
SHA-256).
Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.
Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.
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The CRYPTO block is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on
data buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention.
CRYPTO also provides trigger signals for DMA read and write operations.
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3.8.3 Security Management Unit (SMU)
The Security Management Unit (SMU) allows software to set up fine-grained security for peripheral access, which is not possible in the
Memory Protection Unit (MPU). Peripherals may be secured by hardware on an individual basis, such that only priveleged accesses to
the peripheral's register interface will be allowed. When an access fault occurs, the SMU reports the specific peripheral involved and
can optionally generate an interrupt.
3.9 Analog
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3.9.1 Analog Port (APORT)
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The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog peripherals on a flexible selection of pins.
Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are
grouped by X/Y pairs.
3.9.2 Analog Comparator (ACMP)
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The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption
is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The
ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the
programmable threshold.
3.9.3 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output
sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.
The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of
sources, including pins configurable as either single-ended or differential.
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
System Overview
3.9.4 Digital to Analog Current Converter (IDAC)
The IDAC can source or sink a configurable constant current. This current can be driven on an output pin or routed to the selected ADC
input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with several ranges consisting of
various step sizes.
3.9.5 Digital to Analog Converter (VDAC)
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The Digital to Analog Converter (VDAC) can convert a digital value to an analog output voltage. The VDAC is a fully differential, 500
ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per singleended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications
such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low
frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any
CPU intervention. The VDAC is available in all energy modes down to and including EM3.
3.9.6 Operational Amplifiers
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The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas, and
are available down to EM3. With flexible built-in programming for gain and interconnection they can be configured to support multiple
common opamp functions. All pins are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to
rail output. They can be used in conjunction with the VDAC peripheral or in stand-alone configurations. The opamps save energy, PCB
space, and cost as compared with standalone opamps because they are integrated on-chip.
3.10 Reset Management Unit (RMU)
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The RMU is responsible for handling reset of the EFR32MG14. A wide range of reset sources are available, including several power
supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.
3.11 Core and Memory
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3.11.1 Processor Core
The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
• ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz
• Memory Protection Unit (MPU) supporting up to 8 memory segments
• Up to 256 kB flash program memory
• Up to 32 kB RAM data memory
• Configuration and event handling of all peripherals
• 2-pin Serial-Wire debug interface
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3.11.2 Memory System Controller (MSC)
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The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code
is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a
read-only page in the information block containing system and device calibration data. Read and write operations are supported in energy modes EM0 Active and EM1 Sleep.
3.11.3 Linked Direct Memory Access Controller (LDMA)
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The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This
reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling sophisticated operations to be implemented.
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Rev. 1.4 | 16
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
System Overview
3.12 Memory Map
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The EFR32MG14 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.
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Figure 3.2. EFR32MG14 Memory Map — Core Peripherals and Code Space
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
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System Overview
Figure 3.3. EFR32MG14 Memory Map — Peripherals
3.13 Configuration Summary
Module
R
USART0
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The features of the EFR32MG14 are a subset of the feature set described in the device reference manual. The table below describes
device specific implementation of the features. Remaining modules support full configuration.
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USART1
Table 3.2. Configuration Summary
Configuration
Pin Connections
IrDA
US0_TX, US0_RX, US0_CLK, US0_CS
SmartCard
I2S
US1_TX, US1_RX, US1_CLK, US1_CS
SmartCard
TIMER0
with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
-
TIM1_CC[3:0]
WTIMER0
with DTI
WTIM0_CC[2:0], WTIM0_CDTI[2:0]
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Rev. 1.4 | 18
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
• Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization.
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• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output power-specific external RF impedance-matching networks for interfacing to a 50 Ω source or load.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,
unless stated otherwise.
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Refer to 4.1.2.1 General Operating Conditions for more details about operational supply and temperature limits.
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Rev. 1.4 | 19
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.1 Absolute Maximum Ratings
Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.
Symbol
Test Condition
Storage temperature range
TSTG
-50
Voltage on any supply pin
VDDMAX
-0.3
Voltage ramp rate on any
supply pin
VDDRAMPMAX
DC voltage on any GPIO pin
VDIGPIN
—
Voltage differential between
RF pins (2G4RF_IOP 2G4RF_ION)
VMAXDIFF2G4
Absolute voltage on RF pins
2G4RF_IOP and
2G4RF_ION
VMAX2G4
Absolute voltage on SubGHz RF pins
VMAXSUBG
Unit
—
150
°C
—
3.8
V
—
1
V / µs
Min of 5.25
and IOVDD
+2
V
—
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ew
PRFMAX2G4
Max
—
IOVDD+0.3
V
-0.3
—
1.4
V
—
—
10
dBm
-50
—
50
mV
-0.3
—
3.3
V
Pins SUBGRF_OP and
SUBGRF_ON
-0.3
—
3.3
V
Pins SUBGRF_IP and
SUBGRF_IN,
-0.3
—
0.3
V
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Input RF level on pins
2G4RF_IOP and
2G4RF_ION
Typ
-0.3
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VHFXOPIN
-0.3
5V tolerant GPIO pins1 2 3
Standard GPIO pins
Voltage on HFXO pins
Min
D
Parameter
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Table 4.1. Absolute Maximum Ratings
Source
—
—
200
mA
Total current into VSS
ground lines
IVSSMAX
Sink
—
—
200
mA
Current per I/O pin
IIOMAX
Sink
—
—
50
mA
Source
—
—
50
mA
Sink
—
—
200
mA
Source
—
—
200
mA
-G grade devices
-40
—
105
°C
-I grade devices
-40
—
125
°C
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Total current into VDD power IVDDMAX
lines
R
Current for all I/O pins
N
ot
Junction temperature
IIOALLMAX
TJ
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
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Note:
1. When a GPIO pin is routed to the analog block through the APORT, the maximum voltage = IOVDD.
2. Valid for IOVDD in valid operating range or when IOVDD is undriven (high-Z). If IOVDD is connected to a low-impedance source
below the valid operating range (e.g. IOVDD shorted to VSS), the pin voltage maximum is IOVDD + 0.3 V, to avoid exceeding the
maximum IO current specifications.
3. To operate above the IOVDD supply rail, over-voltage tolerance must be enabled according to the GPIO_Px_OVTDIS register.
Pins with over-voltage tolerance disabled have the same limits as Standard GPIO.
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.2 Operating Conditions
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When assigning supply sources, the following requirements must be observed:
• VREGVDD must be greater than or equal to AVDD, DVDD, RFVDD, PAVDD and all IOVDD supplies.
• VREGVDD = AVDD
• DVDD ≤ AVDD
• IOVDD ≤ AVDD
• RFVDD ≤ AVDD
• PAVDD ≤ AVDD
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Rev. 1.4 | 22
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.2.1 General Operating Conditions
Table 4.2. General Operating Conditions
Symbol
Test Condition
Min
Typ
Max
Unit
Operating ambient temperature range1
TA
-G temperature grade
-40
25
85
°C
-I temperature grade
-40
25
125
°C
AVDD supply voltage2
VAVDD
3.3
3.8
V
VREGVDD operating supply
voltage2 3
VVREGVDD
3.3
3.8
V
3.3
3.8
V
3.3
3.8
V
—
200
mA
2.4
DCDC in bypass, 50mA load
1.8
DCDC not in use. DVDD externally shorted to VREGVDD
1.8
DCDC in bypass, T ≤ 85 °C
—
VRFVDD
DVDD operating supply voltage
VDVDD
PAVDD operating supply
voltage
VPAVDD
DECOUPLE output capacitor4 5
—
100
mA
1.62
—
VVREGVDD
V
1.62
—
VVREGVDD
V
1.62
—
VVREGVDD
V
1.62
—
VVREGVDD
V
0.75
1.0
2.75
µF
—
—
0.1
V
VSCALE2, MODE = WS1
—
—
40
MHz
VSCALE2, MODE = WS0
—
—
25
MHz
VSCALE0, MODE = WS2
—
—
20
MHz
VSCALE0, MODE = WS1
—
—
14
MHz
VSCALE0, MODE = WS0
—
—
7
MHz
VSCALE2
—
—
40
MHz
VSCALE0
—
—
20
MHz
All IOVDD pins
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IOVDD operating supply volt- VIOVDD
age
—
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DCDC in bypass, T > 85 °C
RFVDD operating supply
voltage
CDECOUPLE
Difference between AVDD
dVDD
and VREGVDD, ABS(AVDDVREGVDD)2
fCORE
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HFCORECLK frequency
fHFCLK
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ot
R
HFCLK frequency
D
IVREGVDD
DCDC in regulation
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VREGVDD current
1.8
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ns
Parameter
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Rev. 1.4 | 23
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note:
1. The maximum limit on TA may be lower due to device self-heating, which depends on the power dissipation of the specific application. TA (max) = TJ (max) - (THETAJA x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal
Characteristics table for TJ and THETAJA.
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2. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.
3. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for
other loads can be calculated as VDVDD_min+ILOAD * RBYP_max.
D
4. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance value stays within the specified bounds across temperature and DC bias.
5. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV / usec for approximately 20 usec. During this transition, peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70
mA (with a 2.7 µF capacitor).
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4.1.3 Thermal Characteristics
Table 4.3. Thermal Characteristics
Symbol
Thermal resistance, QFN48
Package
Min
Typ
Max
Unit
THETAJA_QFN48 2-Layer PCB, Air velocity = 0 m/s
—
64.5
—
°C/W
2-Layer PCB, Air velocity = 1 m/s
—
51.6
—
°C/W
2-Layer PCB, Air velocity = 2 m/s
—
47.7
—
°C/W
4-Layer PCB, Air velocity = 0 m/s
—
26.2
—
°C/W
4-Layer PCB, Air velocity = 1 m/s
—
23.1
—
°C/W
4-Layer PCB, Air velocity = 2 m/s
—
22.1
—
°C/W
THETAJA_QFN32 2-Layer PCB, Air velocity = 0 m/s
—
82.1
—
°C/W
2-Layer PCB, Air velocity = 1 m/s
—
64.7
—
°C/W
2-Layer PCB, Air velocity = 2 m/s
—
56.3
—
°C/W
4-Layer PCB, Air velocity = 0 m/s
—
36.8
—
°C/W
4-Layer PCB, Air velocity = 1 m/s
—
32
—
°C/W
4-Layer PCB, Air velocity = 2 m/s
—
30.6
—
°C/W
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Thermal resistance, QFN32
Package
Test Condition
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Parameter
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Rev. 1.4 | 24
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.4 DC-DC Converter
Test conditions: L_DCDC=4.7 µH (Murata LQH3NPN4R7MM0L), C_DCDC=4.7 µF (Samsung CL10B475KQ8NQNC), V_DCDC_I=3.3
V, V_DCDC_O=1.8 V, I_DCDC_LOAD=50 mA, Heavy Drive configuration, F_DCDC_LN=7 MHz, unless otherwise indicated.
Table 4.4. DC-DC Converter
Symbol
Test Condition
Min
Input voltage range
VDCDC_I
Bypass mode, IDCDC_LOAD = 50
mA
1.8
Low noise (LN) mode, 1.8 V output, IDCDC_LOAD = 100 mA, or
Low power (LP) mode, 1.8 V output, IDCDC_LOAD = 10 mA
2.4
Low noise (LN) mode, 1.8 V output, IDCDC_LOAD = 200 mA
2.6
ACCDC
Regulation window2
WINREG
Unit
VVREGVDD_
V
MAX
—
VVREGVDD_
V
MAX
—
VVREGVDD_
V
D
Regulation DC accuracy
—
1.8
—
VVREGVDD
V
Low Noise (LN) mode, 1.8 V target output
1.7
—
1.9
V
Low Power (LP) mode,
LPCMPBIASEMxx3 = 0, 1.8 V target output, IDCDC_LOAD ≤ 75 µA
1.63
—
2.2
V
Low Power (LP) mode,
LPCMPBIASEMxx3 = 3, 1.8 V target output, IDCDC_LOAD ≤ 10 mA
1.63
—
2.1
V
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VDCDC_O
Max
MAX
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Output voltage programmable range1
Typ
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ns
Parameter
VR
Radio disabled
—
3
—
mVpp
Output voltage under/overshoot
VOV
CCM Mode (LNFORCECCM3 =
1), Load changes between 0 mA
and 100 mA
—
25
60
mV
DCM Mode (LNFORCECCM3 =
0), Load changes between 0 mA
and 10 mA
—
45
90
mV
Overshoot during LP to LN
CCM/DCM mode transitions compared to DC level in LN mode
—
200
—
mV
Undershoot during BYP/LP to LN
CCM (LNFORCECCM3 = 1) mode
transitions compared to DC level
in LN mode
—
40
—
mV
Undershoot during BYP/LP to LN
DCM (LNFORCECCM3 = 0) mode
transitions compared to DC level
in LN mode
—
100
—
mV
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Steady-state output ripple
DC line regulation
VREG
Input changes between
VVREGVDD_MAX and 2.4 V
—
0.1
—
%
DC load regulation
IREG
Load changes between 0 mA and
100 mA in CCM mode
—
0.1
—
%
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Rev. 1.4 | 25
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Min
Typ
Max
Unit
Max load current
ILOAD_MAX
Low noise (LN) mode, Heavy
Drive4, T ≤ 85 °C
—
—
200
mA
Low noise (LN) mode, Heavy
Drive4, T > 85 °C
—
—
100
mA
Low noise (LN) mode, Medium
Drive4
—
—
100
mA
Low noise (LN) mode, Light
Drive4
—
Low power (LP) mode,
LPCMPBIASEMxx3 = 0
—
Low power (LP) mode,
LPCMPBIASEMxx3 = 3
—
CDCDC
25% tolerance
1
DCDC nominal output induc- LDCDC
tor
20% tolerance
DCDC nominal output capacitor5
Resistance in Bypass mode
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Test Condition
—
50
mA
—
75
µA
—
10
mA
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Symbol
4.7
µF
4.7
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Parameter
RBYP
4.7
4.7
4.7
µH
—
1.2
2.5
Ω
fo
r
Note:
1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, VVREGVDD.
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2. LP mode controller is a hysteretic controller that maintains the output voltage within the specified limits.
3. LPCMPBIASEMxx refers to either LPCMPBIASEM234H in the EMU_DCDCMISCCTRL register or LPCMPBIASEM01 in the
EMU_DCDCLOEM01CFG register, depending on the energy mode.
4. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medium Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.
5. Output voltage under/over-shoot and regulation are specified with CDCDC 4.7 µF. Different settings for DCDCLNCOMPCTRL
must be used if CDCDC is lower than 4.7 µF. See Application Note AN0948 for details.
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Rev. 1.4 | 26
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.5 Current Consumption
4.1.5.1 Current Consumption 3.3 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 3.3 V. T = 25 °C. DCDC is off.
Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.
Symbol
Min
Typ
Max
Unit
123
—
µA/MHz
96
—
µA/MHz
38.4 MHz crystal, CPU running
while loop from flash1
—
38 MHz HFRCO, CPU running
Prime from flash
—
38 MHz HFRCO, CPU running
while loop from flash
—
93
103
µA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
—
116
—
µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
—
95
106
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
227
384
µA/MHz
19 MHz HFRCO, CPU running
while loop from flash
—
82
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
198
—
µA/MHz
38.4 MHz crystal1
—
73
—
µA/MHz
38 MHz HFRCO
—
44
47
µA/MHz
26 MHz HFRCO
—
46
51
µA/MHz
1 MHz HFRCO
—
178
335
µA/MHz
Current consumption in EM1 IEM1_VS
mode with all peripherals disabled and voltage scaling
enabled
19 MHz HFRCO
—
41
—
µA/MHz
1 MHz HFRCO
—
158
—
µA/MHz
Current consumption in EM2 IEM2_VS
mode, with voltage scaling
enabled
Full 32 kB RAM retention and
RTCC running from LFXO
—
1.9
—
µA
Full 32 kB RAM retention and
RTCC running from LFRCO
—
2.2
—
µA
1 bank (16 kB) RAM retention and
RTCC running from LFRCO2
—
1.9
3.3
µA
Current consumption in EM3 IEM3_VS
mode, with voltage scaling
enabled
Full 32 kB RAM retention and
CRYOTIMER running from ULFRCO
—
1.44
3.0
µA
Current consumption in
EM4H mode, with voltage
scaling enabled
128 byte RAM retention, RTCC
running from LFXO
—
0.89
—
µA
128 byte RAM retention, CRYOTIMER running from ULFRCO
—
0.55
—
µA
128 byte RAM retention, no RTCC
—
0.54
0.8
µA
m
en
de
d
Current consumption in EM0 IACTIVE_VS
mode with all peripherals disabled and voltage scaling
enabled
fo
r
N
ew
Current consumption in EM0 IACTIVE
mode with all peripherals disabled
Test Condition
D
Parameter
es
ig
ns
Table 4.5. Current Consumption 3.3 V without DC-DC Converter
N
ot
R
ec
om
Current consumption in EM1 IEM1
mode with all peripherals disabled
IEM4H_VS
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Rev. 1.4 | 27
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Current consumption in
EM4S mode
IEM4S
No RAM retention, no RTCC
Min
Typ
Max
Unit
—
0.04
0.085
µA
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
es
ig
ns
Note:
1. CMU_HFXOCTRL_LOWPOWER=0.
2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
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Rev. 1.4 | 28
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.5.2 Current Consumption 3.3 V using DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V DC-DC
output. T = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.
Table 4.6. Current Consumption 3.3 V using DC-DC Converter
Min
38 MHz HFRCO, CPU running
Prime from flash
—
38 MHz HFRCO, CPU running
while loop from flash
—
38 MHz HFRCO, CPU running
CoreMark from flash
—
26 MHz HFRCO, CPU running
while loop from flash
Max
Unit
—
µA/MHz
68
—
µA/MHz
67
—
µA/MHz
80
—
µA/MHz
—
73
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
606
—
µA/MHz
38.4 MHz crystal, CPU running
while loop from flash2
—
94
—
µA/MHz
38 MHz HFRCO, CPU running
Prime from flash
—
79
—
µA/MHz
38 MHz HFRCO, CPU running
while loop from flash
—
78
—
µA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
—
90
—
µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
—
90
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
1109
—
µA/MHz
Current consumption in EM0 IACTIVE_CCM_VS
mode with all peripherals disabled and voltage scaling
enabled, DCDC in Low
Noise CCM mode3
19 MHz HFRCO, CPU running
while loop from flash
—
97
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
1093
—
µA/MHz
Current consumption in EM1 IEM1_DCM
mode with all peripherals disabled, DCDC in Low Noise
DCM mode1
38.4 MHz crystal2
—
55
—
µA/MHz
38 MHz HFRCO
—
38
—
µA/MHz
26 MHz HFRCO
—
45
—
µA/MHz
1 MHz HFRCO
—
580
—
µA/MHz
19 MHz HFRCO
—
48
—
µA/MHz
1 MHz HFRCO
—
569
—
µA/MHz
N
ew
—
Typ
84
N
ot
R
ec
om
m
en
de
d
Current consumption in EM0 IACTIVE_CCM
mode with all peripherals disabled, DCDC in Low Noise
CCM mode3
38.4 MHz crystal, CPU running
while loop from flash2
fo
r
Current consumption in EM0 IACTIVE_DCM
mode with all peripherals disabled, DCDC in Low Noise
DCM mode1
Test Condition
es
ig
ns
Symbol
D
Parameter
Current consumption in EM1 IEM1_DCM_VS
mode with all peripherals disabled and voltage scaling
enabled, DCDC in Low
Noise DCM mode1
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Rev. 1.4 | 29
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Current consumption in EM3 IEM3_VS
mode, with voltage scaling
enabled
Current consumption in
EM4H mode, with voltage
scaling enabled
Current consumption in
EM4S mode
IEM4H_VS
IEM4S
Min
Typ
Max
Unit
Full 32 kB RAM retention and
RTCC running from LFXO
—
1.4
—
µA
Full 32 kB RAM retention and
RTCC running from LFRCO
—
1.5
—
µA
1 bank (16 kB) RAM retention and
RTCC running from LFRCO5
—
1.3
—
µA
Full 32 kB RAM retention and
CRYOTIMER running from ULFRCO
—
128 byte RAM retention, RTCC
running from LFXO
—
128 byte RAM retention, CRYOTIMER running from ULFRCO
—
128 byte RAM retention, no RTCC
—
es
ig
ns
Current consumption in EM2 IEM2_VS
mode, with voltage scaling
enabled, DCDC in LP mode4
Test Condition
1.02
—
µA
0.74
—
µA
0.48
—
µA
D
Symbol
—
µA
—
µA
0.48
N
ew
Parameter
No RAM retention, no RTCC
—
0.07
N
ot
R
ec
om
m
en
de
d
fo
r
Note:
1. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD.
2. CMU_HFXOCTRL_LOWPOWER=0.
3. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD.
4. DCDC Low Power Mode = Medium Drive, LPOSCDIV=1, LPCMPBIASEM234H=0, LPCLIMILIMSEL=1, ANASW=DVDD.
5. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
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Rev. 1.4 | 30
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.5.3 Current Consumption 1.8 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 1.8 V. T = 25 °C. DCDC is off.
Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.
Table 4.7. Current Consumption 1.8 V without DC-DC Converter
Min
—
38 MHz HFRCO, CPU running
Prime from flash
—
38 MHz HFRCO, CPU running
while loop from flash
—
38 MHz HFRCO, CPU running
CoreMark from flash
—
26 MHz HFRCO, CPU running
while loop from flash
Typ
Max
Unit
123
—
µA/MHz
96
—
µA/MHz
93
—
µA/MHz
115
—
µA/MHz
—
95
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
224
—
µA/MHz
Current consumption in EM0 IACTIVE_VS
mode with all peripherals disabled and voltage scaling
enabled
19 MHz HFRCO, CPU running
while loop from flash
—
81
—
µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
—
195
—
µA/MHz
Current consumption in EM1 IEM1
mode with all peripherals disabled
38.4 MHz crystal1
—
74
—
µA/MHz
38 MHz HFRCO
—
44
—
µA/MHz
26 MHz HFRCO
—
46
—
µA/MHz
1 MHz HFRCO
—
175
—
µA/MHz
Current consumption in EM1 IEM1_VS
mode with all peripherals disabled and voltage scaling
enabled
19 MHz HFRCO
—
41
—
µA/MHz
1 MHz HFRCO
—
155
—
µA/MHz
Current consumption in EM2 IEM2_VS
mode, with voltage scaling
enabled
Full 32 kB RAM retention and
RTCC running from LFXO
—
1.7
—
µA
Full 32 kB RAM retention and
RTCC running from LFRCO
—
1.9
—
µA
1 bank (16 kB) RAM retention and
RTCC running from LFRCO2
—
1.7
—
µA
Current consumption in EM3 IEM3_VS
mode, with voltage scaling
enabled
Full 32 kB RAM retention and
CRYOTIMER running from ULFRCO
—
1.33
—
µA
Current consumption in
EM4H mode, with voltage
scaling enabled
128 byte RAM retention, RTCC
running from LFXO
—
0.80
—
µA
128 byte RAM retention, CRYOTIMER running from ULFRCO
—
0.44
—
µA
128 byte RAM retention, no RTCC
—
0.43
—
µA
no RAM retention, no RTCC
—
0.04
—
µA
fo
r
N
ew
38.4 MHz crystal, CPU running
while loop from flash1
N
ot
R
ec
om
m
en
de
d
Current consumption in EM0 IACTIVE
mode with all peripherals disabled
Test Condition
es
ig
ns
Symbol
D
Parameter
Current consumption in
EM4S mode
IEM4H_VS
IEM4S
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Rev. 1.4 | 31
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
es
ig
ns
Note:
1. CMU_HFXOCTRL_LOWPOWER=0.
2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
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Rev. 1.4 | 32
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.5.4 Current Consumption Using Radio 3.3 V with DC-DC
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V. T = 25
°C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.
Table 4.8. Current Consumption Using Radio 3.3 V with DC-DC
Test Condition
Min
Current consumption in receive mode, active packet
reception (MCU in EM1 @
38.4 MHz, peripheral clocks
disabled), T ≤ 85 °C
IRX_ACTIVE
500 kbit/s, 2GFSK, F = 915 MHz,
Radio clock prescaled by 4
—
38.4 kbit/s, 2GFSK, F = 868 MHz,
Radio clock prescaled by 4
—
38.4 kbit/s, 2GFSK, F = 490 MHz,
Radio clock prescaled by 4
—
50 kbit/s, 2GFSK, F = 433 MHz,
Radio clock prescaled by 4
—
38.4 kbit/s, 2GFSK, F = 315 MHz,
Radio clock prescaled by 4
Typ
Unit
10.2
mA
8.6
10.2
mA
8.6
10.2
mA
8.6
10.2
mA
—
8.6
10.2
mA
38.4 kbit/s, 2GFSK, F = 169 MHz,
Radio clock prescaled by 4
—
8.4
10.2
mA
1 Mbit/s, 2GFSK, F = 2.4 GHz,
Radio clock prescaled by 4
—
8.8
—
mA
802.15.4 receiving frame, F = 2.4
GHz, Radio clock prescaled by 3
—
10.2
—
mA
500 kbit/s, 2GFSK, F = 915 MHz,
Radio clock prescaled by 4
—
—
13
mA
38.4 kbit/s, 2GFSK, F = 868 MHz,
Radio clock prescaled by 4
—
—
13
mA
38.4 kbit/s, 2GFSK, F = 490 MHz,
Radio clock prescaled by 4
—
—
13
mA
50 kbit/s, 2GFSK, F = 433 MHz,
Radio clock prescaled by 4
—
—
13
mA
38.4 kbit/s, 2GFSK, F = 315 MHz,
Radio clock prescaled by 4
—
—
13
mA
38.4 kbit/s, 2GFSK, F = 169 MHz,
Radio clock prescaled by 4
—
—
13
mA
fo
r
N
ew
9.3
m
en
de
d
IRX_ACTIVE_HT
N
ot
R
ec
om
Current consumption in receive mode, active packet
reception (MCU in EM1 @
38.4 MHz, peripheral clocks
disabled), T > 85 °C
Max
es
ig
ns
Symbol
D
Parameter
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Rev. 1.4 | 33
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Max
Unit
500 kbit/s, 2GFSK, F = 915 MHz,
No radio clock prescaling
—
10.2
11
mA
38.4 kbit/s, 2GFSK, F = 868 MHz,
No radio clock prescaling
—
9.5
11
mA
38.4 kbit/s, 2GFSK, F = 490 MHz,
No radio clock prescaling
—
9.5
11
mA
50 kbit/s, 2GFSK, F = 433 MHz,
No radio clock prescaling
—
38.4 kbit/s, 2GFSK, F = 315 MHz,
No radio clock prescaling
—
38.4 kbit/s, 2GFSK, F = 169 MHz,
No radio clock prescaling
—
1 Mbit/s, 2GFSK, F = 2.4 GHz, No
radio clock prescaling
es
ig
ns
Typ
9.5
11
mA
9.4
11
mA
9.3
11
mA
—
9.6
—
mA
802.15.4, F = 2.4 GHz, No radio
clock prescaling
—
11.1
—
mA
500 kbit/s, 2GFSK, F = 915 MHz,
No radio clock prescaling
—
—
14
mA
38.4 kbit/s, 2GFSK, F = 868 MHz,
No radio clock prescaling
—
—
14
mA
38.4 kbit/s, 2GFSK, F = 490 MHz,
No radio clock prescaling
—
—
14
mA
50 kbit/s, 2GFSK, F = 433 MHz,
No radio clock prescaling
—
—
14
mA
38.4 kbit/s, 2GFSK, F = 315 MHz,
No radio clock prescaling
—
—
14
mA
38.4 kbit/s, 2GFSK, F = 169 MHz,
No radio clock prescaling
—
—
14
mA
N
ot
R
ec
om
m
en
de
d
Current consumption in reIRX_LISTEN_HT
ceive mode, listening for
packet (MCU in EM1 @ 38.4
MHz, peripheral clocks disabled), T > 85 °C
Min
D
Current consumption in reIRX_LISTEN
ceive mode, listening for
packet (MCU in EM1 @ 38.4
MHz, peripheral clocks disabled), T ≤ 85 °C
Test Condition
N
ew
Symbol
fo
r
Parameter
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Rev. 1.4 | 34
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Min
Typ
Max
Unit
Current consumption in
transmit mode (MCU in EM1
@ 38.4 MHz, peripheral
clocks disabled), T ≤ 85 °C
ITX
F = 915 MHz, CW, 20 dBm
match, External PA supply = 3.3V
—
90.2
134.3
mA
F = 915 MHz, CW, 14 dBm
match, External PA supply connected to DCDC output
—
36
42.5
mA
F = 868 MHz, CW, 20 dBm
match, External PA supply = 3.3V
—
79.7
106.7
mA
F = 868 MHz, CW, 14 dBm
match, External PA supply connected to DCDC output
—
35.3
41
mA
F = 490 MHz, CW, 20 dBm
match, External PA supply = 3.3V
—
93.8
125.4
mA
F = 433 MHz, CW, 10 dBm
match, External PA supply connected to DC-DC output
—
20.3
24
mA
es
ig
ns
Test Condition
D
Symbol
N
ew
Parameter
—
34
41.5
mA
F = 315 MHz, CW, 14 dBm
match, External PA supply connected to DCDC output
—
33.5
42
mA
F = 169 MHz, CW, 20 dBm
match, External PA supply = 3.3V
—
88.6
116.7
mA
F = 2.4 GHz, CW, 0 dBm output
power, Radio clock prescaled by 3
—
8.5
—
mA
F = 2.4 GHz, CW, 0 dBm output
power, Radio clock prescaled by 1
—
9.5
—
mA
F = 2.4 GHz, CW, 3 dBm output
power
—
16.5
—
mA
F = 2.4 GHz, CW, 8 dBm output
power
—
26.0
—
mA
F = 2.4 GHz, CW, 10.5 dBm output power
—
34.0
—
mA
F = 2.4 GHz, CW, 16.5 dBm output power, PAVDD connected directly to external 3.3V supply
—
91.6
—
mA
F = 2.4 GHz, CW, 19.5 dBm output power, PAVDD connected directly to external 3.3V supply
—
131.0
—
mA
N
ot
R
ec
om
m
en
de
d
fo
r
F = 433 MHz, CW, 14 dBm
match, External PA supply connected to DCDC output
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Rev. 1.4 | 35
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Min
Typ
Max
Unit
Current consumption in
transmit mode (MCU in EM1
@ 38.4 MHz, peripheral
clocks disabled), T > 85 °C
ITX_HT
F = 915 MHz, CW, 20 dBm
match, External PA supply = 3.3V
—
—
134.3
mA
F = 915 MHz, CW, 14 dBm
match, External PA supply connected to DCDC output
—
—
42.5
mA
F = 868 MHz, CW, 20 dBm
match, External PA supply = 3.3V
—
—
109.8
mA
F = 868 MHz, CW, 14 dBm
match, External PA supply connected to DCDC output
—
—
41.3
mA
F = 490 MHz, CW, 20 dBm
match, External PA supply = 3.3V
—
—
130.8
mA
F = 433 MHz, CW, 10 dBm
match, External PA supply connected to DC-DC output
—
—
24.4
mA
es
ig
ns
Test Condition
D
Symbol
N
ew
Parameter
—
—
41.5
mA
F = 315 MHz, CW, 14 dBm
match, External PA supply connected to DCDC output
—
—
42
mA
—
—
122.8
mA
fo
r
F = 433 MHz, CW, 14 dBm
match, External PA supply connected to DCDC output
N
ot
R
ec
om
m
en
de
d
F = 169 MHz, CW, 20 dBm
match, External PA supply = 3.3V
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Rev. 1.4 | 36
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.6 Wake Up Times
Symbol
Wake up time from EM1
tEM1_WU
Wake up from EM2
tEM2_WU
Wake up from EM3
tEM3_WU
Test Condition
Min
Typ
Max
Unit
—
3
—
AHB
Clocks
10
—
µs
3
—
µs
10
—
µs
3
—
µs
86
—
µs
290
—
µs
Code execution from flash
—
Code execution from RAM
—
Code execution from flash
—
Code execution from RAM
—
tEM4H_WU
Executing from flash
—
Wake up from EM4S1
tEM4S_WU
Executing from flash
—
Time from release of reset
source to first instruction execution
tRESET
Soft Pin Reset released
Power mode scaling time
tSCALE
N
ew
Wake up from EM4H1
es
ig
ns
Parameter
D
Table 4.9. Wake Up Times
—
50
—
µs
—
340
—
µs
VSCALE0 to VSCALE2, HFCLK =
19 MHz2 3
—
31.8
—
µs
VSCALE2 to VSCALE0, HFCLK =
19 MHz4
—
4.3
—
µs
fo
r
Any other reset released
N
ot
R
ec
om
m
en
de
d
Note:
1. Time from wake up request until first instruction is executed. Wakeup results in device reset.
2. Scaling up from VSCALE0 to VSCALE2 requires approximately 30.3 µs + 28 HFCLKs.
3. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV/µs for approximately 20 µs. During this transition,
peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70 mA
(with a 2.7 µF capacitor).
4. Scaling down from VSCALE2 to VSCALE0 requires approximately 2.8 µs + 29 HFCLKs.
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Rev. 1.4 | 37
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.7 Brown Out Detector (BOD)
Table 4.10. Brown Out Detector (BOD)
Symbol
Test Condition
DVDD BOD threshold
VDVDDBOD
DVDD rising
Min
Typ
Max
Unit
—
—
1.62
V
—
—
V
—
—
V
18
—
mV
2.4
—
µs
—
1.8
V
DVDD falling (EM0/EM1)
1.35
DVDD falling (EM2/EM3)
1.3
DVDD BOD hysteresis
VDVDDBOD_HYST
—
DVDD BOD response time
tDVDDBOD_DELAY Supply drops at 0.1V/µs rate
—
AVDD BOD threshold
VAVDDBOD
—
1.62
—
—
V
AVDD falling (EM2/EM3)
1.53
—
—
V
—
20
—
mV
N
ew
AVDD falling (EM0/EM1)
D
AVDD rising
es
ig
ns
Parameter
AVDD BOD hysteresis
VAVDDBOD_HYST
AVDD BOD response time
tAVDDBOD_DELAY Supply drops at 0.1V/µs rate
—
2.4
—
µs
EM4 BOD threshold
VEM4DBOD
—
—
1.7
V
1.45
—
—
V
—
25
—
mV
—
300
—
µs
AVDD falling
VEM4BOD_HYST
EM4 BOD response time
tEM4BOD_DELAY
Supply drops at 0.1V/µs rate
N
ot
R
ec
om
m
en
de
d
EM4 BOD hysteresis
fo
r
AVDD rising
silabs.com | Building a more connected world.
Rev. 1.4 | 38
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.8 Frequency Synthesizer
Table 4.11. Frequency Synthesizer
Symbol
Test Condition
Min
Typ
Max
Unit
RF synthesizer frequency
range
fRANGE
2400 - 2483.5 MHz
2400
—
2483.5
MHz
779 - 956 MHz
779
—
956
MHz
584 - 717 MHz
584
—
717
MHz
358 - 574 MHz
358
—
574
MHz
191 - 358 MHz
191
—
358
MHz
110 - 191 MHz
110
—
191
MHz
2400 - 2483.5 MHz
—
D
fRES
—
73
Hz
779 - 956 MHz
—
—
24
Hz
—
—
18.3
Hz
—
—
12.2
Hz
—
—
7.3
Hz
—
—
4.6
Hz
2400 - 2483.5 MHz
—
—
73
Hz
779 - 956 MHz
—
—
24
Hz
584 - 717 MHz
—
—
18.3
Hz
358 - 574 MHz
—
—
12.2
Hz
191 - 358 MHz
—
—
7.3
Hz
110 - 191 MHz
—
—
4.6
Hz
2400 - 2483.5 MHz
—
—
1677
kHz
779 - 956 MHz
—
—
559
kHz
584 - 717 MHz
—
—
419
kHz
358 - 574 MHz
—
—
280
kHz
191 - 358 MHz
—
—
167
kHz
110 - 191 MHz
—
—
105
kHz
584 - 717 MHz
358 - 574 MHz
191 - 358 MHz
dfMAX
N
ot
R
ec
om
Maximum frequency deviation with 38.4 MHz crystal
dfRES
m
en
de
d
Frequency deviation resolution with 38.4 MHz crystal
fo
r
110 - 191 MHz
N
ew
LO tuning frequency resolution with 38.4 MHz crystal
es
ig
ns
Parameter
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Rev. 1.4 | 39
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.9 2.4 GHz RF Transceiver Characteristics
4.1.9.1 RF Transmitter General Characteristics for 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz.
Typ
Max
Unit
19.5
—
dBm
10.5
—
dBm
D
Parameter
Symbol
Test Condition
Min
Maximum TX power1
POUTMAX
19 dBm-rated part numbers.
PAVDD connected directly to external 3.3V supply
—
10 dBm-rated part numbers
—
-30
—
dBm
1
—
dB
—
0.5
—
dB
1.8 V < VVREGVDD < 3.3 V,
PAVDD connected directly to external supply, for output power >
10 dBm.
—
4.5
—
dB
1.8 V < VVREGVDD < 3.3 V,
PAVDD connected directly to external supply, for output power =
10 dBm.
—
3.8
—
dB
1.8 V < VVREGVDD < 3.3 V using
DC-DC converter
—
2.2
—
dB
From -40 to +85 °C, PAVDD connected to DC-DC output
—
1.5
—
dB
From -40 to +125 °C, PAVDD
connected to DC-DC output
—
2.6
—
dB
From -40 to +85 °C, PAVDD connected to external supply
—
1.5
—
dB
From -40 to +125 °C, PAVDD
connected to external supply
—
2.0
—
dB
Over RF tuning frequency range
—
0.4
—
dB
2400
—
2483.5
MHz
POUTMIN
CW
Output power step size
POUTSTEP
-5 dBm< Output power < 0 dBm
0 dBm < output power <
POUTMAX
POUTVAR_T
om
Output power variation vs
temperature at POUTMAX
m
en
de
d
fo
r
POUTVAR_V
ec
Output power variation vs RF POUTVAR_F
frequency at POUTMAX
FRANGE
R
RF tuning frequency range
—
N
ew
Minimum active TX Power
Output power variation vs
supply at POUTMAX
es
ig
ns
Table 4.12. RF Transmitter General Characteristics for 2.4 GHz Band
N
ot
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices covered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
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Rev. 1.4 | 40
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.9.2 RF Receiver General Characteristics for 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz.
Table 4.13. RF Receiver General Characteristics for 2.4 GHz Band
RF tuning frequency range
FRANGE
Receive mode maximum
spurious emission
SPURRX
Test Condition
Min
2400
—
1 GHz to 12 GHz
—
Max spurious emissions dur- SPURRX_FCC
ing active receive mode, per
FCC Part 15.109(a)
216 MHz to 960 MHz, Conducted
Measurement
—
Above 960 MHz, Conducted
Measurement
—
Level above which
RFSENSE will trigger1
RFSENSETRIG
CW at 2.45 GHz
—
Level below which
RFSENSE will not trigger1
RFSENSETHRES CW at 2.45 GHz
1% PER sensitivity
SENS2GFSK
2 Mbps 2GFSK signal
fo
r
250 kbps 2GFSK signal
Max
Unit
—
2483.5
MHz
-57
—
dBm
-47
—
dBm
-55.2
—
dBm
-47.2
—
dBm
-24
—
dBm
N
ew
30 MHz to 1 GHz
Typ
es
ig
ns
Symbol
D
Parameter
—
-50
—
dBm
—
-89.6
—
dBm
—
-100.7
—
dBm
N
ot
R
ec
om
m
en
de
d
Note:
1. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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Rev. 1.4 | 41
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.9.3 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4MHz. RF center frequency 2.45 GHz. Maximum duty cycle of
85%.
Test Condition
Max
Unit
Transmit 6dB bandwidth
TXBW
10 dBm
—
761
—
kHz
Power spectral density limit
PSDLIMIT
Per FCC part 15.247 at 10 dBm
—
-9.5
—
dBm/
3kHz
Per FCC part 15.247 at 20 dBm
—
-2
—
dBm/
3kHz
Per ETSI 300.328 at 10 dBm/1
MHz
—
10
—
dBm
Occupied channel bandwidth OCPETSI328
per ETSI EN300.328
99% BW at highest and lowest
channels in band, 10 dBm
—
1.1
—
MHz
In-band spurious emissions,
with allowed exceptions1
At ± 2 MHz, 10 dBm
—
-39.5
—
dBm
—
-44.3
—
dBm
—
—
-20
dBm
At ± 3 MHz, 20 dBm
—
—
-30
dBm
2nd,3rd, 5, 6, 8, 9,10 harmonics;
continuous transmission of modulated carrier
—
-47
—
dBm
Per FCC part 15.205/15.209,
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
CW carrier, Restricted Bands2 3
—
-47
—
dBm
Per FCC part 15.247, Above
2.483 GHz or below 2.4 GHz;
continuous transmission of CW
carrier, Non-Restricted Bands
—
-26
—
dBc
[2400-BW to 2400] MHz, [2483.5
to 2483.5+BW] MHz
—
-16
—
dBm
[2400-2BW to 2400-BW] MHz,
[2483.5+BW to 2483.5+2BW]
MHz per ETSI 300.328
—
-26
—
dBm
47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
—
-60
—
dBm
25-1000 MHz
—
-42
—
dBm
1-12 GHz
—
-36
—
dBm
At ± 3 MHz, 10 dBm
SPURHRM_FCC
Spurious emissions out-ofband, excluding harmonics
captured in SPURHARM,FCC.
Emissions taken at
POUTMAX, PAVDD connected to external 3.3 V supply
SPUROOB_FCC
Spurious emissions out-ofband; per ETSI 300.328
SPURETSI328
ec
om
m
en
de
d
Emissions of harmonics outof-band, per FCC part
15.247
fo
r
At ± 2 MHz, 20 dBm
Min
N
ot
R
Spurious emissions per ETSI SPURETSI440
EN300.440
es
ig
ns
Symbol
N
ew
Parameter
SPURINB
Typ
D
Table 4.14. RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate
Note:
1. Per Bluetooth Core_5.0, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a
frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.
2. For 2476 MHz, 1.5 dB of power backoff is used to achieve this value.
3. For 2478 MHz, 4.2 dB of power backoff is used to achieve this value.
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Rev. 1.4 | 42
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.9.4 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4MHz. RF center frequency 2.45 GHz.
Table 4.15. RF Receiver Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate
Test Condition
Min
Max usable receiver input
level, 0.1% BER
SAT
Signal is reference signal1. Packet
length is 20 bytes.
—
Sensitivity, 0.1% BER
SENS
Signal is reference signal1. Using
DC-DC converter.
—
With non-ideal signals as specified in RF-PHY.TS.4.2.2, section
4.6.1.
—
Signal to co-channel interfer- C/ICC
er, 0.1% BER
Desired signal 3 dB above reference sensitivity.
—
N+1 adjacent channel selec- C/I1+
tivity, 0.1% BER, with allowable exceptions. Desired is
reference signal at -67 dBm
Interferer is reference signal at +1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
—
N-1 adjacent channel selec- C/I1tivity, 0.1% BER, with allowable exceptions. Desired is
reference signal at -67 dBm
Interferer is reference signal at -1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
Alternate selectivity, 0.1%
BER, with allowable exceptions. Desired is reference
signal at -67 dBm
C/I2
Alternate selectivity, 0.1%
BER, with allowable exceptions. Desired is reference
signal at -67 dBm
C/I3
Typ
Max
Unit
es
ig
ns
Symbol
10
—
dBm
-93.8
—
dBm
-93.6
—
dBm
D
Parameter
—
dB
-4.7
—
dB
—
-4.8
—
dB
Interferer is reference signal at ± 2
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
—
-45.8
—
dB
Interferer is reference signal at ± 3
MHz offset. Desired frequency
2404 MHz ≤ Fc ≤ 2480 MHz
—
-49.4
—
dB
Selectivity to image frequen- C/IIM
cy, 0.1% BER. Desired is reference signal at -67 dBm
Interferer is reference signal at image frequency with 1 MHz precision
—
-40.5
—
dB
Selectivity to image frequency ± 1 MHz, 0.1% BER. Desired is reference signal at
-67 dBm
Interferer is reference signal at image frequency ± 1 MHz with 1
MHz precision
—
-49.4
—
dB
Interferer frequency 30 MHz ≤ f ≤
2000 MHz
-5
—
—
dBm
Interferer frequency 2003 MHz ≤ f
≤ 2399 MHz3
-10
—
—
dBm
Interferer frequency 2484 MHz ≤ f
≤ 2997 MHz
-10
—
—
dBm
Interferer frequency 3 GHz ≤ f ≤ 6
GHz
-10
—
—
dBm
Interferer frequency 6 GHz ≤ f ≤
12.75 GHz
-17
—
—
dBm
Per Core_4.1, Vol 6, Part A, Section 4.4 with n = 3
—
-22.2
—
dBm
N
ew
fo
r
m
en
de
d
ec
om
C/IIM+1
N
ot
R
Blocking, less than 0.1%
BLOCKOOB
BER. Desired is -67dBm
BLE reference signal at
2426MHz. Interferer is CW in
OOB range2
Intermodulation performance IM
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11.25
Rev. 1.4 | 43
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
es
ig
ns
Note:
1. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 1 Mbps, desired data = PRBS9;
interferer data = PRBS15; frequency accuracy better than 1 ppm.
2. Interferer max power limited by equipment capabilities and path loss. Minimum specified at 25 °C.
3. Except -13 dBm at Desired Frequency - Crystal Frequency.
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Rev. 1.4 | 44
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.9.5 RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz. Maximum duty cycle
of 66%.
Table 4.16. RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Symbol
Test Condition
Min
Typ
Max
Unit
3.8
—
% rms
-26
—
dBc/
100kHz
-36
—
dBm/
100kHz
-4.0
—
dBm/
3kHz
es
ig
ns
Parameter
Average across frequency. Signal
is DSSS-OQPSK reference packet1
—
Power spectral density limit
Relative, at carrier ± 3.5 MHz, output power at POUTMAX
—
Absolute, at carrier ± 3.5 MHz,
output power at POUTMAX2
—
Per FCC part 15.247, output power at POUTMAX
—
ETSI
—
12.1
—
dBm
N
ew
PSDLIMIT
D
Error vector magnitude (off- EVM
set EVM), per 802.15.4-2011
99% BW at highest and lowest
channels in band
—
2.25
—
MHz
Spurious emissions of harSPURHRM_FCC_
monics in restricted bands
R
per FCC Part 15.205/15.209,
Emissions taken at
POUTMAX, PAVDD connected to external 3.3 V supply,
Test Frequency is 2450 MHz
Continuous transmission of modulated carrier
—
-45.8
—
dBm
Spurious emissions of harSPURHRM_FCC_
monics in non-restricted
NRR
bands per FCC Part
15.247/15.35, Emissions taken at POUTMAX, PAVDD
connected to external 3.3 V
supply, Test Frequency is
2450 MHz
Continuous transmission of modulated carrier
—
-26
—
dBc
Spurious emissions out-ofband (above 2.483 GHz or
below 2.4 GHz) in restricted
bands, per FCC part
15.205/15.209, Emissions
taken at POUTMAX, PAVDD
connected to external 3.3 V
supply, Test Frequency =
2450 MHz
Restricted bands 30-88 MHz; continuous transmission of modulated
carrier
—
-61
—
dBm
Restricted bands 88-216 MHz;
continuous transmission of modulated carrier
—
-58
—
dBm
Restricted bands 216-960 MHz;
continuous transmission of modulated carrier
—
-55
—
dBm
Restricted bands >960 MHz; continuous transmission of modulated
carrier3 4
—
-47
—
dBm
m
en
de
d
fo
r
Occupied channel bandwidth OCPETSI328
per ETSI EN300.328
om
SPUROOB_FCC_
N
ot
R
ec
R
silabs.com | Building a more connected world.
Rev. 1.4 | 45
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Test Condition
Min
Typ
Max
Unit
-26
—
dBc
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
modulated carrier
—
Spurious emissions out-ofband; per ETSI 300.3285
[2400-BW to 2400], [2483.5 to
2483.5+BW];
—
[2400-2BW to 2400-BW],
[2483.5+BW to 2483.5+2BW]; per
ETSI 300.328
—
47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
—
25-1000 MHz, excluding above
frequencies
—
SPURETSI328
Spurious emissions per ETSI SPURETSI440
EN300.4405
-16
—
dBm
-26
—
dBm
-60
—
dBm
—
dBm
—
dBm
-42
N
ew
SPUROOB_FCC_
Spurious emissions out-ofband in non-restricted bands NR
per FCC Part 15.247, Emissions taken at POUTMAX,
PAVDD connected to external 3.3 V supply, Test Frequency = 2450 MHz
es
ig
ns
Symbol
D
Parameter
1G-14G
—
-36
N
ot
R
ec
om
m
en
de
d
fo
r
Note:
1. Reference packet is defined as 20 octet PSDU, modulated according to 802.15.4-2011 DSSS-OQPSK in the 2.4GHz band, with
pseudo-random packet data content.
2. For 2415 MHz, 2 dB of power backoff is used to achieve this value.
3. For 2475 MHz, 2 dB of power backoff is used to achieve this value.
4. For 2480 MHz, 13 dB of power backoff is used to achieve this value.
5. Specified at maximum power output level of 10 dBm.
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Rev. 1.4 | 46
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.9.6 RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz.
Table 4.17. RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Test Condition
Min
Max usable receiver input
level, 1% PER
SAT
Signal is reference signal1. Packet
length is 20 octets.
—
Sensitivity, 1% PER
SENS
Signal is reference signal. Packet
length is 20 octets. Using DC-DC
converter.
Typ
Max
Unit
es
ig
ns
Symbol
10
—
dBm
—
-103.3
—
dBm
Signal is reference signal. Packet
length is 20 octets. Without DCDC converter.
—
-103.3
—
dBm
D
Parameter
—
dB
CCR
Desired signal 3 dB above sensitivity limit
—
High-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
level2
ACRP1
Interferer is reference signal at +1
channel-spacing.
—
40.7
—
dB
Interferer is filtered reference signal3 at +1 channel-spacing.
—
47
—
dB
Interferer is CW at +1 channelspacing4.
—
60.1
—
dB
Interferer is reference signal at -1
channel-spacing.
—
40.8
—
dB
Interferer is filtered reference signal3 at -1 channel-spacing.
—
47.5
—
dB
Interferer is CW at -1 channelspacing.
—
61.6
—
dB
Interferer is reference signal at ± 2
channel-spacing
—
51.5
—
dB
Interferer is filtered reference signal3 at ± 2 channel-spacing
—
53.7
—
dB
Interferer is CW at ± 2 channelspacing
—
66.4
—
dB
Interferer is CW in image band4
—
50.4
—
dB
Blocking rejection of all other BLOCK
channels. 1% PER, Desired
is reference signal at 3dB
above reference sensitivity
level2. Interferer is reference
signal
Interferer frequency < Desired frequency - 3 channel-spacing
—
58.5
—
dB
Interferer frequency > Desired frequency + 3 channel-spacing
—
56.4
—
dB
Blocking rejection of 802.11g BLOCK80211G
signal centered at +12MHz
or -13MHz5
Desired is reference signal at 6dB
above reference sensitivity level2
—
54.8
—
dB
ACR2
om
Alternate channel rejection,
1% PER. Desired is reference signal at 3dB above
reference sensitivity level2
fo
r
ACRM1
m
en
de
d
Low-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
level2
N
ot
R
ec
Image rejection , 1% PER,
IR
Desired is reference signal at
3dB above reference sensitivity level2
-4.6
N
ew
Co-channel interferer rejection, 1% PER
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Rev. 1.4 | 47
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Symbol
Min
Typ
Max
Unit
RSSIMAX
Upper limit of input power
range over which RSSI resolution is maintained
—
—
5
dBm
RSSIMIN
Lower limit of input power
range over which RSSI resolution is maintained
-98
—
—
dBm
RSSI resolution
RSSIRES
RSSI accuracy in the linear
region as defined by
802.15.4-2003
RSSILIN
Test Condition
over RSSIMIN to RSSIMAX
—
—
es
ig
ns
Parameter
0.25
—
dB
+/-6
—
dB
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
Note:
1. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksymbols/s.
2. Reference sensitivity level is -85 dBm.
3. Filter is characterized as a symmetric bandpass centered on the adjacent channel having a 3dB bandwidth of 4.6 MHz and stopband rejection better than 26 dB beyond 3.15 MHz from the adjacent carrier.
4. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker
tests place the Interferer center frequency at the Desired frequency ± 5 MHz on the channel raster, whereas the image rejection
test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster.
5. This is an IEEE 802.11b/g ERP-PBCC 22 MBit/s signal as defined by the IEEE 802.11 specification and IEEE 802.11g addendum.
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Rev. 1.4 | 48
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
es
ig
ns
4.1.10 Sub-GHz RF Transceiver Characteristics
silabs.com | Building a more connected world.
Rev. 1.4 | 49
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.10.1 Sub-GHz RF Transmitter characteristics for 915 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 915 MHz.
Table 4.18. Sub-GHz RF Transmitter characteristics for 915 MHz Band
Symbol
RF tuning frequency range
FRANGE
Maximum TX Power1
POUTMAX
Test Condition
Min
902
External PA supply = 3.3V, 20
dBm output power setting
External PA supply connected to
DC-DC output, 14 dBm output
power setting
18
12.6
Max
Unit
—
930
MHz
19.8
23.3
dBm
14.2
16.1
dBm
-45.5
—
dBm
0.5
—
dB
POUTMIN
Output power step size
POUTSTEP
output power > 0 dBm
Output power variation vs
supply at POUTMAX
POUTVAR_V
1.8 V < VVREGVDD < 3.3 V, External PA supply = 3.3 V, T = 25 °C
—
4.8
—
dB
1.8 V < VVREGVDD < 3.3 V, External PA supply connected to DCDC output, T = 25 °C
—
1.9
—
dB
-40 to +85 °C with External PA
supply = 3.3 V
—
0.6
1.3
dB
-40 to +125 °C with External PA
supply = 3.3 V
—
0.8
1.6
dB
-40 to +85 °C with External PA
supply connected to DC-DC output
—
0.7
1.4
dB
-40 to +125 °C with External PA
supply connected to DC-DC output
—
1.0
1.9
dB
External PA supply = 3.3 V, T =
25 °C
—
0.2
0.6
dB
External PA supply connected to
DC-DC output, T = 25 °C
—
0.3
0.6
dB
SPURHARM_FCC In restricted bands, per FCC Part
15.205 / 15.209
—
-45
-42
dBm
—
-26
-20
dBc
N
ew
fo
r
m
en
de
d
POUTVAR_T
—
om
Output power variation vs RF POUTVAR_F
frequency
_20
In non-restricted bands, per FCC
Part 15.247
N
ot
R
ec
Spurious emissions of harmonics at 20 dBm output
power, Conducted measurement, 20dBm match, External PA supply = 3.3V, Test
Frequency = 915 MHz
D
Minimum active TX Power
Output power variation vs
temperature, peak to peak
—
Typ
es
ig
ns
Parameter
silabs.com | Building a more connected world.
Rev. 1.4 | 50
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Typ
Max
Unit
In non-restricted bands, per FCC
Part 15.247
—
-26
-20
dBc
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
—
-62
-56
dBm
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
—
-61
-56
dBm
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
—
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
—
-52
dBm
-47
-42
dBm
-47
-42
dBm
-20
dBc
SPURHARM_FCC In restricted bands, per FCC Part
15.205 / 15.209
_14
—
In non-restricted bands, per FCC
Part 15.247
—
In non-restricted bands, per FCC
Part 15.247
—
-26
-20
dBc
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
—
-62
-56
dBm
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
—
-61
-56
dBm
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
—
-58
-52
dBm
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
—
-45
-42
dBm
Signal is DSSS-OQPSK reference
packet. Modulated according to
802.15.4-2011 DSSS-OQPSK in
the 915MHz band, with pseudorandom packet data content. External PA supply = 3.3V.
—
1.0
2.8
%rms
Relative, at carrier ± 1.2 MHz.
Average spectral power shall be
measured using a 100kHz resolution bandwidth. The reference level shall be the highest average
spectral power measured within ±
600kHz of the carrier frequency.
External PA supply = 3.3V.
—
-37.1
-24.8
dBc/
100kHz
Absolute, at carrier ± 1.2 MHz.
Average spectral power shall be
measured using a 100kHz resolution bandwidth. External PA supply = 3.3V.
—
-24.2
-20
dBm/
100kHz
m
en
de
d
Spurious emissions out-ofSPUROOB_FCC_
band at 14 dBm output pow- 14
er, Conducted measurement,
14dBm match, External PA
supply connected to DC-DC
output, Test Frequency =
915 MHz
om
Error vector magnitude (off- EVM
set EVM), per 802.15.4-2011
PSD
N
ot
R
ec
Power spectral density limit2
-58
silabs.com | Building a more connected world.
-26
N
ew
Spurious emissions of harmonics at 14 dBm output
power, Conducted measurement, 14dBm match, External PA supply connected to
DC-DC output, Test Frequency = 915 MHz
Min
es
ig
ns
SPUROOB_FCC_
Spurious emissions out-ofband at 20 dBm output pow- 20
er, Conducted measurement,
20dBm match, External PA
supply = 3.3V, Test Frequency = 915 MHz
Test Condition
D
Symbol
fo
r
Parameter
Rev. 1.4 | 51
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
es
ig
ns
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices covered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
2. Definition of reference signal is O-QPSK DSSS per 802.15.4, Frequency Range = 902-928 MHz, Data rate = 250 kbps, 16-chip
PN sequence mapping.
silabs.com | Building a more connected world.
Rev. 1.4 | 52
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.10.2 Sub-GHz RF Receiver Characteristics for 915 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 915 MHz.
Table 4.19. Sub-GHz RF Receiver Characteristics for 915 MHz Band
Symbol
Tuning frequency range
FRANGE
Test Condition
Min
902
Typ
Max
Unit
es
ig
ns
Parameter
—
930
MHz
10
—
dBm
Desired is reference 500 kbps
GFSK signal1
—
Sensitivity
Desired is reference 4.8 kbps
OOK signal2, 20% PER, T ≤ 85 °C
—
-107.8
-100.7
dBm
Desired is reference 4.8 kbps
OOK signal2, 20% PER, T > 85
°C
—
—
-99.5
dBm
Desired is reference 600 bps
GFSK signal3, 0.1% BER
—
-126.2
—
dBm
Desired is reference 50 kbps
GFSK signal4, 0.1% BER, T ≤ 85
°C
—
-108.2
-104.2
dBm
Desired is reference 50 kbps
GFSK signal4, 0.1% BER, T > 85
°C
—
—
-103.1
dBm
Desired is reference 100 kbps
GFSK signal5, 0.1% BER, T ≤ 85
°C
—
-105.1
-101.5
dBm
Desired is reference 100 kbps
GFSK signal5, 0.1% BER, T > 85
°C
—
—
-101.3
dBm
Desired is reference 500 kbps
GFSK signal1, 0.1% BER, T ≤ 85
°C
—
-98.2
-93.2
dBm
Desired is reference 500 kbps
GFSK signal1, 0.1% BER, T > 85
°C
—
—
-93.1
dBm
Desired is reference 400 kbps
4GFSK signal6, 1% PER, T ≤ 85
°C
—
-95.2
-91
dBm
Desired is reference 400 kbps
4GFSK signal6, 1% PER, T > 85
°C
—
—
-91
dBm
Desired is reference O-QPSK
DSSS signal7, 1% PER, Payload
length is 20 octets
—
-100.1
—
dBm
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
SENS
D
Max usable input level, 0.1% SAT500K
BER
Level above which
RFSENSE will trigger8
RFSENSETRIG
CW at 915 MHz
—
-28.1
—
dBm
Level below which
RFSENSE will not trigger8
RFSENSETHRES CW at 915 MHz
—
-50
—
dBm
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Rev. 1.4 | 53
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Min
Typ
Max
Unit
Adjacent channel selectivity,
Interferer is CW at ± 1 ×
channel-spacing
C/I1
Desired is 4.8 kbps OOK signal2
at 3dB above sensitivity level,
20% PER
—
48.1
—
dB
Desired is 600 bps GFSK signal3
at 3dB above sensitivity level,
0.1% BER
—
71.4
—
dB
Desired is 50 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
—
Desired is 100 kbps GFSK signal5
at 3dB above sensitivity level,
0.1% BER
—
Desired is 500 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
—
es
ig
ns
Test Condition
49.8
—
dB
51.1
—
dB
48.1
—
dB
D
Symbol
N
ew
Parameter
41.4
—
dB
Desired is reference O-QPSK
DSSS signal7 at 3dB above sensitivity level, 1% PER
—
49.1
—
dB
Desired is 4.8 kbps OOK signal2
at 3dB above sensitivity level,
20% PER
—
56.3
—
dB
Desired is 600 bps GFSK signal3
at 3dB above sensitivity level,
0.1% BER
—
74.7
—
dB
Desired is 50 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
—
55.8
—
dB
Desired is 100 kbps GFSK signal5
at 3dB above sensitivity level,
0.1% BER
—
56.4
—
dB
Desired is 500 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
—
51.8
—
dB
Desired is 400 kbps 4GFSK signal6 at 3dB above sensitivity level,
0.1% BER
—
46.8
—
dB
Desired is reference O-QPSK
DSSS signal7 at 3dB above sensitivity level, 1% PER
—
57.7
—
dB
fo
r
—
N
ot
R
ec
om
m
en
de
d
Alternate channel selectivity, C/I2
Interferer is CW at ± 2 ×
channel-spacing
Desired is 400 kbps 4GFSK signal6 at 3dB above sensitivity level,
0.1% BER
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Rev. 1.4 | 54
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Min
Typ
Max
Unit
Image rejection, Interferer is
CW at image frequency
C/IIMAGE
Desired is 4.8 kbps OOK signal2
at 3dB above sensitivity level,
20% PER
—
48.4
—
dB
Desired is 50 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
—
54.9
—
dB
Desired is 100 kbps GFSK signal5
at 3dB above sensitivity level,
0.1% BER
—
Desired is 500 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
—
Desired is 400 kbps 4GFSK signal6 at 3dB above sensitivity level,
0.1% BER
—
es
ig
ns
Test Condition
49.1
—
dB
47.9
—
dB
42.8
—
dB
D
Symbol
N
ew
Parameter
—
48.9
—
dB
Interferer CW at Desired ± 1 MHz
—
58.7
—
dB
Interferer CW at Desired ± 2 MHz
—
62.5
—
dB
Interferer CW at Desired ± 10
MHz
—
76.4
—
dB
Desired is 100 kbps GFSK signal5
at 3dB above sensitivity level
—
45
—
dB
Upper limit of input power
RSSIMAX
range over which RSSI resolution is maintained
—
—
5
dBm
Lower limit of input power
RSSIMIN
range over which RSSI resolution is maintained
-98
—
—
dBm
Over RSSIMIN to RSSIMAX range
—
0.25
—
dBm
Max spurious emissions dur- SPURRX_FCC
ing active receive mode, per
FCC Part 15.109(a)
216-960 MHz
—
-55
-49.2
dBm
Above 960 MHz
—
-47
-41.2
dBm
Max spurious emissions dur- SPURRX_ARIB
ing active receive mode,per
ARIB STD-T108 Section 3.3
Below 710 MHz, RBW=100kHz
—
-60
-54
dBm
710-900 MHz, RBW=1MHz
—
-61
-55
dBm
900-915 MHz, RBW=100kHz
—
-61
-55
dBm
915-930 MHz, RBW=100kHz
—
-61
-55
dBm
930-1000 MHz, RBW=100kHz
—
-61
-55
dBm
Above 1000 MHz, RBW=1MHz
—
-53
-47
dBm
C/IBLOCKER
Intermod selectivity, 0.1%
BER. CW interferers at 400
kHz and 800 kHz offsets
C/IIM
RSSIRES
N
ot
R
ec
om
RSSI resolution
m
en
de
d
Blocking selectivity, 0.1%
BER. Desired is 100 kbps
GFSK signal at 3dB above
sensitivity level
fo
r
Desired is reference O-QPSK
DSSS signal7 at 3dB above sensitivity level, 1% PER
silabs.com | Building a more connected world.
Rev. 1.4 | 55
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
es
ig
ns
Note:
1. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 175 kHz, RX channel BW = 835.076 kHz, channel spacing = 1
MHz.
2. Definition of reference signal is 4.8 kbps OOK, RX channel BW = 306.036 kHz, channel spacing = 500 kHz.
3. Definition of reference signal is 600 bps 2GFSK, BT=0.5, Δf = 0.3 kHz, RX channel BW = 1.2 kHz, channel spacing = 300 kHz.
4. Definition of reference signal is 50 kbps 2GFSK, BT=0.5, Δf = 25 kHz, RX channel BW = 99.012 kHz, channel spacing = 200 kHz.
5. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 198.024 kHz, channel spacing = 400
kHz.
6. Definition of reference signal is 400 kbps 4GFSK, BT=0.5, inner deviation = 33.3 kHz, RX channel BW = 368.920 kHz, channel
spacing = 600 kHz.
7. Definition of reference signal is O-QPSK DSSS per 802.15.4, Frequency Range = 902-928 MHz, Data rate = 250 kbps, 16-chip
PN sequence mapping.
8. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
silabs.com | Building a more connected world.
Rev. 1.4 | 56
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.10.3 Sub-GHz RF Transmitter characteristics for 868 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 868 MHz.
Table 4.20. Sub-GHz RF Transmitter characteristics for 868 MHz Band
RF tuning frequency range
FRANGE
Maximum TX Power1
POUTMAX
Test Condition
Min
863
Typ
Max
Unit
es
ig
ns
Symbol
—
876
MHz
19.3
22.9
dBm
13.7
16.5
dBm
—
D
Parameter
-43.5
—
dBm
—
0.5
—
dB
External PA connected directly to
3.3V supply, 20 dBm output power setting
17.1
External PA supply connected to
DC-DC output, 14 dBm output
power setting
11.4
POUTMIN
Output power step size
POUTSTEP
output power > 0 dBm
Output power variation vs
supply at POUTMAX
POUTVAR_V
1.8 V < VVREGVDD < 3.3 V, External PA supply = 3.3 V, T = 25 °C
—
5
—
dB
1.8 V < VVREGVDD < 3.3 V, External PA supply connected to DCDC output, T = 25 °C
—
2
—
dB
-40 to +85 °C with External PA
supply = 3.3 V
—
0.6
0.9
dB
-40 to +125 °C with External PA
supply = 3.3 V
—
0.8
1.3
dB
-40 to +85 °C with External PA
supply connected to DC-DC output
—
0.5
1.2
dB
-40 to +125 °C with External PA
supply connected to DC-DC output
—
0.7
1.5
dB
External PA supply = 3.3 V, T =
25 °C
—
0.2
0.6
dB
External PA supply connected to
DC-DC output, T = 25 °C
—
0.2
0.8
dB
SPURHARM_ETSI Per ETSI EN 300-220, Section
7.8.2.1, External PA supply connected to: DCDC at 14 dBm, or
3.3 V at 19.5 dBm
—
-35
-30
dBm
fo
r
POUTVAR_T
m
en
de
d
Output power variation vs
temperature, peak to peak
N
ew
Minimum active TX Power
om
Output power variation vs RF POUTVAR_F
frequency
N
ot
R
ec
Spurious emissions of harmonics, Conducted measurement, Test Frequency =
868 MHz
silabs.com | Building a more connected world.
Rev. 1.4 | 57
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Spurious emissions out-ofband, Conducted measurement, Test Frequency = 868
MHz
SPUROOB_ETSI
Error vector magnitude (off- EVM
set EVM), per 802.15.4-2015
Min
Typ
Max
Unit
Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz), External PA supply connected to: DCDC at 14 dBm, or 3.3 V
at 19.5 dBm
—
-59
-54
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz), External PA supply connected to: DCDC at 14 dBm, or 3.3 V
at 19.5 dBm
—
-42
-36
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz), External PA supply connected to: DCDC at 14 dBm, or 3.3 V
at 19.5 dBm
—
-36
-30
dBm
Signal is DSSS-BPSK reference
packet. Modulated according to
802.15.4-2015 DSSS-BPSK in the
868MHz band, with pseudo-random packet data content. External
PA supply connected to external
3.3V supply
—
—
%rms
es
ig
ns
Test Condition
D
Symbol
5.7
N
ew
Parameter
N
ot
R
ec
om
m
en
de
d
fo
r
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices covered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
silabs.com | Building a more connected world.
Rev. 1.4 | 58
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.10.4 Sub-GHz RF Receiver Characteristics for 868 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 868 MHz.
Table 4.21. Sub-GHz RF Receiver Characteristics for 868 MHz Band
Symbol
Tuning frequency range
FRANGE
Test Condition
Min
863
Typ
Max
Unit
es
ig
ns
Parameter
—
876
MHz
10
—
dBm
10
—
dBm
-120.6
—
dBm
-105.4
dBm
Desired is reference 2.4 kbps
GFSK signal1
—
Max usable input level, 0.1% SAT38k4
BER
Desired is reference 38.4 kbps
GFSK signal2
—
Sensitivity
Desired is reference 2.4 kbps
GFSK signal1, 0.1% BER
—
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER, T ≤ 85
°C
—
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER, T > 85
°C
—
—
-105.2
dBm
Desired is reference 500 kbps
GFSK signal3, 0.1% BER
—
-96.4
—
dBm
CW at 868 MHz
—
-28.1
—
dBm
—
-50
—
dBm
Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
44.5
56.9
—
dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
35.4
43
—
dB
Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
—
56.8
—
dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
—
48.2
—
dB
Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
—
50.2
—
dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
—
48.7
—
dB
Interferer CW at Desired ± 1 MHz
—
72.1
—
dB
Interferer CW at Desired ± 2 MHz
—
77.5
—
dB
Interferer CW at Desired ± 10
MHz
—
90.4
—
dB
-109.5
fo
r
N
ew
SENS
D
Max usable input level, 0.1% SAT2k4
BER
RFSENSETRIG
Level below which
RFSENSE will not trigger4
RFSENSETHRES CW at 868 MHz
Adjacent channel selectivity,
Interferer is CW at ± 1 ×
channel-spacing
C/I1
m
en
de
d
Level above which
RFSENSE will trigger4
ec
om
Alternate channel selectivity, C/I2
Interferer is CW at ± 2 ×
channel-spacing
N
ot
R
Image rejection, Interferer is
CW at image frequency
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal1 at 3 dB above
sensitivity level
C/IIMAGE
C/IBLOCKER
silabs.com | Building a more connected world.
Rev. 1.4 | 59
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Symbol
Min
Typ
Max
Unit
RSSIMAX
Upper limit of input power
range over which RSSI resolution is maintained
—
—
5
dBm
RSSIMIN
Lower limit of input power
range over which RSSI resolution is maintained
-98
—
—
dBm
RSSI resolution
RSSIRES
Max spurious emissions dur- SPURRX
ing active receive mode
Test Condition
Over RSSIMIN to RSSIMAX range
—
30 MHz to 1 GHz
—
1 GHz to 12 GHz
—
es
ig
ns
Parameter
0.25
—
dBm
-63
-57
dBm
-53
-47
dBm
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.797 kHz, channel spacing = 12.5
kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100
kHz.
3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 753.320 kHz.
4. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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Rev. 1.4 | 60
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.10.5 Sub-GHz RF Transmitter characteristics for 490 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 490 MHz.
Table 4.22. Sub-GHz RF Transmitter characteristics for 490 MHz Band
Symbol
Test Condition
Min
RF tuning frequency range
FRANGE
Maximum TX Power1
POUTMAX
Minimum active TX Power
POUTMIN
Output power step size
POUTSTEP
output power > 0 dBm
—
Output power variation vs
supply, peak to peak
POUTVAR_V
at 20 dBm;1.8 V < VVREGVDD <
3.3 V, External PA supply connected directly to external supply, T =
25 °C
—
Output power variation vs
temperature, peak to peak
POUTVAR_T
-40 to +85 °C at 20 dBm
470
-40 to +125 °C at 20 dBm
Unit
510
MHz
20.3
23.7
dBm
-44.9
—
dBm
0.5
—
dB
4.3
—
dB
D
18.1
Max
—
N
ew
External PA supply = 3.3V
Typ
es
ig
ns
Parameter
—
0.2
0.9
dB
—
0.3
1.3
dB
—
0.2
0.4
dB
T = 25 °C
Harmonic emissions, 20
dBm output power setting,
490 MHz
Per China SRW Requirement,
Section 2.1, frequencies below
1GHz
—
-40
-36
dBm
Per China SRW Requirement,
Section 2.1, frequencies above
1GHz
—
-36
-30
dBm
Per China SRW Requirement,
Section 3 (48.5-72.5MHz,
76-108MHz, 167-223MHz,
470-556MHz, and 606-798MHz)
—
-54
—
dBm
Per China SRW Requirement,
Section 2.1 (other frequencies below 1GHz)
—
-42
—
dBm
Per China SRW Requirement,
Section 2.1 (frequencies above
1GHz)
—
-36
—
dBm
m
en
de
d
SPURHARM_CN
fo
r
Output power variation vs RF POUTVAR_F
frequency
om
Spurious emissions, 20 dBm SPUROOB_CN
output power setting, 490
MHz
N
ot
R
ec
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices covered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
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Rev. 1.4 | 61
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.10.6 Sub-GHz RF Receiver Characteristics for 490 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 490 MHz.
Table 4.23. Sub-GHz RF Receiver Characteristics for 490 MHz Band
Symbol
Tuning frequency range
FRANGE
Test Condition
Min
470
Typ
Max
Unit
es
ig
ns
Parameter
—
510
MHz
10
—
dBm
10
—
dBm
-122.2
—
dBm
-108.9
dBm
Desired is reference 2.4 kbps
GFSK signal1
—
Max usable input level, 0.1% SAT38k4
BER
Desired is reference 38.4 kbps
GFSK signal2
—
Sensitivity
Desired is reference 2.4 kbps
GFSK signal1, 0.1% BER
—
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER, T ≤ 85
°C
—
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER, T > 85
°C
—
—
-107.9
dBm
Desired is reference 10 kbps
GFSK signal3, 0.1% BER, T ≤ 85
°C
—
-116.8
-113.9
dBm
Desired is reference 10 kbps
GFSK signal3, 0.1% BER, T > 85
°C
—
—
-113.2
dBm
Desired is reference 100 kbps
GFSK signal4, 0.1% BER, T ≤ 85
°C
—
-107.3
-104.7
dBm
Desired is reference 100 kbps
GFSK signal4, 0.1% BER, T > 85
°C
—
—
-104
dBm
Desired is reference 100 kbps
GFSK signal4, 0.1% BER
—
-28.1
—
dBm
—
-50
—
dBm
Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
48
60.3
—
dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
38.3
45.6
—
dB
Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
—
60.4
—
dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
—
52.6
—
dB
-111.4
m
en
de
d
fo
r
N
ew
SENS
D
Max usable input level, 0.1% SAT2k4
BER
RFSENSETRIG
Level below which
RFSENSE will not trigger5
RFSENSETHRES CW at 490 MHz
ec
om
Level above which
RFSENSE will trigger5
C/I1
N
ot
R
Adjacent channel selectivity,
Interferer is CW at ± 1 ×
channel-spacing
Alternate channel selectivity, C/I2
Interferer is CW at ± 2 ×
channel-spacing
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Test Condition
Image rejection, Interferer is
CW at image frequency
C/IIMAGE
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal1 at 3 dB above
sensitivity level
C/IBLOCKER
Min
Typ
Max
Unit
Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
—
56.5
—
dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
—
54.1
—
dB
Interferer CW at Desired ± 1 MHz
—
Interferer CW at Desired ± 2 MHz
—
Interferer CW at Desired ± 10
MHz
—
—
RSSIMIN
Lower limit of input power
range over which RSSI resolution is maintained
-98
RSSI resolution
RSSIRES
—
dB
75.4
—
dB
90.2
—
dB
—
5
dBm
—
dBm
—
Over RSSIMIN to RSSIMAX range
—
0.25
—
dBm
30 MHz to 1 GHz
—
-53
-47
dBm
—
-53
-47
dBm
1 GHz to 12 GHz
fo
r
Max spurious emissions dur- SPURRX
ing active receive mode
73.9
N
ew
RSSIMAX
Upper limit of input power
range over which RSSI resolution is maintained
es
ig
ns
Symbol
D
Parameter
N
ot
R
ec
om
m
en
de
d
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5
kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100
kHz.
3. Definition of reference signal is 10 kbps 2GFSK, BT=0.5, Δf = 5 kHz, RX channel BW = 20.038 kHz.
4. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 198.024 kHz.
5. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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Rev. 1.4 | 63
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.10.7 Sub-GHz RF Transmitter characteristics for 433 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 433 MHz.
Table 4.24. Sub-GHz RF Transmitter characteristics for 433 MHz Band
FRANGE
Maximum TX Power1
POUTMAX
Minimum active TX Power
POUTMIN
Output power step size
POUTSTEP
Min
426
Max
Unit
—
445
MHz
15.1
17.4
dBm
10.6
13.3
dBm
—
-42
—
dBm
—
0.5
—
dB
External PA supply connected to
DC-DC output, 14dBm output
power
12.5
External PA supply connected to
DC-DC output, 10dBm output
power
8.3
output power > 0 dBm
Typ
es
ig
ns
RF tuning frequency range
Test Condition
D
Symbol
N
ew
Parameter
At 10 dBm;1.8 V < VVREGVDD <
3.3 V, External PA supply = DCDC output, T = 25 °C
—
1.7
—
dB
Output power variation vs
temperature, peak to peak,
Pout= 10dBm
-40 to +85C at 10dBm
—
0.5
1.2
dB
-40 to +125C at 10dBm
—
0.7
1.7
dB
T = 25 °C
—
0.1
0.2
dB
POUTVAR_T
Output power variation vs RF POUTVAR_F
frequency, Pout = 10dBm
fo
r
Output power variation vs
POUTVAR_V
supply, peak to peak, Pout =
10dBm
SPURHARM_FCC In restricted bands, per FCC Part
15.205 / 15.209
—
-47
-42
dBm
In non-restricted bands, per FCC
Part 15.231
—
-26
-20
dBc
Spurious emissions out-ofband FCC, Conducted
measurement, 14dBm
match, External PA supply
connected to DC-DC output,
Test Frequency = 434 MHz
SPUROOB_FCC
In non-restricted bands, per FCC
Part 15.231
—
-26
-20
dBc
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
—
-52
-46
dBm
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
—
-61
-56
dBm
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
—
-58
-52
dBm
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
—
-47
-42
dBm
SPURHARM_ETSI Per ETSI EN 300-220, Section
7.8.2.1 (frequencies below 1Ghz)
—
-42
-36
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1Ghz)
—
-36
-30
dBm
R
ec
om
m
en
de
d
Spurious emissions of harmonics FCC, Conducted
measurement, 14dBm
match, External PA supply
connected to DC-DC output,
Test Frequency = 434 MHz
N
ot
Spurious emissions of harmonics ETSI, Conducted
measurement, 14dBm
match, External PA supply
connected to DC-DC output,
Test Frequency = 434 MHz
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Rev. 1.4 | 64
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Symbol
Test Condition
Min
Typ
Max
Unit
Spurious emissions out-ofband ETSI, Conducted
measurement, 14dBm
match, External PA supply
connected to DC-DC output,
Test Frequency = 434 MHz
SPUROOB_ETSI
Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz)
—
-60
-54
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz)
—
-42
-36
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz)
—
es
ig
ns
Parameter
-36
-30
dBm
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices covered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
silabs.com | Building a more connected world.
Rev. 1.4 | 65
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.10.8 Sub-GHz RF Receiver Characteristics for 433 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 433 MHz.
Table 4.25. Sub-GHz RF Receiver Characteristics for 433 MHz Band
Symbol
Tuning frequency range
FRANGE
Test Condition
Min
426
Typ
Max
Unit
es
ig
ns
Parameter
—
445
MHz
10
—
dBm
10
—
dBm
-109.9
—
dBm
-105
dBm
Desired is reference 2.4 kbps
GFSK signal1
—
Max usable input level, 0.1% SAT50k
BER
Desired is reference 50 kbps
GFSK signal2
—
Sensitivity
Desired is reference 4.8 kbps
OOK signal3, 20% PER
—
Desired is reference 100 kbps
GFSK signal4, 0.1% BER, T ≤ 85
°C
—
Desired is reference 100 kbps
GFSK signal4, 0.1% BER, T > 85
°C
—
—
-104
dBm
Desired is reference 50 kbps
GFSK signal2, 0.1% BER, T ≤ 85
°C
—
-110.3
-107.2
dBm
Desired is reference 50 kbps
GFSK signal2, 0.1% BER, T > 85
°C
—
—
-106.6
dBm
Desired is reference 2.4 kbps
GFSK signal1, 0.1% BER
—
-123.1
—
dBm
Desired is reference 9.6 kbps
GFSK signal5, 1% PER, T ≤ 85 °C
-112.6
-109
dBm
Desired is reference 9.6 kbps
GFSK signal5, 1% PER, T > 85 °C
—
—
-108
dBm
-107.3
RFSENSETRIG
CW at 433 MHz
—
-28.1
—
dBm
Level below which
RFSENSE will not trigger6
RFSENSETHRES CW at 433 MHz
—
-50
—
dBm
N
ot
R
ec
om
—
Level above which
RFSENSE will trigger6
m
en
de
d
fo
r
N
ew
SENS
D
Max usable input level, 0.1% SAT2k4
BER
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Rev. 1.4 | 66
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Test Condition
Min
Typ
Max
Unit
Adjacent channel selectivity,
Interferer is CW at ± 1 ×
channel-spacing
C/I1
Desired is 4.8 kbps OOK signal3
at 3dB above sensitivity level,
20% PER
—
51.6
—
dB
Desired is 100 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
35
44.1
—
dB
Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
47
Desired is 50 kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
45.6
ec
R
N
ot
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal1 at 3dB above
sensitivity level
C/IBLOCKER
silabs.com | Building a more connected world.
dB
53.1
—
dB
35.7
—
dB
—
61.5
—
dB
Desired is 100 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
—
54.6
—
dB
Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
—
62.4
—
dB
Desired is 50 kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
—
58.1
—
dB
Desired is 9.6 kbps 4GFSK signal5 at 3dB above sensitivity level,
1% PER
—
50.6
—
dB
Desired is 4.8 kbps OOK signal3
at 3dB above sensitivity level,
20% PER
—
46.5
—
dB
Desired is 100 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
—
51.7
—
dB
Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
—
57.5
—
dB
Desired is 50 kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
—
54.4
—
dB
Desired is 9.6 kbps 4GFSK signal5 at 3dB above sensitivity level,
1% PER
—
48
—
dB
Interferer CW at Desired ± 1 MHz
—
75.7
—
dB
Interferer CW at Desired ± 2 MHz
—
77.2
—
dB
Interferer CW at Desired ± 10
MHz
—
92
—
dB
m
en
de
d
C/IIMAGE
om
Image rejection, Interferer is
CW at image frequency
—
Desired is 4.8 kbps OOK signal3
at 3dB above sensitivity level,
20% PER
fo
r
Alternate channel selectivity, C/I2
Interferer is CW at ± 2 ×
channel-spacing
—
61.5
N
ew
Desired is 9.6 kbps 4GFSK signal5 at 3dB above sensitivity level,
1% PER
es
ig
ns
Symbol
D
Parameter
Rev. 1.4 | 67
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Test Condition
Min
Typ
Max
Unit
Intermod selectivity, 0.1%
BER. CW interferers at 12.5
kHz and 25 kHz offsets
C/IIM
Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level
—
58.8
—
dB
RSSIMAX
Upper limit of input power
range over which RSSI resolution is maintained
—
—
5
dBm
RSSIMIN
Lower limit of input power
range over which RSSI resolution is maintained
-98
RSSIRES
—
—
dBm
0.25
—
dBm
-55
-49
dBm
-47
-41
dBm
Over RSSIMIN to RSSIMAX range
—
Max spurious emissions dur- SPURRX_FCC
ing active receive mode, per
FCC Part 15.109(a)
216-960 MHz
—
Above 960 MHz
—
Max spurious emissions dur- SPURRX_ETSI
ing active receive mode, per
ETSI 300-220 Section 8.6
Below 1000 MHz
—
-63
-57
dBm
Above 1000 MHz
—
-53
-47
dBm
Max spurious emissions dur- SPURRX_ARIB
ing active receive mode, per
ARIB STD T67 Section
3.3(5)
Below 710 MHz, RBW=100kHz
—
-60
-54
dBm
N
ew
RSSI resolution
es
ig
ns
Symbol
D
Parameter
N
ot
R
ec
om
m
en
de
d
fo
r
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5
kHz.
2. Definition of reference signal is 50 kbps 2GFSK, BT=0.5, Δf = 25 kHz, RX channel BW = 99.012 kHz, channel spacing = 200 kHz.
3. Definition of reference signal is 4.8 kbps OOK, RX channel BW = 306.036 kHz, channel spacing = 500 kHz.
4. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 198.024 kHz, channel spacing = 200
kHz.
5. Definition of reference signal is 9.6 kbps 4GFSK, BT=0.5, inner deviation = 0.8 kHz, RX channel BW = 8.5 kHz, channel spacing
= 12.5 kHz.
6. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
silabs.com | Building a more connected world.
Rev. 1.4 | 68
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.10.9 Sub-GHz RF Transmitter characteristics for 315 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 315 MHz.
Table 4.26. Sub-GHz RF Transmitter characteristics for 315 MHz Band
RF tuning frequency range
FRANGE
Maximum TX Power1
POUTMAX
Minimum active TX Power
POUTMIN
Output power step size
POUTSTEP
output power > 0 dBm
—
Output power variation vs
supply
POUTVAR_V
1.8 V < VVREGVDD < 3.3 V, External PA supply = DC-DC output, T
= 25 °C
—
Output power variation vs
temperature
POUTVAR_T
-40 to +85C
Min
195
13.8
Max
Unit
—
358
MHz
17.2
21.1
dBm
-43.9
—
dBm
0.5
—
dB
1.8
—
dB
N
ew
External PA supply connected to
DC-DC output
Typ
—
0.5
1.2
dB
—
0.7
1.5
dB
—
0.1
0.7
dB
SPURHARM_FCC In restricted bands, per FCC Part
15.205 / 15.209
—
-47
-42
dBm
In non-restricted bands, per FCC
Part 15.231
—
-26
-20
dBc
In non-restricted bands, per FCC
Part 15.231
—
-26
-20
dBc
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
—
-52
-46
dBm
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
—
-61
-56
dBm
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
—
-58
-52
dBm
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
—
-47
-42
dBm
-40 to +125C
T = 25 °C
m
en
de
d
fo
r
Output power variation vs RF POUTVAR_F
frequency
Spurious emissions of harmonics at 14 dBm output
power, Conducted measurement, 14dBm match, External PA supply connected to
DC-DC output, Test Frequency = 303 MHz
Test Condition
es
ig
ns
Symbol
D
Parameter
ec
om
Spurious emissions out-ofSPUROOB_FCC
band at 14 dBm output power, Conducted measurement,
14dBm match, External PA
supply connected to DC-DC
output, Test Frequency =
303 MHz
N
ot
R
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices covered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
silabs.com | Building a more connected world.
Rev. 1.4 | 69
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.10.10 Sub-GHz RF Receiver Characteristics for 315 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 315 MHz.
Table 4.27. Sub-GHz RF Receiver Characteristics for 315 MHz Band
Symbol
Tuning frequency range
FRANGE
Test Condition
Min
195
Typ
Max
Unit
es
ig
ns
Parameter
—
358
MHz
10
—
dBm
10
—
dBm
-123.2
-120.7
dBm
Desired is reference 2.4 kbps
GFSK signal1
—
Max usable input level, 0.1% SAT38k4
BER
Desired is reference 38.4 kbps
GFSK signal2
—
Sensitivity
Desired is reference 2.4 kbps
GFSK signal1, 0.1% BER, T ≤ 85
°C
—
Desired is reference 2.4 kbps
GFSK signal1, 0.1% BER, T > 85
°C
—
—
-120
dBm
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER, T ≤ 85
°C
—
-111.4
-108.6
dBm
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER, T > 85
°C
—
—
-107.9
dBm
Desired is reference 500 kbps
GFSK signal3, 0.1% BER, T ≤ 85
°C
—
-98.8
-95.5
dBm
Desired is reference 500 kbps
GFSK signal3, 0.1% BER, T > 85
°C
—
—
-94.5
dBm
m
en
de
d
fo
r
N
ew
SENS
D
Max usable input level, 0.1% SAT2k4
BER
RFSENSETRIG
CW at 315 MHz
—
-28.1
—
dBm
Level below which
RFSENSE will not trigger4
RFSENSETHRES CW at 315 MHz
—
-50
—
dBm
Adjacent channel selectivity,
Interferer is CW at ± 1 ×
channel-spacing
C/I1
Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
54.1
63.6
—
dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
—
49.9
—
dB
Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
—
64.2
—
dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level2,
0.1% BER
—
56.2
—
dB
R
ec
om
Level above which
RFSENSE will trigger4
N
ot
Alternate channel selectivity, C/I2
Interferer is CW at ± 2 ×
channel-spacing
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Test Condition
Image rejection, Interferer is
CW at image frequency
C/IIMAGE
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal1 at 3 dB above
sensitivity level
C/IBLOCKER
Min
Typ
Max
Unit
Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
—
53
—
dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
—
51.4
—
dB
Interferer CW at Desired ± 1 MHz
—
Interferer CW at Desired ± 2 MHz
—
Interferer CW at Desired ± 10
MHz
72.6
—
RSSIMIN
Lower limit of input power
range over which RSSI resolution is maintained
-98
RSSI resolution
RSSIRES
—
dB
76.5
—
dB
91.9
—
dB
—
5
dBm
—
dBm
—
Over RSSIMIN to RSSIMAX range
—
0.25
—
dBm
216-960 MHz
—
-63
-57
dBm
—
-53
-47
dBm
Above 960MHz
fo
r
Max spurious emissions dur- SPURRX_FCC
ing active receive mode, per
FCC Part 15.109(a)
75
N
ew
RSSIMAX
Upper limit of input power
range over which RSSI resolution is maintained
es
ig
ns
Symbol
D
Parameter
N
ot
R
ec
om
m
en
de
d
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5
kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100
kHz.
3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 753.320 kHz.
4. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.10.11 Sub-GHz RF Transmitter Characteristics for 169 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 169 MHz.
Table 4.28. Sub-GHz RF Transmitter Characteristics for 169 MHz Band
Test Condition
RF tuning frequency range
FRANGE
Maximum TX Power1
POUTMAX
Minimum active TX Power
POUTMIN
Output power step size
POUTSTEP
output power > 0 dBm
—
Output power variation vs
supply, peak to peak
POUTVAR_V
1.8 V < VVREGVDD < 3.3 V, External PA supply = 3.3 V, T = 25 °C
—
Output power variation vs
temperature, peak to peak
POUTVAR_T
-40 to +85 °C at 20 dBm
—
169
18.1
Max
Unit
—
170
MHz
19.7
22.4
dBm
-42.6
—
dBm
0.5
—
dB
4.8
5.0
dB
1.2
dB
0.6
0.8
1.5
dB
Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz)
—
-42
—
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz)2
—
-38
—
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz)2
—
-36
—
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz)
—
-42
-36
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz)
—
-42
-36
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz)
—
-36
-30
dBm
fo
r
—
m
en
de
d
om
Spurious emissions out-ofSPUROOB_ETSI
band, Conducted measurement, External PA supply =
3.3 V, Test Frequency = 169
MHz
Typ
N
ew
External PA supply = 3.3 V
-40 to +125 °C at 20 dBm
Spurious emissions of harSPURHARM_ETSI
monics, Conducted measurement, External PA supply
= 3.3 V, Test Frequency =
169 MHz
Min
es
ig
ns
Symbol
D
Parameter
N
ot
R
ec
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices covered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
2. Typical value marginally passes specification. Additional margin can be obtained by increasing the order of the harmonic filter.
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.10.12 Sub-GHz RF Receiver Characteristics for 169 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 169 MHz.
Table 4.29. Sub-GHz RF Receiver Characteristics for 169 MHz Band
Symbol
Tuning frequency range
FRANGE
Test Condition
Min
169
Typ
Max
Unit
es
ig
ns
Parameter
—
170
MHz
10
—
dBm
10
—
dBm
-124
—
dBm
-108
dBm
Desired is reference 2.4 kbps
GFSK signal1
—
Max usable input level, 0.1% SAT38k4
BER
Desired is reference 38.4 kbps
GFSK signal2
—
Sensitivity
Desired is reference 2.4 kbps
GFSK signal1, 0.1% BER
—
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER, T ≤ 85
°C
—
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER, T > 85
°C
—
—
-107
dBm
Desired is reference 500 kbps
GFSK signal3, 0.1% BER, T ≤ 85
°C
—
-99.2
-96
dBm
Desired is reference 500 kbps
GFSK signal3, 0.1% BER, T > 85
°C
—
—
-95
dBm
-112.2
m
en
de
d
fo
r
N
ew
SENS
D
Max usable input level, 0.1% SAT2k4
BER
RFSENSETRIG
CW at 169 MHz
—
-28.1
—
dBm
Level below which
RFSENSE will not trigger4
RFSENSETHRES CW at 169 MHz
—
-50
—
dBm
Adjacent channel selectivity,
Interferer is CW at ± 1 x
channel-spacing
C/I1
Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
—
64.8
—
dB
Desired is 38.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
43.3
51.4
—
dB
Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
—
67.4
—
dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
—
60.6
—
dB
Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
—
47.1
—
dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
—
47.1
—
dB
ec
om
Level above which
RFSENSE will trigger4
N
ot
R
Alternate channel selectivity, C/I2
Interferer is CW at ± 2 x
channel-spacing
Image rejection, Interferer is
CW at image frequency
C/IIMAGE
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Test Condition
Min
Typ
Max
Unit
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal1 at 3 dB above
sensitivity level
C/IBLOCKER
Interferer CW at Desired ± 1 MHz
—
73.4
—
dB
Interferer CW at Desired ± 2 MHz
—
75
—
dB
Interferer CW at Desired ± 10
MHz
80
90.1
—
dB
RSSIMAX
Upper limit of input power
range over which RSSI resolution is maintained
—
—
5
dBm
RSSIMIN
Lower limit of input power
range over which RSSI resolution is maintained
-98
—
—
dBm
0.25
—
dBm
-63
-57
dBm
-53
-47
dBm
RSSI resolution
RSSIRES
Max spurious emissions dur- SPURRX
ing active receive mode
Over RSSIMIN to RSSIMAX range
—
30 MHz to 1 GHz
—
1 GHz to 12 GHz
—
es
ig
ns
Symbol
D
Parameter
fo
r
N
ew
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5
kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100
kHz.
3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 753.320 kHz.
4. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
m
en
de
d
4.1.11 Modem
Table 4.30. Modem
Symbol
Test Condition
Min
Typ
Max
Unit
Receive bandwidth
BWRX
Configurable range with 38.4 MHz
crystal
0.1
—
2530
kHz
IF frequency
fIF
Configurable range with 38.4 MHz
crystal. Selected steps available.
150
—
1371
kHz
om
Parameter
SLDSSS
Configurable in steps of 1 chip
2
—
32
chips
DSSS bits per symbol
BPSDSSS
Configurable
1
—
4
bits/
symbol
N
ot
R
ec
DSSS symbol length
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.12 Oscillators
4.1.12.1 Low-Frequency Crystal Oscillator (LFXO)
Typ
Max
Unit
—
32.768
—
kHz
ESRLFXO
—
—
70
kΩ
Supported range of crystal
load capacitance 1
CLFXO_CL
6
—
18
pF
On-chip tuning cap range 2
CLFXO_T
8
D
Crystal frequency
fLFXO
Supported crystal equivalent
series resistance (ESR)
Test Condition
Min
—
40
pF
On-chip tuning cap step size
SSLFXO
—
0.25
—
pF
Current consumption after
startup 3
ILFXO
ESR = 70 kOhm, CL = 7 pF,
GAIN4 = 2, AGC4 = 1
—
273
—
nA
Start- up time
tLFXO
ESR = 70 kOhm, CL = 7 pF,
GAIN4 = 2
—
308
—
ms
On each of LFXTAL_N and
LFXTAL_P pins
N
ew
Symbol
fo
r
Parameter
es
ig
ns
Table 4.31. Low-Frequency Crystal Oscillator (LFXO)
N
ot
R
ec
om
m
en
de
d
Note:
1. Total load capacitance as seen by the crystal.
2. The effective load capacitance seen by the crystal will be CLFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
3. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.
4. In CMU_LFXOCTRL register.
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.12.2 High-Frequency Crystal Oscillator (HFXO)
Parameter
Symbol
Test Condition
Typ
Max
Unit
Crystal frequency
fHFXO
38.4 MHz required for radio transciever operation
38
38.4
40
MHz
Supported crystal equivalent
series resistance (ESR)
ESRHFXO_38M4
Crystal frequency 38.4 MHz
—
—
60
Ω
Supported range of crystal
load capacitance 1
CHFXO_CL
—
12
pF
On-chip tuning cap range 2
CHFXO_T
20
25
pF
On-chip tuning capacitance
step
SSHFXO
—
pF
Startup time
tHFXO
38.4 MHz, ESR = 50 Ohm, CL =
10 pF
—
300
—
µs
Frequency tolerance for the
crystal
FTHFXO
38.4 MHz, ESR = 50 Ohm, CL =
10 pF
-40
—
40
ppm
es
ig
ns
Min
D
Table 4.32. High-Frequency Crystal Oscillator (HFXO)
6
On each of HFXTAL_N and
HFXTAL_P pins
9
0.04
N
ew
—
m
en
de
d
fo
r
Note:
1. Total load capacitance as seen by the crystal.
2. The effective load capacitance seen by the crystal will be CHFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
4.1.12.3 Low-Frequency RC Oscillator (LFRCO)
Table 4.33. Low-Frequency RC Oscillator (LFRCO)
Symbol
Test Condition
Min
Typ
Max
Unit
Oscillation frequency
fLFRCO
ENVREF1 = 1, T ≤ 85 °C
31.3
32.768
33.6
kHz
ENVREF1 = 1, T > 85 °C
31.6
32.768
36.8
kHz
ENVREF1 = 0, T ≤ 85 °C
31.3
32.768
33.4
kHz
ENVREF1 = 0, T > 85 °C
30
32.768
33.4
kHz
—
500
—
µs
ENVREF = 1 in
CMU_LFRCOCTRL
—
342
—
nA
ENVREF = 0 in
CMU_LFRCOCTRL
—
494
—
nA
ec
om
Parameter
tLFRCO
Current consumption 2
ILFRCO
N
ot
R
Startup time
Note:
1. In CMU_LFRCOCTRL register.
2. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.12.4 High-Frequency RC Oscillator (HFRCO)
Table 4.34. High-Frequency RC Oscillator (HFRCO)
Symbol
Test Condition
Min
Typ
Max
Unit
Frequency accuracy
fHFRCO_ACC
At production calibrated frequencies, across supply voltage and
temperature
-2.5
—
2.5
%
Start-up time
tHFRCO
fHFRCO ≥ 19 MHz
—
300
—
ns
4 < fHFRCO < 19 MHz
—
1
—
µs
fHFRCO ≤ 4 MHz
—
2.5
—
µs
fHFRCO = 38 MHz
—
231
260
µA
fHFRCO = 32 MHz
—
193
218
µA
fHFRCO = 26 MHz
D
IHFRCO
N
ew
Current consumption on all
supplies
es
ig
ns
Parameter
—
165
186
µA
—
137
155
µA
—
118
131
µA
—
106
119
µA
fHFRCO = 7 MHz
—
83
94
µA
fHFRCO = 4 MHz
—
31
40
µA
fHFRCO = 2 MHz
—
27
37
µA
fHFRCO = 1 MHz
—
25
35
µA
—
0.8
—
%
fHFRCO = 19 MHz
fHFRCO = 16 MHz
m
en
de
d
fo
r
fHFRCO = 13 MHz
Coarse trim step size (% of
period)
SSHFRCO_COARS
Fine trim step size (% of period)
SSHFRCO_FINE
—
0.1
—
%
Period jitter
PJHFRCO
—
0.2
—
% RMS
Frequency limits
fHFRCO_BAND
FREQRANGE = 0, FINETUNINGEN = 0
3.47
—
6.15
MHz
FREQRANGE = 3, FINETUNINGEN = 0
6.24
—
11.45
MHz
FREQRANGE = 6, FINETUNINGEN = 0
11.3
—
19.8
MHz
FREQRANGE = 7, FINETUNINGEN = 0
13.45
—
22.8
MHz
FREQRANGE = 8, FINETUNINGEN = 0
16.5
—
29.0
MHz
FREQRANGE = 10, FINETUNINGEN = 0
23.11
—
40.63
MHz
FREQRANGE = 11, FINETUNINGEN = 0
27.27
—
48
MHz
FREQRANGE = 12, FINETUNINGEN = 0
33.33
—
54
MHz
N
ot
R
ec
om
E
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.12.5 Auxiliary High-Frequency RC Oscillator (AUXHFRCO)
Table 4.35. Auxiliary High-Frequency RC Oscillator (AUXHFRCO)
Frequency accuracy
fAUXHFRCO_ACC
Start-up time
tAUXHFRCO
Current consumption on all
supplies
IAUXHFRCO
Min
Typ
Max
Unit
At production calibrated frequencies, across supply voltage and
temperature
-3
—
3
%
fAUXHFRCO ≥ 19 MHz
—
400
—
ns
4 < fAUXHFRCO < 19 MHz
—
1.4
—
µs
fAUXHFRCO ≤ 4 MHz
—
2.5
—
µs
fAUXHFRCO = 38 MHz
—
237
265
µA
fAUXHFRCO = 32 MHz
—
194
218
µA
fAUXHFRCO = 26 MHz
—
165
186
µA
—
131
148
µA
—
119
134
µA
—
92
104
µA
fAUXHFRCO = 7 MHz
—
61
70
µA
fAUXHFRCO = 4 MHz
—
34
42
µA
fAUXHFRCO = 2 MHz
—
29
37
µA
fAUXHFRCO = 1 MHz
—
26
34
µA
—
0.8
—
%
—
0.1
—
%
—
0.2
—
% RMS
Min
Typ
Max
Unit
0.95
1
1.07
kHz
fAUXHFRCO = 19 MHz
fAUXHFRCO = 16 MHz
m
en
de
d
fo
r
fAUXHFRCO = 13 MHz
Coarse trim step size (% of
period)
CO_COARSE
Fine trim step size (% of period)
CO_FINE
Period jitter
PJAUXHFRCO
es
ig
ns
Test Condition
D
Symbol
N
ew
Parameter
SSAUXHFR-
om
SSAUXHFR-
ec
4.1.12.6 Ultra-low Frequency RC Oscillator (ULFRCO)
Table 4.36. Ultra-low Frequency RC Oscillator (ULFRCO)
Symbol
Oscillation frequency
fULFRCO
Test Condition
N
ot
R
Parameter
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.13 Flash Memory Characteristics1
Table 4.37. Flash Memory Characteristics1
Symbol
Flash erase cycles before
failure
ECFLASH
Flash data retention
RETFLASH
tW_PROG
Min
Typ
Max
Unit
10000
—
—
cycles
—
—
years
—
—
years
26.1
30
µs
68.5
80
µs
T ≤ 85 °C
10
T ≤ 125 °C
10
Burst write, 128 words, average
time per word
20
Single word
60
tPERASE
20
28.8
40
ms
Mass erase time3
tMERASE
20
28.7
40
ms
Device erase time4 5
tDERASE
—
54.4
70
ms
—
54.4
75
ms
—
—
1.6
mA
—
—
3.5
mA
1.62
—
3.6
V
N
ew
Page erase time2
D
Word (32-bit) programming
time
Test Condition
es
ig
ns
Parameter
T ≤ 85 °C
T ≤ 125 °C
IERASE
Write current6
IWRITE
Supply voltage during flash
erase and write
VFLASH
Page Erase
fo
r
Erase current6
N
ot
R
ec
om
m
en
de
d
Note:
1. Flash data retention information is published in the Quarterly Quality and Reliability Report.
2. From setting the ERASEPAGE bit in MSC_WRITECMD to 1 until the BUSY bit in MSC_STATUS is cleared to 0. Internal setup
and hold times for flash control signals are included.
3. Mass erase is issued by the CPU and erases all flash.
4. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock
Word (ULW).
5. From setting the DEVICEERASE bit in AAP_CMD to 1 until the ERASEBUSY bit in AAP_STATUS is cleared to 0. Internal setup
and hold times for flash control signals are included.
6. Measured at 25 °C.
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.14 General-Purpose I/O (GPIO)
Table 4.38. General-Purpose I/O (GPIO)
Symbol
Test Condition
Min
Typ
Max
Unit
Input low voltage1
VIL
GPIO pins
—
—
IOVDD*0.3
V
Input high voltage1
VIH
GPIO pins
IOVDD*0.7
—
—
V
Output high voltage relative
to IOVDD
VOH
Sourcing 3 mA, IOVDD ≥ 3 V,
IOVDD*0.8
—
—
V
—
—
V
DRIVESTRENGTH2 = WEAK
IOVDD*0.6
D
Sourcing 1.2 mA, IOVDD ≥ 1.62
V,
DRIVESTRENGTH2 = WEAK
IOVDD*0.8
—
—
V
IOVDD*0.6
—
—
V
—
—
IOVDD*0.2
V
—
—
IOVDD*0.4
V
—
—
IOVDD*0.2
V
—
—
IOVDD*0.4
V
All GPIO except LFXO pins, GPIO
≤ IOVDD, T ≤ 85 °C
—
0.1
30
nA
LFXO Pins, GPIO ≤ IOVDD, T ≤
85 °C
—
0.1
50
nA
All GPIO except LFXO pins, GPIO
≤ IOVDD, T > 85 °C
—
—
110
nA
LFXO Pins, GPIO ≤ IOVDD, T >
85 °C
—
—
250
nA
IOVDD < GPIO ≤ IOVDD + 2 V
—
3.3
15
µA
30
40
65
kΩ
15
25
45
ns
N
ew
Sourcing 20 mA, IOVDD ≥ 3 V,
es
ig
ns
Parameter
DRIVESTRENGTH2 = STRONG
Sourcing 8 mA, IOVDD ≥ 1.62 V,
DRIVESTRENGTH2 = STRONG
Sinking 3 mA, IOVDD ≥ 3 V,
fo
r
Output low voltage relative to VOL
IOVDD
DRIVESTRENGTH2 = WEAK
Sinking 1.2 mA, IOVDD ≥ 1.62 V,
m
en
de
d
DRIVESTRENGTH2 = WEAK
Sinking 20 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH2 = STRONG
Sinking 8 mA, IOVDD ≥ 1.62 V,
DRIVESTRENGTH2 = STRONG
IIOLEAK
R
ec
om
Input leakage current
N
ot
Input leakage current on
5VTOL pads above IOVDD
I/O pin pull-up/pull-down resistor3
I5VTOLLEAK
RPUD
Pulse width of pulses retIOGLITCH
moved by the glitch suppression filter
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Rev. 1.4 | 80
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Output fall time, From 70%
to 30% of VIO
tIOOF
CL = 50 pF,
Min
Typ
Max
Unit
—
1.8
—
ns
—
4.5
—
ns
DRIVESTRENGTH2 = STRONG,
DRIVESTRENGTH2 = WEAK,
SLEWRATE2 = 0x6
Output rise time, From 30%
to 70% of VIO
tIOOR
CL = 50 pF,
—
DRIVESTRENGTH2 = STRONG,
SLEWRATE = 0x62
CL = 50 pF,
—
2.2
—
ns
D
CL = 50 pF,
es
ig
ns
SLEWRATE2 = 0x6
—
ns
7.4
SLEWRATE2 = 0x6
N
ew
DRIVESTRENGTH2 = WEAK,
N
ot
R
ec
om
m
en
de
d
fo
r
Note:
1. GPIO input threshold are proportional to the IOVDD supply, except for RESETn which is proportional to AVDD.
2. In GPIO_Pn_CTRL register.
3. GPIO pull-ups are referenced to the IOVDD supply, except for RESETn, which connects to AVDD.
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Rev. 1.4 | 81
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.15 Voltage Monitor (VMON)
Symbol
Test Condition
Typ
Max
Unit
Supply current (including
I_SENSE)
IVMON
In EM0 or EM1, 1 active channel,
T ≤ 85 °C
—
6.3
8
µA
In EM0 or EM1, 1 active channel,
T > 85 °C
—
—
11
µA
In EM0 or EM1, All channels active, T ≤ 85 °C
—
12.5
15
µA
In EM0 or EM1, All channels active, T > 85 °C
—
—
18
µA
In EM2, EM3 or EM4, 1 channel
active and above threshold
—
—
nA
In EM2, EM3 or EM4, 1 channel
active and below threshold
—
62
—
nA
In EM2, EM3 or EM4, All channels
active and above threshold
—
99
—
nA
In EM2, EM3 or EM4, All channels
active and below threshold
—
99
—
nA
In EM0 or EM1
—
2
—
µA
In EM2, EM3 or EM4
—
2
—
nA
1.62
—
3.4
V
Coarse
—
200
—
mV
Fine
—
20
—
mV
Supply drops at 1V/µs rate
—
460
—
ns
—
26
—
mV
62
ISENSE
m
en
de
d
Loading of monitored supply
fo
r
N
ew
Parameter
es
ig
ns
Min
D
Table 4.39. Voltage Monitor (VMON)
Threshold range
VVMON_RANGE
Threshold step size
NVMON_STESP
tVMON_RES
Hysteresis
VVMON_HYST
N
ot
R
ec
om
Response time
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Rev. 1.4 | 82
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.16 Analog to Digital Converter (ADC)
Specified at 1 Msps, ADCCLK = 16 MHz, BIASPROG = 0, GPBIASACC = 0, unless otherwise indicated.
Table 4.40. Analog to Digital Converter (ADC)
Resolution
VRESOLUTION
Input voltage range1
VADCIN
Test Condition
Single ended
Min
Typ
Max
Unit
6
—
12
Bits
—
VFS
V
—
VFS/2
V
—
VAVDD
V
80
—
dB
80
—
dB
—
Differential
-VFS/2
Input range of external refer- VADCREFIN_P
ence voltage, single ended
and differential
1
PSRRADC
At DC
—
Analog input common mode
rejection ratio
CMRRADC
At DC
—
Current from all supplies, us- IADC_CONTINUing internal reference buffer. OUS_LP
Continuous operation. WARMUPMODE3 = KEEPADCWARM
N
ew
Power supply rejection2
es
ig
ns
Symbol
D
Parameter
—
270
304
µA
250 ksps / 4 MHz ADCCLK, BIASPROG = 6, GPBIASACC = 1 4
—
125
—
µA
62.5 ksps / 1 MHz ADCCLK, BIASPROG = 15, GPBIASACC = 1 4
—
80
—
µA
Current from all supplies, us- IADC_NORMAL_LP 35 ksps / 16 MHz ADCCLK, BIAing internal reference buffer.
SPROG = 0, GPBIASACC = 1 4
Duty-cycled operation. WAR5 ksps / 16 MHz ADCCLK BIAMUPMODE3 = NORMAL
SPROG = 0, GPBIASACC = 1 4
—
45
—
µA
—
8
—
µA
Current from all supplies, us- IADC_STANDing internal reference buffer. BY_LP
Duty-cycled operation.
AWARMUPMODE3 = KEEPINSTANDBY or KEEPINSLOWACC
125 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 1 4
—
105
—
µA
35 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 1 4
—
70
—
µA
1 Msps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 0 4
—
325
—
µA
250 ksps / 4 MHz ADCCLK, BIASPROG = 6, GPBIASACC = 0 4
—
175
—
µA
62.5 ksps / 1 MHz ADCCLK, BIASPROG = 15, GPBIASACC = 0 4
—
125
—
µA
Current from all supplies, us- IADC_NORMAL_HP 35 ksps / 16 MHz ADCCLK, BIAing internal reference buffer.
SPROG = 0, GPBIASACC = 0 4
Duty-cycled operation. WAR5 ksps / 16 MHz ADCCLK BIAMUPMODE3 = NORMAL
SPROG = 0, GPBIASACC = 0 4
—
85
—
µA
—
16
—
µA
m
en
de
d
fo
r
1 Msps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 1 4
N
ot
R
ec
om
Current from all supplies, us- IADC_CONTINUing internal reference buffer. OUS_HP
Continuous operation. WARMUPMODE3 = KEEPADCWARM
Current from all supplies, us- IADC_STANDing internal reference buffer. BY_HP
Duty-cycled operation.
AWARMUPMODE3 = KEEPINSTANDBY or KEEPINSLOWACC
125 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 0 4
—
160
—
µA
35 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 0 4
—
125
—
µA
Current from HFPERCLK
HFPERCLK = 16 MHz
—
150
—
µA
IADC_CLK
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Rev. 1.4 | 83
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Min
Typ
Max
Unit
fADCCLK
—
—
16
MHz
Throughput rate
fADCRATE
—
—
1
Msps
Conversion time5
tADCCONV
6 bit
—
7
—
cycles
8 bit
—
9
—
cycles
12 bit
—
WARMUPMODE3 = NORMAL
—
WARMUPMODE3 = KEEPINSTANDBY
—
WARMUPMODE3 = KEEPINSLOWACC
—
Internal reference6, differential
measurement
58
Startup time of reference
generator and ADC core
SNDR at 1Msps and fIN =
10kHz
tADCSTART
SNDRADC
es
ig
ns
ADC clock frequency
Test Condition
13
—
cycles
—
5
µs
—
2
µs
—
1
µs
D
Symbol
—
dB
67
N
ew
Parameter
—
68
—
dB
Spurious-free dynamic range SFDRADC
(SFDR)
1 MSamples/s, 10 kHz full-scale
sine wave
—
75
—
dB
Differential non-linearity
(DNL)
DNLADC
12 bit resolution, No missing codes
-1
—
2
LSB
Integral non-linearity (INL),
End point method
INLADC
12 bit resolution
-6
—
6
LSB
Offset error
VADCOFFSETERR
-3
0
3
LSB
Gain error in ADC
VADCGAIN
Using internal reference
—
-0.2
3.5
%
Using external reference
—
-1
—
%
—
-1.84
—
mV/°C
m
en
de
d
Temperature sensor slope
fo
r
External reference7, differential
measurement
VTS_SLOPE
N
ot
R
ec
om
Note:
1. The absolute voltage allowed at any ADC input is dictated by the power rail supplied to on-chip circuitry, and may be lower than
the effective full scale voltage. All ADC inputs are limited to the ADC supply (AVDD or DVDD depending on
EMU_PWRCTRL_ANASW). Any ADC input routed through the APORT will further be limited by the IOVDD supply to the pin.
2. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL.
3. In ADCn_CTRL register.
4. In ADCn_BIASPROG register.
5. Derived from ADCCLK.
6. Internal reference option used corresponds to selection 2V5 in the SINGLECTRL_REF or SCANCTRL_REF register field. The
differential input range with this configuration is ± 1.25 V. Typical value is characterized using full-scale sine wave input. Minimum
value is production-tested using sine wave input at 1.5 dB lower than full scale.
7. External reference is 1.25 V applied externally to ADCnEXTREFP, with the selection CONF in the SINGLECTRL_REF or
SCANCTRL_REF register field and VREFP in the SINGLECTRLX_VREFSEL or SCANCTRLX_VREFSEL field. The differential
input range with this configuration is ± 1.25 V.
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Rev. 1.4 | 84
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.17 Analog Comparator (ACMP)
Table 4.41. Analog Comparator (ACMP)
Symbol
Test Condition
Input voltage range
VACMPIN
Supply voltage
VACMPVDD
Max
Unit
ACMPVDD =
ACMPn_CTRL_PWRSEL 1
—
—
VACMPVDD
V
BIASPROG2 ≤ 0x10 or FULLBIAS2 = 0
1.8
—
VVREGVDD_
V
0x10 < BIASPROG2 ≤ 0x20 and
FULLBIAS2 = 1
2.1
BIASPROG2 = 1, FULLBIAS2 = 0
—
BIASPROG2 = 0x10, FULLBIAS2
=0
—
BIASPROG2 = 0x02, FULLBIAS2
=1
—
BIASPROG2 = 0x20, FULLBIAS2
=1
MAX
—
V
MAX
50
—
nA
306
—
nA
6.1
10
µA
—
74
92
µA
VLP selected as input using 2.5 V
Reference / 4 (0.625 V)
—
50
—
nA
VLP selected as input using VDD
—
20
—
nA
VBDIV selected as input using
1.25 V reference / 1
—
4.1
—
µA
VADIV selected as input using
VDD/1
—
2.4
—
µA
fo
r
N
ot
R
ec
om
m
en
de
d
Current consumption of inter- IACMPREF
nal voltage reference3
VVREGVDD_
D
IACMP
Typ
N
ew
Active current not including
voltage reference3
Min
es
ig
ns
Parameter
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Rev. 1.4 | 85
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Test Condition
Min
Typ
Max
Unit
Hysteresis (VCM = 1.25 V,
BIASPROG2 = 0x10, FULLBIAS2 = 1)
VACMPHYST
HYSTSEL4 = HYST0
-3
0
3
mV
HYSTSEL4 = HYST1
5
18
27
mV
HYSTSEL4 = HYST2
12
33
50
mV
HYSTSEL4 = HYST3
17
46
67
mV
HYSTSEL4 = HYST4
23
HYSTSEL4 = HYST5
26
HYSTSEL4 = HYST6
30
HYSTSEL4 = HYST7
34
HYSTSEL4 = HYST8
-3
HYSTSEL4 = HYST9
HYSTSEL4 = HYST10
86
mV
68
104
mV
79
130
mV
90
155
mV
0
3
mV
-27
-18
-5
mV
-50
-33
-12
mV
-67
-45
-17
mV
-86
-57
-23
mV
-104
-67
-26
mV
HYSTSEL4 = HYST14
-130
-78
-30
mV
HYSTSEL4 = HYST15
-155
-88
-34
mV
—
30
95
µs
BIASPROG2 = 0x10, FULLBIAS2
=0
—
3.7
10
µs
BIASPROG2 = 0x02, FULLBIAS2
=1
—
360
1000
ns
BIASPROG2 = 0x20, FULLBIAS2
=1
—
35
—
ns
BIASPROG2 =0x10, FULLBIAS2
=1
-35
—
35
mV
Internal 1.25 V reference
1
1.25
1.47
V
Internal 2.5 V reference
1.98
2.5
2.8
V
CSRESSEL6 = 0
—
infinite
—
kΩ
CSRESSEL6 = 1
—
15
—
kΩ
CSRESSEL6 = 2
—
27
—
kΩ
CSRESSEL6 = 3
—
39
—
kΩ
CSRESSEL6 = 4
—
51
—
kΩ
CSRESSEL6 = 5
—
102
—
kΩ
CSRESSEL6 = 6
—
164
—
kΩ
CSRESSEL6 = 7
—
239
—
kΩ
HYSTSEL4 = HYST12
tACMPDELAY
BIASPROG2 = 1, FULLBIAS2 = 0
m
en
de
d
VACMPOFFSET
om
Offset voltage
Reference voltage
fo
r
HYSTSEL4 = HYST13
VACMPREF
N
ot
R
ec
Capacitive sense internal re- RCSRES
sistance
silabs.com | Building a more connected world.
N
ew
57
HYSTSEL4 = HYST11
Comparator delay5
es
ig
ns
Symbol
D
Parameter
Rev. 1.4 | 86
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note:
1. ACMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be IOVDD, AVDD or DVDD.
2. In ACMPn_CTRL register.
3. The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference. IACMPTOTAL = IACMP +
IACMPREF.
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
es
ig
ns
4. In ACMPn_HYSTERESIS registers.
5. ± 100 mV differential drive.
6. In ACMPn_INPUTSEL register.
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Rev. 1.4 | 87
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.18 Digital to Analog Converter (VDAC)
DRIVESTRENGTH = 2 unless otherwise specified. Primary VDAC output.
Table 4.42. Digital to Analog Converter (VDAC)
Test Condition
Output voltage
VDACOUT
Single-Ended
Max
Unit
0
—
VVREF
V
—
VVREF
V
396
—
µA
72
—
µA
1.2
—
µA
500 ksps, 12-bit, DRIVESTRENGTH = 2, REFSEL = 4
—
44.1 ksps, 12-bit, DRIVESTRENGTH = 1, REFSEL = 4
—
200 Hz refresh rate, 12-bit Sample-Off mode in EM2, DRIVESTRENGTH = 2, REFSEL = 4,
SETTLETIME = 0x02, WARMUPTIME = 0x0A
—
N
ew
IDAC
Typ
-VVREF
Differential1
IDAC_CLK
—
5
—
µA/MHz
Sample rate
SRDAC
—
—
500
ksps
DAC clock frequency
fDAC
—
—
1
MHz
Conversion time
tDACCONV
fDAC = 1MHz
2
—
—
µs
Settling time
tDACSETTLE
50% fs step settling to 5 LSB
—
2.5
—
µs
Startup time
tDACSTARTUP
Enable to 90% fs output, settling
to 10 LSB
—
—
12
µs
Output impedance
ROUT
DRIVESTRENGTH = 2, 0.4 V ≤
VOUT ≤ VOPA - 0.4 V, -8 mA <
IOUT < 8 mA, Full supply range
—
2
—
Ω
DRIVESTRENGTH = 0 or 1, 0.4 V
≤ VOUT ≤ VOPA - 0.4 V, -400 µA <
IOUT < 400 µA, Full supply range
—
2
—
Ω
DRIVESTRENGTH = 2, 0.1 V ≤
VOUT ≤ VOPA - 0.1 V, -2 mA <
IOUT < 2 mA, Full supply range
—
2
—
Ω
DRIVESTRENGTH = 0 or 1, 0.1 V
≤ VOUT ≤ VOPA - 0.1 V, -100 µA <
IOUT < 100 µA, Full supply range
—
2
—
Ω
Vout = 50% fs. DC
—
65.5
—
dB
ec
om
m
en
de
d
Current from HFPERCLK3
fo
r
Current consumption including references (2 channels)2
Min
es
ig
ns
Symbol
D
Parameter
N
ot
R
Power supply rejection ratio4 PSRR
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Min
Typ
Max
Unit
500 ksps, single-ended, internal
1.25V reference
—
60.4
—
dB
500 ksps, single-ended, internal
2.5V reference
—
61.6
—
dB
500 ksps, single-ended, 3.3V
VDD reference
—
64.0
—
dB
500 ksps, differential, internal
1.25V reference
—
500 ksps, differential, internal
2.5V reference
—
500 ksps, differential, 3.3V VDD
reference
—
Signal to noise and distortion SNDRDAC_BAND 500 ksps, single-ended, internal
1.25V reference
ratio (1 kHz sine wave),
Noise band limited to 22 kHz
500 ksps, single-ended, internal
2.5V reference
63.3
—
dB
64.4
—
dB
65.8
—
dB
—
65.3
—
dB
—
66.7
—
dB
500 ksps, single-ended, 3.3V
VDD reference
—
70.0
—
dB
500 ksps, differential, internal
1.25V reference
—
67.8
—
dB
500 ksps, differential, internal
2.5V reference
—
69.0
—
dB
500 ksps, differential, 3.3V VDD
reference
—
68.5
—
dB
—
70.2
—
dB
m
en
de
d
fo
r
N
ew
Signal to noise and distortion SNDRDAC
ratio (1 kHz sine wave),
Noise band limited to 250
kHz
Test Condition
es
ig
ns
Symbol
D
Parameter
THD
Differential non-linearity5
DNLDAC
-0.99
—
1
LSB
Intergral non-linearity
INLDAC
-4
—
4
LSB
Offset error6
VOFFSET
T = 25 °C
-8
—
8
mV
Across operating temperature
range
-25
—
25
mV
T = 25 °C, Low-noise internal reference (REFSEL = 1V25LN or
2V5LN)
-2.5
—
2.5
%
T = 25 °C, Internal reference (REFSEL = 1V25 or 2V5)
-5
—
5
%
T = 25 °C, External reference
(REFSEL = VDD or EXT)
-1.8
—
1.8
%
Across operating temperature
range, Low-noise internal reference (REFSEL = 1V25LN or
2V5LN)
-3.5
—
3.5
%
Across operating temperature
range, Internal reference (REFSEL = 1V25 or 2V5)
-7.5
—
7.5
%
Across operating temperature
range, External reference (REFSEL = VDD or EXT)
-2.0
—
2.0
%
VGAIN
N
ot
R
ec
Gain error6
om
Total harmonic distortion
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Rev. 1.4 | 89
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
External load capactiance,
OUTSCALE=0
CLOAD
Test Condition
Min
Typ
Max
Unit
—
—
75
pF
es
ig
ns
Note:
1. In differential mode, the output is defined as the difference between two single-ended outputs. Absolute voltage on each output is
limited to the single-ended range.
2. Supply current specifications are for VDAC circuitry operating with static output only and do not include current required to drive
the load.
3. Current from HFPERCLK is dependent on HFPERCLK frequency. This current contributes to the total supply current used when
the clock to the DAC peripheral is enabled in the CMU.
4. PSRR calculated as 20 * log10(ΔVDD / ΔVOUT), VDAC output at 90% of full scale
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
5. Entire range is monotonic and has no missing codes.
6. Gain is calculated by measuring the slope from 10% to 90% of full scale. Offset is calculated by comparing actual VDAC output at
10% of full scale to ideal VDAC output at 10% of full scale with the measured gain.
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Rev. 1.4 | 90
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.19 Current Digital to Analog Converter (IDAC)
Table 4.43. Current Digital to Analog Converter (IDAC)
NIDAC_RANGES
Output current
IIDAC_OUT
Linear steps within each
range
NIDAC_STEPS
Step size
SSIDAC
—
4
—
ranges
—
1.6
µA
—
4.7
µA
—
16
µA
—
64
µA
1.6
RANGESEL1 = RANGE2
0.5
RANGESEL1 = RANGE3
2
—
32
—
steps
—
50
—
nA
—
100
—
nA
—
500
—
nA
—
2
—
µA
EM0 or EM1, AVDD=3.3 V, T = 25
°C
-3
—
3
%
EM0 or EM1, Across operating
temperature range
-18
—
22
%
EM2 or EM3, Source mode, RANGESEL1 = RANGE0, AVDD=3.3
V, T = 25 °C
—
-2
—
%
EM2 or EM3, Source mode, RANGESEL1 = RANGE1, AVDD=3.3
V, T = 25 °C
—
-1.7
—
%
EM2 or EM3, Source mode, RANGESEL1 = RANGE2, AVDD=3.3
V, T = 25 °C
—
-0.8
—
%
EM2 or EM3, Source mode, RANGESEL1 = RANGE3, AVDD=3.3
V, T = 25 °C
—
-0.5
—
%
EM2 or EM3, Sink mode, RANGESEL1 = RANGE0, AVDD=3.3
V, T = 25 °C
—
-0.7
—
%
EM2 or EM3, Sink mode, RANGESEL1 = RANGE1, AVDD=3.3
V, T = 25 °C
—
-0.6
—
%
EM2 or EM3, Sink mode, RANGESEL1 = RANGE2, AVDD=3.3
V, T = 25 °C
—
-0.5
—
%
EM2 or EM3, Sink mode, RANGESEL1 = RANGE3, AVDD=3.3
V, T = 25 °C
—
-0.5
—
%
RANGESEL1 = RANGE0
fo
r
m
en
de
d
om
ec
R
Unit
RANGESEL1 = RANGE1
RANGESEL1 = RANGE3
N
ot
Max
0.05
RANGESEL1 = RANGE2
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Typ
RANGESEL1 = RANGE0
RANGESEL1 = RANGE1
Total accuracy, STEPSEL1 = ACCIDAC
0x10
Min
es
ig
ns
Number of ranges
Test Condition
D
Symbol
N
ew
Parameter
Rev. 1.4 | 91
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Test Condition
Start up time
tIDAC_SU
IIDAC
Unit
Output within 1% of steady state
value
—
5
—
µs
Range setting is changed
—
5
—
µs
Step value is changed
—
1
—
µs
EM0 or EM1 Source mode, excluding output current, Across operating temperature range
—
11
15
µA
EM0 or EM1 Sink mode, excluding output current, Across operating temperature range
—
13
18
µA
EM2 or EM3 Source mode, excluding output current, T = 25 °C
—
0.050
—
µA
EM2 or EM3 Sink mode, excluding output current, T = 25 °C
—
—
µA
R
ec
om
Output voltage compliance in ICOMP_SINK
sink mode, sink current
change relative to current
sunk at IOVDD
0.075
EM2 or EM3 Source mode, excluding output current, T ≥ 85 °C
—
11
—
µA
EM2 or EM3 Sink mode, excluding output current, T ≥ 85 °C
—
13
—
µA
RANGESEL1 = RANGE0, output
voltage = min(VIOVDD,
VAVDD2-100 mV)
—
0.11
—
%
RANGESEL1 = RANGE1, output
voltage = min(VIOVDD,
VAVDD2-100 mV)
—
0.06
—
%
RANGESEL1 = RANGE2, output
voltage = min(VIOVDD,
VAVDD2-150 mV)
—
0.04
—
%
RANGESEL1 = RANGE3, output
voltage = min(VIOVDD,
VAVDD2-250 mV)
—
0.03
—
%
RANGESEL1 = RANGE0, output
voltage = 100 mV
—
0.12
—
%
RANGESEL1 = RANGE1, output
voltage = 100 mV
—
0.05
—
%
RANGESEL1 = RANGE2, output
voltage = 150 mV
—
0.04
—
%
RANGESEL1 = RANGE3, output
voltage = 250 mV
—
0.03
—
%
m
en
de
d
Output voltage compliance in ICOMP_SRC
source mode, source current
change relative to current
sourced at 0 V
Max
fo
r
Current consumption2
Typ
es
ig
ns
Symbol
N
ew
Parameter
Settling time, (output settled tIDAC_SETTLE
within 1% of steady state value),
Min
D
Electrical Specifications
N
ot
Note:
1. In IDAC_CURPROG register.
2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and
PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects between AVDD (0) and DVDD (1).
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.20 Operational Amplifier (OPAMP)
Unless otherwise indicated, specified conditions are: Non-inverting input configuration, VDD = 3.3 V, DRIVESTRENGTH = 2, MAINOUTEN = 1, CLOAD = 75 pF with OUTSCALE = 0, or CLOAD = 37.5 pF with OUTSCALE = 1. Unit gain buffer and 3X-gain connection as
specified in table footnotes1 2.
Symbol
Test Condition
Supply voltage (from AVDD)
VOPA
HCMDIS = 0, Rail-to-rail input
range
VIN
Input impedance
RIN
Output voltage
VOUT
Load capacitance3
CLOAD
HCMDIS = 1
1.62
HCMDIS = 0, Rail-to-rail input
range
VVSS
HCMDIS = 1
VVSS
100
IOPA
N
ot
R
Active current4
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—
3.8
V
—
3.8
V
—
VOPA
V
—
VOPA-1.2
V
—
—
MΩ
VOPA
V
—
—
75
pF
—
—
37.5
pF
DRIVESTRENGTH = 2 or 3, 0.4 V
≤ VOUT ≤ VOPA - 0.4 V, -8 mA <
IOUT < 8 mA, Buffer connection,
Full supply range
—
0.25
—
Ω
DRIVESTRENGTH = 0 or 1, 0.4 V
≤ VOUT ≤ VOPA - 0.4 V, -400 µA <
IOUT < 400 µA, Buffer connection,
Full supply range
—
0.6
—
Ω
DRIVESTRENGTH = 2 or 3, 0.1 V
≤ VOUT ≤ VOPA - 0.1 V, -2 mA <
IOUT < 2 mA, Buffer connection,
Full supply range
—
0.4
—
Ω
DRIVESTRENGTH = 0 or 1, 0.1 V
≤ VOUT ≤ VOPA - 0.1 V, -100 µA <
IOUT < 100 µA, Buffer connection,
Full supply range
—
1
—
Ω
Buffer connection
0.99
1
1.01
-
3x Gain connection
2.93
2.99
3.05
-
16x Gain connection
15.07
15.7
16.33
-
DRIVESTRENGTH = 3, OUTSCALE = 0
—
580
—
µA
DRIVESTRENGTH = 2, OUTSCALE = 0
—
176
—
µA
DRIVESTRENGTH = 1, OUTSCALE = 0
—
13
—
µA
DRIVESTRENGTH = 0, OUTSCALE = 0
—
4.7
—
µA
OUTSCALE = 0
m
en
de
d
om
GCL
ec
Internal closed-loop gain
Unit
—
fo
r
ROUT
Max
VVSS
OUTSCALE = 1
Output impedance
2
Typ
N
ew
Input voltage
Min
D
Parameter
es
ig
ns
Table 4.44. Operational Amplifier (OPAMP)
Rev. 1.4 | 93
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Symbol
Test Condition
Open-loop gain
GOL
Max
Unit
DRIVESTRENGTH = 3
—
135
—
dB
DRIVESTRENGTH = 2
—
137
—
dB
DRIVESTRENGTH = 1
—
121
—
dB
DRIVESTRENGTH = 0
—
109
—
dB
DRIVESTRENGTH = 3, Buffer
connection
—
DRIVESTRENGTH = 2, Buffer
connection
—
DRIVESTRENGTH = 1, Buffer
connection
—
DRIVESTRENGTH = 0, Buffer
connection
—
DRIVESTRENGTH = 3, 3x Gain
connection
—
DRIVESTRENGTH = 2, 3x Gain
connection
—
DRIVESTRENGTH = 1, 3x Gain
connection
3.38
—
MHz
0.9
—
MHz
132
—
kHz
34
—
kHz
2.57
—
MHz
0.71
—
MHz
—
113
—
kHz
DRIVESTRENGTH = 0, 3x Gain
connection
—
28
—
kHz
DRIVESTRENGTH = 3, Buffer
connection
—
67
—
°
DRIVESTRENGTH = 2, Buffer
connection
—
69
—
°
DRIVESTRENGTH = 1, Buffer
connection
—
63
—
°
DRIVESTRENGTH = 0, Buffer
connection
—
68
—
°
DRIVESTRENGTH = 3, Buffer
connection, 10 Hz - 10 MHz
—
146
—
µVrms
DRIVESTRENGTH = 2, Buffer
connection, 10 Hz - 10 MHz
—
163
—
µVrms
DRIVESTRENGTH = 1, Buffer
connection, 10 Hz - 1 MHz
—
170
—
µVrms
DRIVESTRENGTH = 0, Buffer
connection, 10 Hz - 1 MHz
—
176
—
µVrms
DRIVESTRENGTH = 3, 3x Gain
connection, 10 Hz - 10 MHz
—
313
—
µVrms
DRIVESTRENGTH = 2, 3x Gain
connection, 10 Hz - 10 MHz
—
271
—
µVrms
DRIVESTRENGTH = 1, 3x Gain
connection, 10 Hz - 1 MHz
—
247
—
µVrms
DRIVESTRENGTH = 0, 3x Gain
connection, 10 Hz - 1 MHz
—
245
—
µVrms
D
UGF
Typ
PM
NOUT
N
ot
R
ec
om
Output voltage noise
m
en
de
d
Phase margin
fo
r
N
ew
Loop unit-gain frequency5
Min
es
ig
ns
Parameter
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Min
Typ
Max
Unit
Slew rate6
SR
DRIVESTRENGTH = 3,
INCBW=17
—
4.7
—
V/µs
DRIVESTRENGTH = 3,
INCBW=0
—
1.5
—
V/µs
DRIVESTRENGTH = 2,
INCBW=17
—
1.27
—
V/µs
DRIVESTRENGTH = 2,
INCBW=0
—
DRIVESTRENGTH = 1,
INCBW=17
—
DRIVESTRENGTH = 1,
INCBW=0
DRIVESTRENGTH = 0,
INCBW=17
DRIVESTRENGTH = 0,
INCBW=0
es
ig
ns
Test Condition
0.42
—
V/µs
0.17
—
V/µs
—
0.058
—
V/µs
—
D
Symbol
—
V/µs
0.044
N
ew
Parameter
—
0.015
—
V/µs
—
—
12
µs
-2
—
2
mV
DRIVESTRENGTH = 1 or 0, T =
25 °C
-2
—
2
mV
DRIVESTRENGTH = 2 or 3,
across operating temperature
range
-12
—
12
mV
DRIVESTRENGTH = 1 or 0,
across operating temperature
range
-30
—
30
mV
TSTART
DRIVESTRENGTH = 2
Input offset voltage
VOSI
DRIVESTRENGTH = 2 or 3, T =
25 °C
m
en
de
d
fo
r
Startup time8
PSRRDC
Input referred
—
70
—
dB
DC common-mode rejection
ratio9
CMRRDC
Input referred
—
70
—
dB
DRIVESTRENGTH = 2, 3x Gain
connection, 1 kHz, VOUT = 0.1 V
to VOPA - 0.1 V
—
90
—
dB
DRIVESTRENGTH = 0, 3x Gain
connection, 0.1 kHz, VOUT = 0.1 V
to VOPA - 0.1 V
—
90
—
dB
om
DC power supply rejection
ratio9
THDOPA
N
ot
R
ec
Total harmonic distortion
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Rev. 1.4 | 95
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note:
1. Specified configuration for Unit gain buffer configuration is: INCBW = 0, HCMDIS = 0, RESINSEL = DISABLE. VINPUT = 0.5 V,
VOUTPUT = 0.5 V.
es
ig
ns
2. Specified configuration for 3X-Gain configuration is: INCBW = 1, HCMDIS = 1, RESINSEL = VSS, VINPUT = 0.5 V, VOUTPUT = 1.5
V. Nominal voltage gain is 3.
3. If the maximum CLOAD is exceeded, an isolation resistor is required for stability. See AN0038 for more information.
4. Current into the load resistor is excluded. When the OPAMP is connected with closed-loop gain > 1, there will be extra current to
drive the resistor feedback network. The internal resistor feedback network has total resistance of 143.5 kOhm, which will cause
another ~10 µA current when the OPAMP drives 1.5 V between output and ground.
5. In unit gain connection, UGF is the gain-bandwidth product of the OPAMP. In 3x Gain connection, UGF is the gain-bandwidth
product of the OPAMP and 1/3 attenuation of the feedback network.
6. Step between 0.2V and VOPA-0.2V, 10%-90% rising/falling range.
N
ew
D
7. When INCBW is set to 1 the OPAMP bandwidth is increased. This is allowed only when the non-inverting close-loop gain is ≥ 3,
or the OPAMP may not be stable.
8. From enable to output settled. In sample-and-off mode, RC network after OPAMP will contribute extra delay. Settling error < 1mV.
9. When HCMDIS=1 and input common mode transitions the region from VOPA-1.4V to VOPA-1V, input offset will change. PSRR
and CMRR specifications do not apply to this transition region.
fo
r
4.1.21 Pulse Counter (PCNT)
Table 4.45. Pulse Counter (PCNT)
Symbol
Input frequency
FIN
Parameter
Min
Typ
Max
Unit
Asynchronous Single and Quadrature Modes
—
—
10
MHz
Sampled Modes with Debounce
filter set to 0.
—
—
8
kHz
Min
Typ
Max
Unit
Table 4.46. Analog Port (APORT)
Symbol
Test Condition
IAPORT
Operation in EM0/EM1
—
7
—
µA
Operation in EM2/EM3
—
63
—
nA
ec
Supply current1 2
om
4.1.22 Analog Port (APORT)
Test Condition
m
en
de
d
Parameter
N
ot
R
Note:
1. Supply current increase that occurs when an analog peripheral requests access to APORT. This current is not included in reported peripheral currents. Additional peripherals requesting access to APORT do not incur further current.
2. Specified current is for continuous APORT operation. In applications where the APORT is not requested continuously (e.g. periodic ACMP requests from LESENSE in EM2), the average current requirements can be estimated by mutiplying the duty cycle of
the requests by the specified continuous current number.
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.23 I2C
4.1.23.1 I2C Standard-mode (Sm)1
Test Condition
SCL clock frequency2
fSCL
0
SCL clock low time
tLOW
4.7
SCL clock high time
tHIGH
4
SDA set-up time
tSU_DAT
250
SDA hold time3
tHD_DAT
Repeated START condition
set-up time
tSU_STA
tSU_STO
Bus free time between a
STOP and START condition
tBUF
Min
fo
r
(Repeated) START condition tHD_STA
hold time
STOP condition set-up time
Typ
Max
Unit
—
100
kHz
—
—
µs
—
—
µs
—
—
ns
100
D
Symbol
—
3450
ns
4.7
—
—
µs
4
—
—
µs
4
—
—
µs
4.7
—
—
µs
N
ew
Parameter
es
ig
ns
Table 4.47. I2C Standard-mode (Sm)1
N
ot
R
ec
om
m
en
de
d
Note:
1. For CLHR set to 0 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual.
3. The maximum SDA hold time (tHD_DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.23.2 I2C Fast-mode (Fm)1
Symbol
SCL clock frequency2
Typ
Max
Unit
fSCL
0
—
400
kHz
SCL clock low time
tLOW
1.3
—
—
µs
SCL clock high time
tHIGH
0.6
—
—
µs
SDA set-up time
tSU_DAT
100
—
—
ns
SDA hold time3
tHD_DAT
100
—
900
ns
Repeated START condition
set-up time
tSU_STA
0.6
—
—
µs
(Repeated) START condition tHD_STA
hold time
0.6
—
—
µs
0.6
—
—
µs
1.3
—
—
µs
STOP condition set-up time
tSU_STO
Bus free time between a
STOP and START condition
tBUF
Test Condition
N
ew
Parameter
es
ig
ns
Min
D
Table 4.48. I2C Fast-mode (Fm)1
N
ot
R
ec
om
m
en
de
d
fo
r
Note:
1. For CLHR set to 1 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual.
3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.23.3 I2C Fast-mode Plus (Fm+)1
Symbol
SCL clock frequency2
Typ
Max
Unit
fSCL
0
—
1000
kHz
SCL clock low time
tLOW
0.5
—
—
µs
SCL clock high time
tHIGH
0.26
—
—
µs
SDA set-up time
tSU_DAT
50
—
—
ns
SDA hold time
tHD_DAT
100
—
—
ns
Repeated START condition
set-up time
tSU_STA
0.26
—
—
µs
(Repeated) START condition tHD_STA
hold time
0.26
—
—
µs
0.26
—
—
µs
0.5
—
—
µs
STOP condition set-up time
tSU_STO
Bus free time between a
STOP and START condition
tBUF
Test Condition
N
ew
Parameter
es
ig
ns
Min
D
Table 4.49. I2C Fast-mode Plus (Fm+)1
N
ot
R
ec
om
m
en
de
d
fo
r
Note:
1. For CLHR set to 0 or 1 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual.
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Rev. 1.4 | 99
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.24 USART SPI
SPI Master Timing
Symbol
SCLK period 1 2 3
tSCLK
CS to MOSI 1 2
tCS_MO
SCLK to MOSI 1 2
tSCLK_MO
MISO setup time 1 2
tSU_MI
Test Condition
Min
2*
tHFPERCLK
-34
-17.5
Max
Unit
—
—
ns
—
34
ns
—
17.5
ns
—
—
ns
IOVDD = 1.62 V
94
IOVDD = 3.0 V
48
—
—
ns
-9
—
—
ns
N
ew
tH_MI
MISO hold time 1 2
Typ
D
Parameter
es
ig
ns
Table 4.50. SPI Master Timing
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
tCS_MO
m
en
de
d
CS
fo
r
3. tHFPERCLK is one period of the selected HFPERCLK.
tSCKL_MO
SCLK
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1
MOSI
tSU_MI
tH_MI
Figure 4.1. SPI Master Timing Diagram
N
ot
R
ec
om
MISO
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
SPI Slave Timing
Table 4.51. SPI Slave Timing
Min
Typ
Max
Unit
tSCLK
6*
tHFPERCLK
—
—
ns
SCLK high time1 2 3
tSCLK_HI
2.5 *
tHFPERCLK
SCLK low time1 2 3
tSCLK_LO
2.5 *
tHFPERCLK
CS active to MISO 1 2
tCS_ACT_MI
4
CS disable to MISO 1 2
tCS_DIS_MI
4
MOSI setup time 1 2
tSU_MO
MOSI hold time 1 2 3
tH_MO
SCLK to MISO 1 2 3
tSCLK_MI
12.5
es
ig
ns
SCLK period 1 2 3
Test Condition
—
—
ns
—
—
ns
—
70
ns
—
50
ns
—
—
ns
D
Symbol
N
ew
Parameter
13
—
—
ns
6 + 1.5 *
tHFPERCLK
—
45 + 2.5 *
tHFPERCLK
ns
CS
SCLK
CLKPOL = 0
SCLK
CLKPOL = 1
tCS_ACT_MI
om
MOSI
m
en
de
d
3. tHFPERCLK is one period of the selected HFPERCLK.
fo
r
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
tSCLK_HI
tSU_MO
tCS_DIS_MI
tSCLK_LO
tSCLK
tH_MO
tSCLK_MI
Figure 4.2. SPI Slave Timing Diagram
R
ec
MISO
4.2 Typical Performance Curves
N
ot
Typical performance curves indicate typical characterized performance under the stated conditions.
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
es
ig
ns
4.2.1 Supply Current
Figure 4.3. EM0 Active Mode Typical Supply Current vs. Temperature
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Figure 4.4. EM1 Sleep Mode Typical Supply Current vs. Temperature
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
es
ig
ns
Electrical Specifications
Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.
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Rev. 1.4 | 103
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Figure 4.5. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Temperature
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
es
ig
ns
Electrical Specifications
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Figure 4.6. EM0 and EM1 Mode Typical Supply Current vs. Supply
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
es
ig
ns
Electrical Specifications
Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.
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Rev. 1.4 | 105
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Figure 4.7. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Supply
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
es
ig
ns
Electrical Specifications
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.2.2 DC-DC Converter
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
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Default test conditions: CCM mode, LDCDC = 4.7 μH, CDCDC = 4.7 μF, VDCDC_I = 3.3 V, VDCDC_O = 1.8 V, FDCDC_LN = 7 MHz
Figure 4.8. DC-DC Converter Typical Performance Characteristics
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Electrical Specifications
DVDD
DVDD
60mV/div
offset:1.8V
20mV/div
offset:1.8V
100mA
ILOAD
1mA
2V/div
offset:1.8V
10μs/div
100μs/div
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Figure 4.9. DC-DC Converter Transition Waveforms
D
VSW
es
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Load Step Response in LN (CCM) mode
(Heavy Drive)
LN (CCM) and LP mode transition (load: 5mA)
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Electrical Specifications
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4.2.3 2.4 GHz Radio
Figure 4.10. 2.4 GHz RF Transmitter Output Power
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Electrical Specifications
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Figure 4.11. 2.4 GHz RF Receiver Sensitivity
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Typical Connection Diagrams
5. Typical Connection Diagrams
5.1 Power
Typical power supply connections for direct supply, without using the internal DC-DC converter, are shown in the following figure.
VDD
+
–
VREGVDD
AVDD
VREGSW
es
ig
ns
Main
Supply
IOVDD
HFXTAL_N
VREGVSS
HFXTAL_P
DVDD
LFXTAL_N
LFXTAL_P
PAVDD
N
ew
RFVDD
D
DECOUPLE
Figure 5.1. EFR32MG14 Typical Application Circuit: Direct Supply Configuration without DC-DC converter
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Typical power supply circuits using the internal DC-DC converter are shown below. The MCU operates from the DC-DC converter supply. For low RF transmit power applications less than 13dBm, the RF PA may be supplied by the DC-DC converter. For OPNs supporting high power RF transmission, the RF PA must be directly supplied by VDD for RF transmit power greater than 13 dBm.
VDD
+
–
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Main
Supply
VREGVDD
VDCDC
VREGSW
VREGVSS
IOVDD
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
DECOUPLE
RFVDD
PAVDD
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DVDD
AVDD
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R
Figure 5.2. EFR32MG14 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC)
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Typical Connection Diagrams
VDD
+
–
VREGVDD
VDCDC
AVDD
VREGSW
IOVDD
HFXTAL_N
VREGVSS
HFXTAL_P
DVDD
LFXTAL_N
LFXTAL_P
DECOUPLE
PAVDD
D
RFVDD
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Main
Supply
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Figure 5.3. EFR32MG14 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDD)
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Typical Connection Diagrams
5.2 RF Matching Networks
4-Element Match for 2.4GHz Band
2-Element Match for 2.4GHz Band
PAVDD
PAVDD
PAVDD
L0
2G4RF_IOP
50Ω
2G4RF_IOP
C0
C0
2G4RF_ION
L1
50Ω
C1
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2G4RF_ION
L0
D
PAVDD
es
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Typical RF matching network circuit diagrams are shown in Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on
page 113 for applications in the 2.4 GHz band, and in Figure 5.5 Typical Sub-GHz RF impedance-matching network circuits on page
113 for applications in the sub-GHz band. Application-specific component values can be found in the EFR32xG13 Reference Manual.
For low RF transmit power applications less than 13 dBm, the two-element match is recommended. For OPNs supporting high power
RF transmission, the four-element match is recommended for high RF transmit power (> 13 dBm).
Figure 5.4. Typical 2.4 GHz RF impedance-matching network circuits
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Sub-GHz Match Topology I (169-500 MHz)
PAVDD
L1
L2
C0
L3
C5
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SUBGRF_IN
L5
L6
L7
50Ω
C2
C4
L0
C7
C8
C9
C10
C3
SUBGRF_IP
C1
SUBGRF_ON
om
SUBGRF_OP
L4
C0
C6
BAL1
Sub-GHz Match Topology 2 (500-915 MHz)
L3
PAVDD
L5
L6
50Ω
ec
SUBGRF_IN
L0
C4
C7
C8
C9
R
SUBGRF_IP
C1
L4
BAL1
SUBGRF_ON
N
ot
SUBGRF_OP
Figure 5.5. Typical Sub-GHz RF impedance-matching network circuits
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Typical Connection Diagrams
5.3 Other Connections
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Other components or connections may be required to meet the system-level requirements. Application Note AN0002: "Hardware Design Considerations" contains detailed information on these connections. Application Notes can be accessed on the Silicon Labs
website (www.silabs.com/32bit-appnotes).
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Pin Definitions
6. Pin Definitions
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6.1 QFN48 2.4 GHz and Sub-GHz Device Pinout
Figure 6.1. QFN48 2.4 GHz and Sub-GHz Device Pinout
R
ec
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 6.4 GPIO Functionality Table or 6.5 Alternate Functionality Overview.
N
ot
Pin Name
Pin(s)
Table 6.1. QFN48 2.4 GHz and Sub-GHz Device Pinout
Description
Pin Name
Pin(s)
Description
VSS
0
Ground
PF0
1
GPIO (5V)
PF1
2
GPIO (5V)
PF2
3
GPIO (5V)
PF3
4
GPIO (5V)
PF4
5
GPIO (5V)
PF5
6
GPIO (5V)
PF6
7
GPIO (5V)
PF7
8
GPIO (5V)
RFVDD
9
Radio power supply
HFXTAL_N
10
High Frequency Crystal input pin.
HFXTAL_P
11
High Frequency Crystal output pin.
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Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
SUBGRF_OP
13
Sub GHz Differential RF output, positive
path.
SUBGRF_IP
15
Sub GHz Differential RF input, positive
path.
12
SUBGRF_ON
14
Sub GHz Differential RF output, negative path.
SUBGRF_IN
16
Sub GHz Differential RF input, negative
path.
RFVSS
17
Radio Ground
PAVSS
18
Power Amplifier (PA) voltage regulator
VSS
2G4RF_ION
19
2.4 GHz Differential RF input/output,
negative path. This pin should be externally grounded.
2G4RF_IOP
20
2.4 GHz Differential RF input/output,
positive path.
PAVDD
21
Power Amplifier (PA) voltage regulator
VDD input
PD13
22
GPIO
PD14
23
GPIO
PD15
24
GPIO
PA0
25
GPIO
PA1
26
GPIO
PA2
27
GPIO
PA3
28
GPIO
PA4
29
GPIO
PA5
30
GPIO (5V)
PB11
31
GPIO (5V)
PB12
32
GPIO (5V)
PB13
33
GPIO (5V)
AVDD
34
Analog power supply.
PB14
35
GPIO
PB15
36
GPIO
VREGVSS
37
Voltage regulator VSS
VREGSW
38
DCDC regulator switching node
VREGVDD
39
Voltage regulator VDD input
DECOUPLE
41
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
m
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RESETn
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
40
Digital power supply.
IOVDD
42
Digital IO power supply.
PC6
43
GPIO (5V)
PC7
44
GPIO (5V)
PC8
45
GPIO (5V)
PC9
46
GPIO (5V)
PC10
47
GPIO (5V)
PC11
48
GPIO (5V)
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DVDD
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Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PB11, PB12, and PB13 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains.
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Pin Definitions
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6.2 QFN48 2.4 GHz Device Pinout
om
Figure 6.2. QFN48 2.4 GHz Device Pinout
ec
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 6.4 GPIO Functionality Table or 6.5 Alternate Functionality Overview.
Pin(s)
R
Pin Name
Table 6.2. QFN48 2.4 GHz Device Pinout
Description
Pin Name
Pin(s)
Description
0
Ground
PF0
1
GPIO (5V)
PF1
2
GPIO (5V)
PF2
3
GPIO (5V)
PF3
4
GPIO (5V)
PF4
5
GPIO (5V)
PF5
6
GPIO (5V)
PF6
7
GPIO (5V)
PF7
8
GPIO (5V)
RFVDD
9
Radio power supply
HFXTAL_N
10
High Frequency Crystal input pin.
HFXTAL_P
11
High Frequency Crystal output pin.
N
ot
VSS
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Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
Pin(s)
Description
NC
13
No Connect.
PAVSS
15
Power Amplifier (PA) voltage regulator
VSS
12
RFVSS
14
Radio Ground
2G4RF_ION
16
2.4 GHz Differential RF input/output,
negative path. This pin should be externally grounded.
2G4RF_IOP
17
2.4 GHz Differential RF input/output,
positive path.
PAVDD
18
Power Amplifier (PA) voltage regulator
VDD input
PD10
19
GPIO (5V)
PD11
20
GPIO (5V)
PD12
21
GPIO (5V)
PD13
22
GPIO
PD14
23
GPIO
PD15
24
GPIO
PA0
25
GPIO
PA1
26
GPIO
PA2
27
GPIO
PA3
28
GPIO
PA4
29
GPIO
PA5
30
GPIO (5V)
PB11
31
GPIO (5V)
PB12
32
GPIO (5V)
PB13
33
GPIO (5V)
AVDD
34
Analog power supply.
PB14
35
GPIO
PB15
36
GPIO
VREGVSS
37
Voltage regulator VSS
VREGSW
38
DCDC regulator switching node
39
Voltage regulator VDD input
DECOUPLE
41
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
m
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RESETn
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
VREGVDD
40
Digital power supply.
IOVDD
42
Digital IO power supply.
PC6
43
GPIO (5V)
PC7
44
GPIO (5V)
PC8
45
GPIO (5V)
PC9
46
GPIO (5V)
PC10
47
GPIO (5V)
PC11
48
GPIO (5V)
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DVDD
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Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PB11, PB12, and PB13 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains.
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Pin Definitions
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6.3 QFN32 2.4 GHz Device Pinout
om
Figure 6.3. QFN32 2.4 GHz Device Pinout
ec
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 6.4 GPIO Functionality Table or 6.5 Alternate Functionality Overview.
Pin(s)
R
Pin Name
Table 6.3. QFN32 2.4 GHz Device Pinout
Description
Pin Name
Pin(s)
Description
0
Ground
PF0
1
GPIO (5V)
PF1
2
GPIO (5V)
PF2
3
GPIO (5V)
PF3
4
GPIO (5V)
RFVDD
5
Radio power supply
HFXTAL_N
6
High Frequency Crystal input pin.
HFXTAL_P
7
High Frequency Crystal output pin.
N
ot
VSS
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Pin Definitions
Pin Name
Pin(s)
Description
Pin Name
RESETn
8
Reset input, active low. This pin is internally pulled up to AVDD. To apply an
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
PAVSS
10
Power Amplifier (PA) voltage regulator
VSS
2G4RF_IOP
12
2.4 GHz Differential RF input/output,
positive path.
PD13
14
PD15
Pin(s)
Description
9
Radio Ground
2G4RF_ION
11
2.4 GHz Differential RF input/output,
negative path. This pin should be externally grounded.
PAVDD
13
Power Amplifier (PA) voltage regulator
VDD input
GPIO
PD14
15
GPIO
16
GPIO
PA0
17
GPIO
PA1
18
GPIO
PB11
19
GPIO (5V)
PB12
20
GPIO (5V)
PB13
21
GPIO (5V)
AVDD
22
Analog power supply.
PB14
23
GPIO
PB15
24
GPIO
VREGVSS
25
Voltage regulator VSS
VREGSW
26
DCDC regulator switching node
VREGVDD
27
Voltage regulator VDD input
Digital power supply.
IOVDD
30
Digital IO power supply.
PC11
32
GPIO (5V)
D
N
ew
29
Decouple output for on-chip voltage
regulator. An external decoupling capacitor is required at this pin. This pin
should not be used to power any external circuits.
31
GPIO (5V)
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28
DECOUPLE
m
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DVDD
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RFVSS
PC10
N
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R
ec
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Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PB11, PB12, and PB13 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains.
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
6.4 GPIO Functionality Table
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of each GPIO
pin, followed by the functionality available on that pin. Refer to 6.5 Alternate Functionality Overview for a list of GPIO locations available
for each function.
Pin Alternate Functionality / Description
TIM0_CC0 #0
TIM0_CC1 #31
TIM0_CC2 #30
TIM0_CDTI0 #29
TIM0_CDTI1 #28
TIM0_CDTI2 #27
PA0
BUSDY
TIM1_CC0 #0
BUSCX
TIM1_CC1 #31
ADC0_EXTN
TIM1_CC2 #30
TIM1_CC3 #29
WTIM0_CC0 #0
US0_TX #0
US0_RX #31
US0_CLK #30
US0_CS #29
Radio
Other
US0_CTS #28
FRC_DCLK #0
CMU_CLK1 #0
US0_RTS #27
FRC_DOUT #31
PRS_CH6 #0
US1_TX #0
FRC_DFRAME #30
PRS_CH7 #10
US1_RX #31
MODEM_DCLK #0
PRS_CH8 #9
US1_CLK #30
MODEM_DIN #31
PRS_CH9 #8
US1_CS #29
MODEM_DOUT #30
ACMP0_O #0
US1_CTS #28
MODEM_ANT0 #29
ACMP1_O #0
US1_RTS #27
MODEM_ANT1 #28
LES_CH8
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LETIM0_OUT0 #0
Communication
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Analog
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GPIO Name
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Table 6.4. GPIO Functionality Table
LETIM0_OUT1 #31
PCNT0_S0IN #0
LEU0_RX #31
I2C0_SDA #0
I2C0_SCL #31
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PCNT0_S1IN #31
LEU0_TX #0
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Pin Definitions
Pin Alternate Functionality / Description
TIM0_CC1 #0
TIM0_CC2 #31
TIM0_CDTI0 #30
TIM0_CDTI1 #29
BUSCY
BUSDX
PA1
ADC0_EXTP
VDAC0_EXT
TIM0_CDTI2 #28
TIM1_CC0 #1
TIM1_CC1 #0
TIM1_CC2 #31
TIM1_CC3 #30
WTIM0_CC0 #1
LETIM0_OUT0 #1
LETIM0_OUT1 #0
PCNT0_S0IN #1
PCNT0_S1IN #0
PA2
om
VDAC0_OUT1ALT /
OPA1_OUTALT #1
BUSDY
BUSCX
N
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R
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OPA0_P
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Other
US0_TX #1
US0_RX #0
US0_CLK #31
US0_CS #30
US0_CTS #29
FRC_DCLK #1
CMU_CLK0 #0
US0_RTS #28
FRC_DOUT #0
PRS_CH6 #1
US1_TX #1
FRC_DFRAME #31
PRS_CH7 #0
US1_RX #0
MODEM_DCLK #1
PRS_CH8 #10
US1_CLK #31
MODEM_DIN #0
PRS_CH9 #9
US1_CS #30
MODEM_DOUT #31
ACMP0_O #1
US1_CTS #29
MODEM_ANT0 #30
ACMP1_O #1
US1_RTS #28
MODEM_ANT1 #29
LES_CH9
LEU0_TX #1
LEU0_RX #0
I2C0_SDA #1
I2C0_SCL #0
US0_TX #2
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TIM0_CC0 #2
Radio
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TIM0_CC0 #1
Communication
D
Timers
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Analog
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GPIO Name
TIM0_CC1 #1
US0_RX #1
TIM0_CC2 #0
US0_CLK #0
TIM0_CDTI0 #31
US0_CS #31
TIM0_CDTI1 #30
US0_CTS #30
FRC_DCLK #2
TIM0_CDTI2 #29
US0_RTS #29
FRC_DOUT #1
TIM1_CC0 #2
US1_TX #2
FRC_DFRAME #0
TIM1_CC1 #1
US1_RX #1
MODEM_DCLK #2
TIM1_CC2 #0
US1_CLK #0
MODEM_DIN #1
TIM1_CC3 #31
US1_CS #31
MODEM_DOUT #0
WTIM0_CC0 #2
US1_CTS #30
MODEM_ANT0 #31
WTIM0_CC1 #0
US1_RTS #29
MODEM_ANT1 #30
LETIM0_OUT0 #2
LEU0_TX #2
LETIM0_OUT1 #1
LEU0_RX #1
PCNT0_S0IN #2
I2C0_SDA #2
PCNT0_S1IN #1
I2C0_SCL #1
PRS_CH6 #2
PRS_CH7 #1
PRS_CH8 #0
PRS_CH9 #10
ACMP0_O #2
ACMP1_O #2
LES_CH10
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Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
TIM0_CC0 #3
US0_TX #3
TIM0_CC1 #2
US0_RX #2
TIM0_CC2 #1
US0_CLK #1
TIM0_CDTI0 #0
US0_CS #0
TIM0_CDTI1 #31
US0_CTS #31
FRC_DCLK #3
PRS_CH6 #3
TIM0_CDTI2 #30
US0_RTS #30
FRC_DOUT #2
PRS_CH7 #2
BUSCY
TIM1_CC0 #3
US1_TX #3
FRC_DFRAME #1
PRS_CH8 #1
BUSDX
TIM1_CC1 #2
US1_RX #2
MODEM_DCLK #3
PRS_CH9 #0
VDAC0_OUT0 /
OPA0_OUT
TIM1_CC2 #1
US1_CLK #1
MODEM_DIN #2
ACMP0_O #3
TIM1_CC3 #0
US1_CS #0
MODEM_DOUT #1
ACMP1_O #3
WTIM0_CC0 #3
US1_CTS #31
MODEM_ANT0 #0
LES_CH11
WTIM0_CC1 #1
US1_RTS #30
MODEM_ANT1 #31
GPIO_EM4WU8
LETIM0_OUT0 #3
LEU0_TX #3
LETIM0_OUT1 #2
LEU0_RX #2
PCNT0_S0IN #3
I2C0_SDA #3
PCNT0_S1IN #2
TIM0_CC1 #3
TIM0_CC2 #2
TIM0_CDTI0 #1
TIM0_CDTI1 #0
TIM0_CDTI2 #31
PA4
TIM1_CC0 #4
om
VDAC0_OUT1ALT /
OPA1_OUTALT #2
TIM1_CC1 #3
OPA0_N
WTIM0_CC0 #4
BUSDY
N
ot
R
ec
BUSCX
silabs.com | Building a more connected world.
TIM1_CC2 #2
TIM1_CC3 #1
WTIM0_CC1 #2
WTIM0_CC2 #0
LETIM0_OUT0 #4
LETIM0_OUT1 #3
PCNT0_S0IN #4
PCNT0_S1IN #3
Other
D
I2C0_SCL #2
US0_TX #4
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TIM0_CC0 #4
Radio
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Communication
N
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PA3
Timers
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Analog
US0_RX #3
US0_CLK #2
US0_CS #1
US0_CTS #0
FRC_DCLK #4
US0_RTS #31
FRC_DOUT #3
US1_TX #4
FRC_DFRAME #2
US1_RX #3
MODEM_DCLK #4
US1_CLK #2
MODEM_DIN #3
US1_CS #1
MODEM_DOUT #2
US1_CTS #0
MODEM_ANT0 #1
US1_RTS #31
MODEM_ANT1 #0
PRS_CH6 #4
PRS_CH7 #3
PRS_CH8 #2
PRS_CH9 #1
ACMP0_O #4
ACMP1_O #4
LES_CH12
LEU0_TX #4
LEU0_RX #3
I2C0_SDA #4
I2C0_SCL #3
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
Pin Alternate Functionality / Description
TIM0_CC1 #4
TIM0_CC2 #3
TIM0_CDTI0 #2
TIM0_CDTI1 #1
TIM0_CDTI2 #0
TIM1_CC0 #5
VDAC0_OUT0ALT /
OPA0_OUTALT #0
PA5
BUSCY
BUSDX
TIM1_CC1 #4
TIM1_CC2 #3
TIM1_CC3 #2
WTIM0_CC0 #5
WTIM0_CC1 #3
WTIM0_CC2 #1
LETIM0_OUT0 #5
LETIM0_OUT1 #4
PCNT0_S0IN #5
Other
US0_TX #5
US0_RX #4
US0_CLK #3
US0_CS #2
US0_CTS #1
FRC_DCLK #5
CMU_CLKI0 #4
US0_RTS #0
FRC_DOUT #4
PRS_CH6 #5
US1_TX #5
FRC_DFRAME #3
PRS_CH7 #4
US1_RX #4
MODEM_DCLK #5
PRS_CH8 #3
US1_CLK #3
MODEM_DIN #4
PRS_CH9 #2
US1_CS #2
MODEM_DOUT #3
ACMP0_O #5
US1_CTS #1
MODEM_ANT0 #2
ACMP1_O #5
US1_RTS #0
MODEM_ANT1 #1
LES_CH13
LEU0_TX #5
LEU0_RX #4
I2C0_SDA #5
I2C0_SCL #4
N
ot
R
ec
om
m
en
de
d
PCNT0_S1IN #4
Radio
es
ig
ns
TIM0_CC0 #5
Communication
D
Timers
N
ew
Analog
fo
r
GPIO Name
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Rev. 1.4 | 124
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #6
TIM0_CC1 #5
TIM0_CDTI0 #3
US0_RX #5
TIM0_CDTI1 #2
US0_CLK #4
TIM0_CDTI2 #1
US0_CS #3
TIM1_CC0 #6
US0_CTS #2
FRC_DCLK #6
TIM1_CC1 #5
US0_RTS #1
FRC_DOUT #5
PRS_CH6 #6
TIM1_CC2 #4
US1_TX #6
FRC_DFRAME #4
PRS_CH7 #5
BUSCY
TIM1_CC3 #3
US1_RX #5
MODEM_DCLK #6
PRS_CH8 #4
BUSDX
WTIM0_CC0 #15
US1_CLK #4
MODEM_DIN #5
PRS_CH9 #3
WTIM0_CC1 #13
US1_CS #3
MODEM_DOUT #4
ACMP0_O #6
WTIM0_CC2 #11
US1_CTS #2
MODEM_ANT0 #3
ACMP1_O #6
WTIM0_CDTI0 #7
US1_RTS #1
MODEM_ANT1 #2
WTIM0_CDTI1 #5
LEU0_TX #6
WTIM0_CDTI2 #3
D
N
ew
LEU0_RX #5
I2C0_SDA #6
m
en
de
d
LETIM0_OUT0 #6
es
ig
ns
US0_TX #6
fo
r
PB11
TIM0_CC2 #4
LETIM0_OUT1 #5
I2C0_SCL #5
PCNT0_S0IN #6
N
ot
R
ec
om
PCNT0_S1IN #5
silabs.com | Building a more connected world.
Rev. 1.4 | 125
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #7
TIM0_CC1 #6
TIM0_CDTI0 #4
US0_RX #6
TIM0_CDTI1 #3
US0_CLK #5
TIM0_CDTI2 #2
US0_CS #4
TIM1_CC0 #7
US0_CTS #3
FRC_DCLK #7
TIM1_CC1 #6
US0_RTS #2
FRC_DOUT #6
PRS_CH6 #7
TIM1_CC2 #5
US1_TX #7
FRC_DFRAME #5
PRS_CH7 #6
BUSDY
TIM1_CC3 #4
US1_RX #6
MODEM_DCLK #7
PRS_CH8 #5
BUSCX
WTIM0_CC0 #16
US1_CLK #5
MODEM_DIN #6
PRS_CH9 #4
WTIM0_CC1 #14
US1_CS #4
MODEM_DOUT #5
ACMP0_O #7
WTIM0_CC2 #12
US1_CTS #3
MODEM_ANT0 #4
ACMP1_O #7
WTIM0_CDTI0 #8
US1_RTS #2
MODEM_ANT1 #3
WTIM0_CDTI1 #6
LEU0_TX #7
WTIM0_CDTI2 #4
D
N
ew
LEU0_RX #6
I2C0_SDA #7
m
en
de
d
LETIM0_OUT0 #7
es
ig
ns
US0_TX #7
fo
r
PB12
TIM0_CC2 #5
LETIM0_OUT1 #6
I2C0_SCL #6
PCNT0_S0IN #7
N
ot
R
ec
om
PCNT0_S1IN #6
silabs.com | Building a more connected world.
Rev. 1.4 | 126
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #8
TIM0_CC1 #7
TIM0_CDTI0 #5
US0_RX #7
TIM0_CDTI1 #4
US0_CLK #6
TIM0_CDTI2 #3
US0_CS #5
TIM1_CC0 #8
US0_CTS #4
FRC_DCLK #8
TIM1_CC1 #7
US0_RTS #3
FRC_DOUT #7
TIM1_CC2 #6
US1_TX #8
FRC_DFRAME #6
BUSCY
TIM1_CC3 #5
US1_RX #7
MODEM_DCLK #8
BUSDX
WTIM0_CC0 #17
US1_CLK #6
MODEM_DIN #7
WTIM0_CC1 #15
US1_CS #5
MODEM_DOUT #6
WTIM0_CC2 #13
US1_CTS #4
MODEM_ANT0 #5
WTIM0_CDTI0 #9
US1_RTS #3
MODEM_ANT1 #4
WTIM0_CDTI1 #7
LEU0_TX #8
WTIM0_CDTI2 #5
D
N
ew
CMU_CLKI0 #0
PRS_CH6 #8
PRS_CH7 #7
PRS_CH8 #6
PRS_CH9 #5
ACMP0_O #8
ACMP1_O #8
DBG_SWO #1
GPIO_EM4WU9
LEU0_RX #7
I2C0_SDA #8
m
en
de
d
LETIM0_OUT0 #8
es
ig
ns
US0_TX #8
fo
r
PB13
TIM0_CC2 #6
LETIM0_OUT1 #7
I2C0_SCL #7
PCNT0_S0IN #8
N
ot
R
ec
om
PCNT0_S1IN #7
silabs.com | Building a more connected world.
Rev. 1.4 | 127
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #9
TIM0_CC1 #8
BUSCX
LFXTAL_N
US0_RX #8
TIM0_CDTI1 #5
US0_CLK #7
TIM0_CDTI2 #4
US0_CS #6
TIM1_CC0 #9
US0_CTS #5
FRC_DCLK #9
TIM1_CC1 #8
US0_RTS #4
FRC_DOUT #8
TIM1_CC2 #7
US1_TX #9
FRC_DFRAME #7
TIM1_CC3 #6
US1_RX #8
MODEM_DCLK #9
WTIM0_CC0 #18
US1_CLK #7
MODEM_DIN #8
WTIM0_CC1 #16
US1_CS #6
MODEM_DOUT #7
WTIM0_CC2 #14
US1_CTS #5
MODEM_ANT0 #6
WTIM0_CDTI0 #10
US1_RTS #4
MODEM_ANT1 #5
WTIM0_CDTI1 #8
LEU0_TX #9
WTIM0_CDTI2 #6
D
CMU_CLK1 #1
PRS_CH6 #9
PRS_CH7 #8
PRS_CH8 #7
PRS_CH9 #6
ACMP0_O #9
ACMP1_O #9
LEU0_RX #8
I2C0_SDA #9
m
en
de
d
LETIM0_OUT0 #9
es
ig
ns
TIM0_CDTI0 #6
N
ew
PB14
US0_TX #9
fo
r
BUSDY
TIM0_CC2 #7
LETIM0_OUT1 #8
I2C0_SCL #8
PCNT0_S0IN #9
N
ot
R
ec
om
PCNT0_S1IN #8
silabs.com | Building a more connected world.
Rev. 1.4 | 128
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #10
TIM0_CC1 #9
BUSDX
LFXTAL_P
US0_RX #9
TIM0_CDTI1 #6
US0_CLK #8
TIM0_CDTI2 #5
US0_CS #7
TIM1_CC0 #10
US0_CTS #6
FRC_DCLK #10
TIM1_CC1 #9
US0_RTS #5
FRC_DOUT #9
TIM1_CC2 #8
US1_TX #10
FRC_DFRAME #8
TIM1_CC3 #7
US1_RX #9
MODEM_DCLK #10
WTIM0_CC0 #19
US1_CLK #8
MODEM_DIN #9
WTIM0_CC1 #17
US1_CS #7
MODEM_DOUT #8
WTIM0_CC2 #15
US1_CTS #6
MODEM_ANT0 #7
WTIM0_CDTI0 #11
US1_RTS #5
MODEM_ANT1 #6
WTIM0_CDTI1 #9
LEU0_TX #10
WTIM0_CDTI2 #7
D
CMU_CLK0 #1
PRS_CH6 #10
PRS_CH7 #9
PRS_CH8 #8
PRS_CH9 #7
ACMP0_O #10
ACMP1_O #10
LEU0_RX #9
I2C0_SDA #10
m
en
de
d
LETIM0_OUT0 #10
es
ig
ns
TIM0_CDTI0 #7
N
ew
PB15
US0_TX #10
fo
r
BUSCY
TIM0_CC2 #8
LETIM0_OUT1 #9
I2C0_SCL #9
PCNT0_S0IN #10
N
ot
R
ec
om
PCNT0_S1IN #9
silabs.com | Building a more connected world.
Rev. 1.4 | 129
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #11
TIM0_CC1 #10
TIM0_CDTI0 #8
US0_RX #10
TIM0_CDTI1 #7
US0_CLK #9
TIM0_CDTI2 #6
US0_CS #8
TIM1_CC0 #11
US0_CTS #7
FRC_DCLK #11
CMU_CLK0 #2
TIM1_CC1 #10
US0_RTS #6
FRC_DOUT #10
CMU_CLKI0 #2
TIM1_CC2 #9
US1_TX #11
FRC_DFRAME #9
PRS_CH0 #8
BUSBY
TIM1_CC3 #8
US1_RX #10
MODEM_DCLK #11
PRS_CH9 #11
BUSAX
WTIM0_CC0 #26
US1_CLK #9
MODEM_DIN #10
PRS_CH10 #0
WTIM0_CC1 #24
US1_CS #8
MODEM_DOUT #9
PRS_CH11 #5
WTIM0_CC2 #22
US1_CTS #7
MODEM_ANT0 #8
ACMP0_O #11
WTIM0_CDTI0 #18
US1_RTS #6
MODEM_ANT1 #7
ACMP1_O #11
WTIM0_CDTI1 #16
LEU0_TX #11
WTIM0_CDTI2 #14
D
N
ew
LEU0_RX #10
I2C0_SDA #11
m
en
de
d
LETIM0_OUT0 #11
es
ig
ns
US0_TX #11
fo
r
PC6
TIM0_CC2 #9
LETIM0_OUT1 #10
I2C0_SCL #10
PCNT0_S0IN #11
N
ot
R
ec
om
PCNT0_S1IN #10
silabs.com | Building a more connected world.
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #12
TIM0_CC1 #11
TIM0_CDTI0 #9
US0_RX #11
TIM0_CDTI1 #8
US0_CLK #10
TIM0_CDTI2 #7
US0_CS #9
TIM1_CC0 #12
US0_CTS #8
FRC_DCLK #12
TIM1_CC1 #11
US0_RTS #7
FRC_DOUT #11
TIM1_CC2 #10
US1_TX #12
FRC_DFRAME #10
BUSAY
TIM1_CC3 #9
US1_RX #11
MODEM_DCLK #12
BUSBX
WTIM0_CC0 #27
US1_CLK #10
MODEM_DIN #11
WTIM0_CC1 #25
US1_CS #9
MODEM_DOUT #10
WTIM0_CC2 #23
US1_CTS #8
MODEM_ANT0 #9
WTIM0_CDTI0 #19
US1_RTS #7
MODEM_ANT1 #8
WTIM0_CDTI1 #17
LEU0_TX #12
WTIM0_CDTI2 #15
D
N
ew
CMU_CLK1 #2
PRS_CH0 #9
PRS_CH9 #12
PRS_CH10 #1
PRS_CH11 #0
ACMP0_O #12
ACMP1_O #12
LEU0_RX #11
I2C0_SDA #12
m
en
de
d
LETIM0_OUT0 #12
es
ig
ns
US0_TX #12
fo
r
PC7
TIM0_CC2 #10
LETIM0_OUT1 #11
I2C0_SCL #11
PCNT0_S0IN #12
N
ot
R
ec
om
PCNT0_S1IN #11
silabs.com | Building a more connected world.
Rev. 1.4 | 131
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #13
TIM0_CC1 #12
TIM0_CDTI0 #10
US0_RX #12
TIM0_CDTI1 #9
US0_CLK #11
TIM0_CDTI2 #8
US0_CS #10
TIM1_CC0 #13
US0_CTS #9
FRC_DCLK #13
TIM1_CC1 #12
US0_RTS #8
FRC_DOUT #12
PRS_CH0 #10
TIM1_CC2 #11
US1_TX #13
FRC_DFRAME #11
PRS_CH9 #13
BUSBY
TIM1_CC3 #10
US1_RX #12
MODEM_DCLK #13
PRS_CH10 #2
BUSAX
WTIM0_CC0 #28
US1_CLK #11
MODEM_DIN #12
PRS_CH11 #1
WTIM0_CC1 #26
US1_CS #10
MODEM_DOUT #11
ACMP0_O #13
WTIM0_CC2 #24
US1_CTS #9
MODEM_ANT0 #10
ACMP1_O #13
WTIM0_CDTI0 #20
US1_RTS #8
MODEM_ANT1 #9
WTIM0_CDTI1 #18
LEU0_TX #13
WTIM0_CDTI2 #16
D
N
ew
LEU0_RX #12
I2C0_SDA #13
m
en
de
d
LETIM0_OUT0 #13
es
ig
ns
US0_TX #13
fo
r
PC8
TIM0_CC2 #11
LETIM0_OUT1 #12
I2C0_SCL #12
PCNT0_S0IN #13
N
ot
R
ec
om
PCNT0_S1IN #12
silabs.com | Building a more connected world.
Rev. 1.4 | 132
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #14
TIM0_CC1 #13
TIM0_CDTI0 #11
US0_RX #13
TIM0_CDTI1 #10
US0_CLK #12
TIM0_CDTI2 #9
US0_CS #11
TIM1_CC0 #14
US0_CTS #10
FRC_DCLK #14
TIM1_CC1 #13
US0_RTS #9
FRC_DOUT #13
PRS_CH0 #11
TIM1_CC2 #12
US1_TX #14
FRC_DFRAME #12
PRS_CH9 #14
BUSAY
TIM1_CC3 #11
US1_RX #13
MODEM_DCLK #14
PRS_CH10 #3
BUSBX
WTIM0_CC0 #29
US1_CLK #12
MODEM_DIN #13
PRS_CH11 #2
WTIM0_CC1 #27
US1_CS #11
MODEM_DOUT #12
ACMP0_O #14
WTIM0_CC2 #25
US1_CTS #10
MODEM_ANT0 #11
ACMP1_O #14
WTIM0_CDTI0 #21
US1_RTS #9
MODEM_ANT1 #10
WTIM0_CDTI1 #19
LEU0_TX #14
WTIM0_CDTI2 #17
D
N
ew
LEU0_RX #13
I2C0_SDA #14
m
en
de
d
LETIM0_OUT0 #14
es
ig
ns
US0_TX #14
fo
r
PC9
TIM0_CC2 #12
LETIM0_OUT1 #13
I2C0_SCL #13
PCNT0_S0IN #14
N
ot
R
ec
om
PCNT0_S1IN #13
silabs.com | Building a more connected world.
Rev. 1.4 | 133
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #15
TIM0_CC1 #14
TIM0_CDTI0 #12
US0_RX #14
TIM0_CDTI1 #11
US0_CLK #13
TIM0_CDTI2 #10
US0_CS #12
TIM1_CC0 #15
US0_CTS #11
FRC_DCLK #15
CMU_CLK1 #3
TIM1_CC1 #14
US0_RTS #10
FRC_DOUT #14
PRS_CH0 #12
TIM1_CC2 #13
US1_TX #15
FRC_DFRAME #13
PRS_CH9 #15
BUSBY
TIM1_CC3 #12
US1_RX #14
MODEM_DCLK #15
PRS_CH10 #4
BUSAX
WTIM0_CC0 #30
US1_CLK #13
MODEM_DIN #14
PRS_CH11 #3
WTIM0_CC1 #28
US1_CS #12
MODEM_DOUT #13
ACMP0_O #15
WTIM0_CC2 #26
US1_CTS #11
MODEM_ANT0 #12
ACMP1_O #15
WTIM0_CDTI0 #22
US1_RTS #10
MODEM_ANT1 #11
GPIO_EM4WU12
WTIM0_CDTI1 #20
LEU0_TX #15
WTIM0_CDTI2 #18
D
N
ew
LEU0_RX #14
I2C0_SDA #15
m
en
de
d
LETIM0_OUT0 #15
es
ig
ns
US0_TX #15
fo
r
PC10
TIM0_CC2 #13
LETIM0_OUT1 #14
I2C0_SCL #14
PCNT0_S0IN #15
N
ot
R
ec
om
PCNT0_S1IN #14
silabs.com | Building a more connected world.
Rev. 1.4 | 134
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #16
TIM0_CC1 #15
TIM0_CDTI0 #13
US0_RX #15
TIM0_CDTI1 #12
US0_CLK #14
TIM0_CDTI2 #11
US0_CS #13
TIM1_CC0 #16
US0_CTS #12
FRC_DCLK #16
CMU_CLK0 #3
TIM1_CC1 #15
US0_RTS #11
FRC_DOUT #15
PRS_CH0 #13
TIM1_CC2 #14
US1_TX #16
FRC_DFRAME #14
PRS_CH9 #16
BUSAY
TIM1_CC3 #13
US1_RX #15
MODEM_DCLK #16
PRS_CH10 #5
BUSBX
WTIM0_CC0 #31
US1_CLK #14
MODEM_DIN #15
PRS_CH11 #4
WTIM0_CC1 #29
US1_CS #13
MODEM_DOUT #14
ACMP0_O #16
WTIM0_CC2 #27
US1_CTS #12
MODEM_ANT0 #13
ACMP1_O #16
WTIM0_CDTI0 #23
US1_RTS #11
MODEM_ANT1 #12
DBG_SWO #3
WTIM0_CDTI1 #21
LEU0_TX #16
WTIM0_CDTI2 #19
D
N
ew
LEU0_RX #15
I2C0_SDA #16
m
en
de
d
LETIM0_OUT0 #16
es
ig
ns
US0_TX #16
fo
r
PC11
TIM0_CC2 #14
LETIM0_OUT1 #15
I2C0_SCL #15
PCNT0_S0IN #16
N
ot
R
ec
om
PCNT0_S1IN #15
silabs.com | Building a more connected world.
Rev. 1.4 | 135
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #18
TIM0_CC2 #16
US0_RX #17
TIM0_CDTI0 #15
US0_CLK #16
TIM0_CDTI1 #14
US0_CS #15
TIM0_CDTI2 #13
US0_CTS #14
FRC_DCLK #18
CMU_CLK1 #4
TIM1_CC0 #18
US0_RTS #13
FRC_DOUT #17
PRS_CH3 #9
TIM1_CC1 #17
US1_TX #18
FRC_DFRAME #16
PRS_CH4 #1
BUSDY
TIM1_CC2 #16
US1_RX #17
MODEM_DCLK #18
PRS_CH5 #0
BUSCX
TIM1_CC3 #15
US1_CLK #16
MODEM_DIN #17
PRS_CH6 #12
WTIM0_CC2 #30
US1_CS #15
MODEM_DOUT #16
ACMP0_O #18
WTIM0_CDTI0 #26
US1_CTS #14
MODEM_ANT0 #15
ACMP1_O #18
WTIM0_CDTI1 #24
US1_RTS #13
MODEM_ANT1 #14
LES_CH2
WTIM0_CDTI2 #22
LEU0_TX #18
LETIM0_OUT0 #18
LEU0_RX #17
LETIM0_OUT1 #17
D
N
ew
I2C0_SDA #18
I2C0_SCL #17
m
en
de
d
PCNT0_S0IN #18
es
ig
ns
US0_TX #18
fo
r
PD10
TIM0_CC1 #17
N
ot
R
ec
om
PCNT0_S1IN #17
silabs.com | Building a more connected world.
Rev. 1.4 | 136
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #19
TIM0_CC2 #17
US0_RX #18
TIM0_CDTI0 #16
US0_CLK #17
TIM0_CDTI1 #15
US0_CS #16
TIM0_CDTI2 #14
US0_CTS #15
FRC_DCLK #19
TIM1_CC0 #19
US0_RTS #14
FRC_DOUT #18
TIM1_CC1 #18
US1_TX #19
FRC_DFRAME #17
BUSCY
TIM1_CC2 #17
US1_RX #18
MODEM_DCLK #19
BUSDX
TIM1_CC3 #16
US1_CLK #17
MODEM_DIN #18
WTIM0_CC2 #31
US1_CS #16
MODEM_DOUT #17
WTIM0_CDTI0 #27
US1_CTS #15
MODEM_ANT0 #16
WTIM0_CDTI1 #25
US1_RTS #14
MODEM_ANT1 #15
WTIM0_CDTI2 #23
LEU0_TX #19
LETIM0_OUT0 #19
LEU0_RX #18
LETIM0_OUT1 #18
D
N
ew
PRS_CH3 #10
PRS_CH4 #2
PRS_CH5 #1
PRS_CH6 #13
ACMP0_O #19
ACMP1_O #19
LES_CH3
I2C0_SDA #19
I2C0_SCL #18
m
en
de
d
PCNT0_S0IN #19
es
ig
ns
US0_TX #19
fo
r
PD11
TIM0_CC1 #18
PCNT0_S1IN #18
TIM0_CC0 #20
TIM0_CC1 #19
TIM0_CC2 #18
TIM0_CDTI0 #17
om
TIM0_CDTI1 #16
ec
VDAC0_OUT1ALT /
OPA1_OUTALT #0
BUSDY
BUSCX
N
ot
R
PD12
TIM0_CDTI2 #15
TIM1_CC0 #20
TIM1_CC1 #19
TIM1_CC2 #18
TIM1_CC3 #17
WTIM0_CDTI0 #28
WTIM0_CDTI1 #26
WTIM0_CDTI2 #24
LETIM0_OUT0 #20
LETIM0_OUT1 #19
PCNT0_S0IN #20
PCNT0_S1IN #19
silabs.com | Building a more connected world.
US0_TX #20
US0_RX #19
US0_CLK #18
US0_CS #17
US0_CTS #16
FRC_DCLK #20
US0_RTS #15
FRC_DOUT #19
US1_TX #20
FRC_DFRAME #18
US1_RX #19
MODEM_DCLK #20
US1_CLK #18
MODEM_DIN #19
US1_CS #17
MODEM_DOUT #18
US1_CTS #16
MODEM_ANT0 #17
US1_RTS #15
MODEM_ANT1 #16
PRS_CH3 #11
PRS_CH4 #3
PRS_CH5 #2
PRS_CH6 #14
ACMP0_O #20
ACMP1_O #20
LES_CH4
LEU0_TX #20
LEU0_RX #19
I2C0_SDA #20
I2C0_SCL #19
Rev. 1.4 | 137
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
Pin Alternate Functionality / Description
TIM0_CC1 #20
TIM0_CC2 #19
TIM0_CDTI0 #18
TIM0_CDTI1 #17
TIM0_CDTI2 #16
VDAC0_OUT0ALT /
OPA0_OUTALT #1
BUSCY
PD13
BUSDX
OPA1_P
TIM1_CC0 #21
TIM1_CC1 #20
TIM1_CC2 #19
TIM1_CC3 #18
WTIM0_CDTI0 #29
WTIM0_CDTI1 #27
WTIM0_CDTI2 #25
LETIM0_OUT0 #21
LETIM0_OUT1 #20
PCNT0_S0IN #21
TIM0_CC0 #22
TIM0_CC1 #21
TIM0_CC2 #20
TIM0_CDTI0 #19
TIM0_CDTI1 #18
om
TIM0_CDTI2 #17
BUSDY
PD14
BUSCX
N
ot
R
ec
VDAC0_OUT1 /
OPA1_OUT
TIM1_CC0 #22
TIM1_CC1 #21
TIM1_CC2 #20
TIM1_CC3 #19
WTIM0_CDTI0 #30
WTIM0_CDTI1 #28
WTIM0_CDTI2 #26
LETIM0_OUT0 #22
LETIM0_OUT1 #21
PCNT0_S0IN #22
PCNT0_S1IN #21
silabs.com | Building a more connected world.
Other
US0_TX #21
US0_RX #20
US0_CLK #19
US0_CS #18
US0_CTS #17
FRC_DCLK #21
US0_RTS #16
FRC_DOUT #20
US1_TX #21
FRC_DFRAME #19
US1_RX #20
MODEM_DCLK #21
US1_CLK #19
MODEM_DIN #20
US1_CS #18
MODEM_DOUT #19
US1_CTS #17
MODEM_ANT0 #18
US1_RTS #16
MODEM_ANT1 #17
PRS_CH3 #12
PRS_CH4 #4
PRS_CH5 #3
PRS_CH6 #15
ACMP0_O #21
ACMP1_O #21
LES_CH5
LEU0_TX #21
LEU0_RX #20
I2C0_SDA #21
I2C0_SCL #20
m
en
de
d
PCNT0_S1IN #20
Radio
es
ig
ns
TIM0_CC0 #21
Communication
D
Timers
N
ew
Analog
fo
r
GPIO Name
US0_TX #22
US0_RX #21
US0_CLK #20
US0_CS #19
US0_CTS #18
FRC_DCLK #22
US0_RTS #17
FRC_DOUT #21
US1_TX #22
FRC_DFRAME #20
US1_RX #21
MODEM_DCLK #22
US1_CLK #20
MODEM_DIN #21
US1_CS #19
MODEM_DOUT #20
US1_CTS #18
MODEM_ANT0 #19
US1_RTS #17
MODEM_ANT1 #18
LEU0_TX #22
CMU_CLK0 #5
PRS_CH3 #13
PRS_CH4 #5
PRS_CH5 #4
PRS_CH6 #16
ACMP0_O #22
ACMP1_O #22
LES_CH6
GPIO_EM4WU4
LEU0_RX #21
I2C0_SDA #22
I2C0_SCL #21
Rev. 1.4 | 138
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
Pin Alternate Functionality / Description
TIM0_CC1 #22
TIM0_CC2 #21
TIM0_CDTI0 #20
TIM0_CDTI1 #19
TIM0_CDTI2 #18
VDAC0_OUT0ALT /
OPA0_OUTALT #2
BUSCY
PD15
BUSDX
OPA1_N
TIM1_CC0 #23
TIM1_CC1 #22
TIM1_CC2 #21
TIM1_CC3 #20
WTIM0_CDTI0 #31
WTIM0_CDTI1 #29
WTIM0_CDTI2 #27
LETIM0_OUT0 #23
LETIM0_OUT1 #22
PCNT0_S0IN #23
US0_RX #22
US0_CLK #21
US0_CS #20
US0_CTS #19
FRC_DCLK #23
US0_RTS #18
FRC_DOUT #22
US1_TX #23
FRC_DFRAME #21
US1_RX #22
MODEM_DCLK #23
US1_CLK #21
MODEM_DIN #22
US1_CS #20
MODEM_DOUT #21
US1_CTS #19
MODEM_ANT0 #20
US1_RTS #18
MODEM_ANT1 #19
LEU0_TX #23
CMU_CLK1 #5
PRS_CH3 #14
PRS_CH4 #6
PRS_CH5 #5
PRS_CH6 #17
ACMP0_O #23
ACMP1_O #23
LES_CH7
DBG_SWO #2
LEU0_RX #22
I2C0_SDA #23
I2C0_SCL #22
US0_TX #24
TIM0_CC1 #23
US0_RX #23
TIM0_CC2 #22
US0_CLK #22
TIM0_CDTI0 #21
US0_CS #21
TIM0_CDTI1 #20
US0_CTS #20
FRC_DCLK #24
PRS_CH0 #0
TIM0_CDTI2 #19
US0_RTS #19
FRC_DOUT #23
PRS_CH1 #7
TIM1_CC0 #24
US1_TX #24
FRC_DFRAME #22
PRS_CH2 #6
BUSBY
TIM1_CC1 #23
US1_RX #23
MODEM_DCLK #24
PRS_CH3 #5
BUSAX
TIM1_CC2 #22
US1_CLK #22
MODEM_DIN #23
ACMP0_O #24
TIM1_CC3 #21
US1_CS #21
MODEM_DOUT #22
ACMP1_O #24
WTIM0_CDTI1 #30
US1_CTS #20
MODEM_ANT0 #21
DBG_SWCLKTCK
WTIM0_CDTI2 #28
US1_RTS #19
MODEM_ANT1 #20
BOOT_TX
LETIM0_OUT0 #24
LEU0_TX #24
LETIM0_OUT1 #23
LEU0_RX #23
PCNT0_S0IN #24
I2C0_SDA #24
PCNT0_S1IN #23
I2C0_SCL #23
om
TIM0_CC0 #24
N
ot
R
ec
PF0
Other
US0_TX #23
m
en
de
d
PCNT0_S1IN #22
Radio
es
ig
ns
TIM0_CC0 #23
Communication
D
Timers
N
ew
Analog
fo
r
GPIO Name
silabs.com | Building a more connected world.
Rev. 1.4 | 139
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
TIM0_CC0 #25
US0_TX #25
TIM0_CC1 #24
US0_RX #24
TIM0_CC2 #23
US0_CLK #23
TIM0_CDTI0 #22
US0_CS #22
TIM0_CDTI1 #21
US0_CTS #21
FRC_DCLK #25
PRS_CH0 #1
TIM0_CDTI2 #20
US0_RTS #20
FRC_DOUT #24
PRS_CH1 #0
TIM1_CC0 #25
US1_TX #25
FRC_DFRAME #23
PRS_CH2 #7
BUSAY
TIM1_CC1 #24
US1_RX #24
MODEM_DCLK #25
PRS_CH3 #6
BUSBX
TIM1_CC2 #23
US1_CLK #23
MODEM_DIN #24
ACMP0_O #25
TIM1_CC3 #22
US1_CS #22
MODEM_DOUT #23
ACMP1_O #25
WTIM0_CDTI1 #31
US1_CTS #21
MODEM_ANT0 #22
DBG_SWDIOTMS
WTIM0_CDTI2 #29
US1_RTS #20
MODEM_ANT1 #21
BOOT_RX
LETIM0_OUT0 #25
LEU0_TX #25
LETIM0_OUT1 #24
LEU0_RX #24
PCNT0_S0IN #25
I2C0_SDA #25
PCNT0_S1IN #24
TIM0_CC1 #25
TIM0_CC2 #24
TIM0_CDTI0 #23
TIM0_CDTI1 #22
TIM0_CDTI2 #21
om
BUSBY
BUSAX
N
ot
R
ec
PF2
silabs.com | Building a more connected world.
TIM1_CC0 #26
TIM1_CC1 #25
TIM1_CC2 #24
TIM1_CC3 #23
WTIM0_CDTI2 #30
LETIM0_OUT0 #26
LETIM0_OUT1 #25
PCNT0_S0IN #26
PCNT0_S1IN #25
Other
D
I2C0_SCL #24
US0_TX #26
m
en
de
d
TIM0_CC0 #26
Radio
es
ig
ns
Communication
N
ew
PF1
Timers
fo
r
Analog
US0_RX #25
US0_CLK #24
US0_CS #23
CMU_CLK0 #6
US0_CTS #22
FRC_DCLK #26
PRS_CH0 #2
US0_RTS #21
FRC_DOUT #25
PRS_CH1 #1
US1_TX #26
FRC_DFRAME #24
PRS_CH2 #0
US1_RX #25
MODEM_DCLK #26
PRS_CH3 #7
US1_CLK #24
MODEM_DIN #25
ACMP0_O #26
US1_CS #23
MODEM_DOUT #24
ACMP1_O #26
US1_CTS #22
MODEM_ANT0 #23
DBG_TDO
US1_RTS #21
MODEM_ANT1 #22
DBG_SWO #0
LEU0_TX #26
GPIO_EM4WU0
LEU0_RX #25
I2C0_SDA #26
I2C0_SCL #25
Rev. 1.4 | 140
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
Pin Alternate Functionality / Description
TIM0_CC1 #26
TIM0_CC2 #25
TIM0_CDTI0 #24
TIM0_CDTI1 #23
TIM0_CDTI2 #22
BUSAY
PF3
BUSBX
TIM1_CC0 #27
TIM1_CC1 #26
TIM1_CC2 #25
TIM1_CC3 #24
WTIM0_CDTI2 #31
LETIM0_OUT0 #27
LETIM0_OUT1 #26
PCNT0_S0IN #27
PCNT0_S1IN #26
Radio
Other
US0_TX #27
US0_RX #26
US0_CLK #25
US0_CS #24
es
ig
ns
TIM0_CC0 #27
Communication
US0_CTS #23
FRC_DCLK #27
CMU_CLK1 #6
US0_RTS #22
FRC_DOUT #26
PRS_CH0 #3
US1_TX #27
FRC_DFRAME #25
PRS_CH1 #2
US1_RX #26
MODEM_DCLK #27
PRS_CH2 #1
US1_CLK #25
MODEM_DIN #26
PRS_CH3 #0
US1_CS #24
MODEM_DOUT #25
ACMP0_O #27
D
Timers
N
ew
Analog
US1_CTS #23
MODEM_ANT0 #24
ACMP1_O #27
US1_RTS #22
MODEM_ANT1 #23
DBG_TDI
LEU0_TX #27
LEU0_RX #26
I2C0_SDA #27
fo
r
GPIO Name
I2C0_SCL #26
m
en
de
d
US0_TX #28
TIM0_CC1 #27
US0_CLK #26
TIM0_CC2 #26
US0_CS #25
TIM0_CDTI0 #25
US0_CTS #24
FRC_DCLK #28
TIM0_CDTI1 #24
US0_RTS #23
FRC_DOUT #27
PRS_CH0 #4
TIM0_CDTI2 #23
US1_TX #28
FRC_DFRAME #26
PRS_CH1 #3
BUSBY
TIM1_CC0 #28
US1_RX #27
MODEM_DCLK #28
PRS_CH2 #2
BUSAX
TIM1_CC1 #27
US1_CLK #26
MODEM_DIN #27
PRS_CH3 #1
TIM1_CC2 #26
US1_CS #25
MODEM_DOUT #26
ACMP0_O #28
TIM1_CC3 #25
US1_CTS #24
MODEM_ANT0 #25
ACMP1_O #28
LETIM0_OUT0 #28
US1_RTS #23
MODEM_ANT1 #24
LETIM0_OUT1 #27
LEU0_TX #28
PCNT0_S0IN #28
LEU0_RX #27
PCNT0_S1IN #27
I2C0_SDA #28
om
US0_RX #27
N
ot
R
ec
PF4
TIM0_CC0 #28
silabs.com | Building a more connected world.
I2C0_SCL #27
Rev. 1.4 | 141
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
US0_TX #29
TIM0_CC1 #28
US0_CLK #27
TIM0_CC2 #27
US0_CS #26
TIM0_CDTI0 #26
US0_CTS #25
FRC_DCLK #29
TIM0_CDTI1 #25
US0_RTS #24
FRC_DOUT #28
PRS_CH0 #5
TIM0_CDTI2 #24
US1_TX #29
FRC_DFRAME #27
PRS_CH1 #4
BUSAY
TIM1_CC0 #29
US1_RX #28
MODEM_DCLK #29
PRS_CH2 #3
BUSBX
TIM1_CC1 #28
US1_CLK #27
MODEM_DIN #28
PRS_CH3 #2
TIM1_CC2 #27
US1_CS #26
MODEM_DOUT #27
ACMP0_O #29
TIM1_CC3 #26
US1_CTS #25
MODEM_ANT0 #26
LETIM0_OUT0 #29
US1_RTS #24
MODEM_ANT1 #25
LETIM0_OUT1 #28
LEU0_TX #29
PCNT0_S0IN #29
LEU0_RX #28
PCNT0_S1IN #28
I2C0_SDA #29
N
ew
D
es
ig
ns
US0_RX #28
ACMP1_O #29
fo
r
PF5
TIM0_CC0 #29
I2C0_SCL #28
m
en
de
d
US0_TX #30
TIM0_CC1 #29
US0_CLK #28
TIM0_CC2 #28
US0_CS #27
TIM0_CDTI0 #27
US0_CTS #26
FRC_DCLK #30
TIM0_CDTI1 #26
US0_RTS #25
FRC_DOUT #29
TIM0_CDTI2 #25
US1_TX #30
FRC_DFRAME #28
BUSBY
TIM1_CC0 #30
US1_RX #29
MODEM_DCLK #30
BUSAX
TIM1_CC1 #29
US1_CLK #28
MODEM_DIN #29
TIM1_CC2 #28
US1_CS #27
MODEM_DOUT #28
TIM1_CC3 #27
US1_CTS #26
MODEM_ANT0 #27
LETIM0_OUT0 #30
US1_RTS #25
MODEM_ANT1 #26
LETIM0_OUT1 #29
LEU0_TX #30
PCNT0_S0IN #30
LEU0_RX #29
PCNT0_S1IN #29
I2C0_SDA #30
om
US0_RX #29
N
ot
R
ec
PF6
TIM0_CC0 #30
silabs.com | Building a more connected world.
CMU_CLK1 #7
PRS_CH0 #6
PRS_CH1 #5
PRS_CH2 #4
PRS_CH3 #3
ACMP0_O #30
ACMP1_O #30
I2C0_SCL #29
Rev. 1.4 | 142
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
US0_TX #31
TIM0_CC1 #30
US0_CLK #29
TIM0_CC2 #29
US0_CS #28
TIM0_CDTI0 #28
US0_CTS #27
FRC_DCLK #31
TIM0_CDTI1 #27
US0_RTS #26
FRC_DOUT #30
TIM0_CDTI2 #26
US1_TX #31
FRC_DFRAME #29
BUSAY
TIM1_CC0 #31
US1_RX #30
MODEM_DCLK #31
BUSBX
TIM1_CC1 #30
US1_CLK #29
MODEM_DIN #30
TIM1_CC2 #29
US1_CS #28
MODEM_DOUT #29
TIM1_CC3 #28
US1_CTS #27
MODEM_ANT0 #28
LETIM0_OUT0 #31
US1_RTS #26
MODEM_ANT1 #27
LETIM0_OUT1 #30
LEU0_TX #31
PCNT0_S0IN #31
LEU0_RX #30
PCNT0_S1IN #30
I2C0_SDA #31
N
ew
D
es
ig
ns
US0_RX #30
CMU_CLKI0 #1
CMU_CLK0 #7
PRS_CH0 #7
PRS_CH1 #6
PRS_CH2 #5
PRS_CH3 #4
ACMP0_O #31
ACMP1_O #31
GPIO_EM4WU1
fo
r
PF7
TIM0_CC0 #31
N
ot
R
ec
om
m
en
de
d
I2C0_SCL #30
silabs.com | Building a more connected world.
Rev. 1.4 | 143
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
6.5 Alternate Functionality Overview
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings and the associated GPIO
pin. Refer to 6.4 GPIO Functionality Table for a list of functions available on each GPIO pin.
Table 6.5. Alternate Functionality Overview
Alternate
LOCATION
ACMP1_O
8 - 11
12 - 15
16 - 19
20 - 23
0: PA0
4: PA4
8: PB13
1: PA1
5: PA5
2: PA2
12: PC7
16: PC11
20: PD12
24: PF0
9: PB14
13: PC8
18: PD10
21: PD13
25: PF1
29: PF5
6: PB11
10: PB15
14: PC9
19: PD11
22: PD14
26: PF2
30: PF6
3: PA3
7: PB12
11: PC6
15: PC10
0: PA0
4: PA4
8: PB13
12: PC7
1: PA1
5: PA5
9: PB14
2: PA2
6: PB11
3: PA3
7: PB12
0: PA0
0: PA1
ADC0_EXTP
BOOT_RX
0: PF1
BOOT_TX
0: PF0
CMU_CLK0
28: PF4
27: PF3
31: PF7
16: PC11
20: PD12
24: PF0
28: PF4
13: PC8
18: PD10
21: PD13
25: PF1
29: PF5
10: PB15
14: PC9
19: PD11
22: PD14
26: PF2
30: PF6
11: PC6
15: PC10
27: PF3
31: PF7
23: PD15
Description
Analog comparator
ACMP0, digital output.
Analog comparator
ACMP1, digital output.
Analog to digital
converter ADC0 external reference input negative pin.
Analog to digital
converter ADC0 external reference input positive pin.
Bootloader RX.
Bootloader TX.
5: PD14
om
0: PA1
28 - 31
23: PD15
m
en
de
d
ADC0_EXTN
24 - 27
D
4-7
N
ew
ACMP0_O
0-3
fo
r
Functionality
es
ig
ns
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
1: PB15
6: PF2
2: PC6
7: PF7
Clock Management
Unit, clock output
number 0.
ec
3: PC11
4: PD10
1: PB14
5: PD15
2: PC7
6: PF3
3: PC10
7: PF6
0: PB13
4: PA5
R
0: PA0
N
ot
CMU_CLK1
CMU_CLKI0
1: PF7
2: PC6
silabs.com | Building a more connected world.
Clock Management
Unit, clock output
number 1.
Clock Management
Unit, clock input
number 0.
Rev. 1.4 | 144
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0-3
4-7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
0: PF0
Debug-interface
Serial Wire clock
input and JTAG
Test Clock.
DBG_SWCLKTCK
es
ig
ns
Note that this function is enabled to
the pin out of reset,
and has a built-in
pull down.
D
0: PF1
N
ew
DBG_SWDIOTMS
0: PF2
fo
r
1: PB13
2: PD15
3: PC11
0: PF3
ec
Debug-interface
JTAG Test Data
Out.
Note that this function becomes available after the first
valid JTAG command is received.
R
DBG_TDO
N
ot
Debug-interface
Serial Wire viewer
Output.
Note that this function becomes available after the first
valid JTAG command is received,
and has a built-in
pull up when JTAG
is active.
0: PF2
FRC_DCLK
Note that this function is enabled to
the pin out of reset,
and has a built-in
pull up.
Debug-interface
JTAG Test Data In.
om
DBG_TDI
Debug-interface
Serial Wire data input / output and
JTAG Test Mode
Select.
Note that this function is not enabled
after reset, and
must be enabled by
software to be
used.
m
en
de
d
DBG_SWO
Description
0: PA0
4: PA4
8: PB13
12: PC7
16: PC11
20: PD12
24: PF0
28: PF4
1: PA1
5: PA5
9: PB14
13: PC8
18: PD10
21: PD13
25: PF1
29: PF5
2: PA2
6: PB11
10: PB15
14: PC9
19: PD11
22: PD14
26: PF2
30: PF6
3: PA3
7: PB12
11: PC6
15: PC10
23: PD15
27: PF3
31: PF7
silabs.com | Building a more connected world.
Frame Controller,
Data Sniffer Clock.
Rev. 1.4 | 145
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
LOCATION
Functionality
FRC_DFRAME
FRC_DOUT
16 - 19
20 - 23
12: PC9
16: PD10
20: PD14
24: PF2
28: PF6
9: PC6
13: PC10
17: PD11
21: PD15
25: PF3
29: PF7
6: PB13
10: PC7
14: PC11
18: PD12
22: PF0
26: PF4
30: PA0
3: PA5
7: PB14
11: PC8
19: PD13
23: PF1
27: PF5
0: PA1
4: PA5
8: PB14
12: PC8
17: PD10
20: PD13
24: PF1
1: PA2
5: PB11
9: PB15
13: PC9
18: PD11
21: PD14
25: PF2
2: PA3
6: PB12
10: PC6
14: PC10
19: PD12
22: PD15
26: PF3
3: PA4
7: PB13
11: PC7
15: PC11
23: PF0
27: PF4
es
ig
ns
Alternate
0-3
4-7
8 - 11
12 - 15
0: PA2
4: PB11
8: PB15
1: PA3
5: PB12
2: PA4
0: PF7
GPIO_EM4WU1
0: PD14
0: PA3
0: PB13
0: PC10
GPIO_EM4WU12
0: PA1
LES_CH4
LES_CH5
Pin can be used to
wake the system
up from EM4
Pin can be used to
wake the system
up from EM4
24: PF1
28: PF5
5: PB11
9: PB15
13: PC9
18: PD11
21: PD14
25: PF2
29: PF6
6: PB12
10: PC6
14: PC10
19: PD12
22: PD15
26: PF3
30: PF7
3: PA4
7: PB13
11: PC7
15: PC11
23: PF0
27: PF4
31: PA0
0: PA0
4: PA4
8: PB13
12: PC7
16: PC11
20: PD12
24: PF0
28: PF4
1: PA1
5: PA5
9: PB14
13: PC8
18: PD10
21: PD13
25: PF1
29: PF5
2: PA2
6: PB11
10: PB15
14: PC9
19: PD11
22: PD14
26: PF2
30: PF6
7: PB12
11: PC6
15: PC10
23: PD15
27: PF3
31: PF7
ec
N
ot
LES_CH3
Pin can be used to
wake the system
up from EM4
Pin can be used to
wake the system
up from EM4
20: PD13
2: PA3
Pin can be used to
wake the system
up from EM4
Pin can be used to
wake the system
up from EM4
17: PD10
1: PA2
Frame Controller,
Data Sniffer Output.
31: PA0
12: PC8
3: PA3
LES_CH2
30: PF7
8: PB14
R
I2C0_SDA
29: PF6
4: PA5
om
I2C0_SCL
m
en
de
d
GPIO_EM4WU8
Frame Controller,
Data Sniffer Frame
active
28: PF5
fo
r
GPIO_EM4WU4
Description
31: PA1
N
ew
GPIO_EM4WU0
GPIO_EM4WU9
28 - 31
D
0: PF2
24 - 27
I2C0 Serial Clock
Line input / output.
I2C0 Serial Data input / output.
0: PD10
LESENSE channel
2.
0: PD11
LESENSE channel
3.
0: PD12
LESENSE channel
4.
0: PD13
LESENSE channel
5.
silabs.com | Building a more connected world.
Rev. 1.4 | 146
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
LES_CH12
LES_CH13
LETIM0_OUT0
LETIM0_OUT1
Description
LESENSE channel
6.
0: PD15
LESENSE channel
7.
0: PA0
LESENSE channel
8.
0: PA1
LESENSE channel
9.
0: PA2
LESENSE channel
10.
0: PA3
0: PA4
0: PA5
0: PA0
4: PA4
8: PB13
12: PC7
16: PC11
20: PD12
24: PF0
28: PF4
1: PA1
5: PA5
9: PB14
13: PC8
18: PD10
21: PD13
25: PF1
29: PF5
2: PA2
6: PB11
10: PB15
14: PC9
22: PD14
26: PF2
30: PF6
3: PA3
7: PB12
11: PC6
15: PC10
23: PD15
27: PF3
31: PF7
0: PA1
4: PA5
8: PB14
12: PC8
17: PD10
20: PD13
24: PF1
28: PF5
5: PB11
9: PB15
13: PC9
18: PD11
21: PD14
25: PF2
29: PF6
6: PB12
10: PC6
14: PC10
19: PD12
22: PD15
26: PF3
30: PF7
7: PB13
11: PC7
15: PC11
23: PF0
27: PF4
31: PA0
4: PA5
8: PB14
12: PC8
17: PD10
20: PD13
24: PF1
28: PF5
5: PB11
9: PB15
13: PC9
18: PD11
21: PD14
25: PF2
29: PF6
6: PB12
10: PC6
14: PC10
19: PD12
22: PD15
26: PF3
30: PF7
23: PF0
27: PF4
31: PA0
1: PA2
2: PA3
0: PA1
1: PA2
2: PA3
19: PD11
7: PB13
11: PC7
15: PC11
0: PA0
4: PA4
8: PB13
12: PC7
16: PC11
20: PD12
24: PF0
28: PF4
1: PA1
5: PA5
9: PB14
13: PC8
18: PD10
21: PD13
25: PF1
29: PF5
2: PA2
6: PB11
10: PB15
14: PC9
19: PD11
22: PD14
26: PF2
30: PF6
3: PA3
7: PB12
11: PC6
15: PC10
23: PD15
27: PF3
31: PF7
ec
3: PA4
R
LEU0_TX
28 - 31
0: PD14
3: PA4
LEU0_RX
24 - 27
es
ig
ns
LES_CH11
20 - 23
D
LES_CH10
16 - 19
N
ew
LES_CH9
12 - 15
fo
r
LES_CH8
8 - 11
m
en
de
d
LES_CH7
4-7
om
LES_CH6
0-3
LESENSE channel
11.
LESENSE channel
12.
LESENSE channel
13.
Low Energy Timer
LETIM0, output
channel 0.
Low Energy Timer
LETIM0, output
channel 1.
LEUART0 Receive
input.
LEUART0 Transmit
output. Also used
as receive input in
half duplex communication.
Low Frequency
Crystal (typically
32.768 kHz) negative pin. Also used
as an optional external clock input
pin.
0: PB15
Low Frequency
Crystal (typically
32.768 kHz) positive pin.
N
ot
0: PB14
LFXTAL_N
LFXTAL_P
silabs.com | Building a more connected world.
Rev. 1.4 | 147
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
LOCATION
MODEM_DIN
MODEM_DOUT
16 - 19
20 - 23
4: PB12
1: PA4
8: PC6
12: PC10
16: PD11
20: PD15
24: PF3
28: PF7
5: PB13
9: PC7
13: PC11
17: PD12
21: PF0
25: PF4
29: PA0
2: PA5
6: PB14
10: PC8
15: PD10
18: PD13
22: PF1
26: PF5
30: PA1
3: PB11
7: PB15
11: PC9
19: PD14
23: PF2
27: PF6
0: PA4
4: PB13
8: PC7
12: PC11
16: PD12
20: PF0
24: PF4
1: PA5
5: PB14
9: PC8
14: PD10
17: PD13
21: PF1
25: PF5
2: PB11
6: PB15
10: PC9
15: PD11
18: PD14
22: PF2
26: PF6
3: PB12
7: PC6
11: PC10
19: PD15
23: PF3
27: PF7
0: PA0
4: PA4
8: PB13
12: PC7
16: PC11
20: PD12
24: PF0
1: PA1
5: PA5
9: PB14
13: PC8
18: PD10
21: PD13
25: PF1
2: PA2
6: PB11
10: PB15
14: PC9
19: PD11
3: PA3
7: PB12
11: PC6
15: PC10
0: PA1
4: PA5
8: PB14
12: PC8
1: PA2
5: PB11
9: PB15
2: PA3
6: PB12
3: PA4
0: PA2
1: PA3
2: PA4
3: PA5
0: PA4
OPA0_N
0: PA2
28 - 31
29: PA1
30: PA2
28: PF4
29: PF5
26: PF2
30: PF6
23: PD15
27: PF3
31: PF7
17: PD10
20: PD13
24: PF1
28: PF5
13: PC9
18: PD11
21: PD14
25: PF2
29: PF6
10: PC6
14: PC10
19: PD12
22: PD15
26: PF3
30: PF7
7: PB13
11: PC7
15: PC11
23: PF0
27: PF4
31: PA0
4: PB11
8: PB15
12: PC9
20: PD14
24: PF2
28: PF6
5: PB12
9: PC6
13: PC10
17: PD11
21: PD15
25: PF3
29: PF7
6: PB13
10: PC7
14: PC11
18: PD12
22: PF0
26: PF4
30: PA0
7: PB14
11: PC8
19: PD13
23: PF1
27: PF5
31: PA1
MODEM data in.
MODEM data out.
Operational Amplifier 0 external positive input.
Operational Amplifier 1 external negative input.
ec
R
N
ot
PCNT0_S0IN
MODEM data clock
out.
Operational Amplifier 0 external negative input.
0: PD13
OPA1_P
MODEM antenna
control output 1,
used for antenna
diversity.
31: PA3
0: PD15
OPA1_N
MODEM antenna
control output 0,
used for antenna
diversity.
28: PA0
22: PD14
16: PD10
Description
31: PA2
om
OPA0_P
24 - 27
D
0: PA3
8 - 11
N
ew
MODEM_DCLK
4-7
fo
r
MODEM_ANT1
0-3
m
en
de
d
Functionality
MODEM_ANT0
12 - 15
es
ig
ns
Alternate
Operational Amplifier 1 external positive input.
0: PA0
4: PA4
8: PB13
12: PC7
16: PC11
20: PD12
24: PF0
28: PF4
1: PA1
5: PA5
9: PB14
13: PC8
18: PD10
21: PD13
25: PF1
29: PF5
2: PA2
6: PB11
10: PB15
14: PC9
19: PD11
22: PD14
26: PF2
30: PF6
3: PA3
7: PB12
11: PC6
15: PC10
23: PD15
27: PF3
31: PF7
silabs.com | Building a more connected world.
Pulse Counter
PCNT0 input number 0.
Rev. 1.4 | 148
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
LOCATION
PRS_CH2
PRS_CH3
12 - 15
20 - 23
0: PA1
4: PA5
8: PB14
1: PA2
5: PB11
2: PA3
12: PC8
17: PD10
20: PD13
24: PF1
28: PF5
9: PB15
13: PC9
18: PD11
21: PD14
25: PF2
29: PF6
6: PB12
10: PC6
14: PC10
19: PD12
22: PD15
26: PF3
30: PF7
3: PA4
7: PB13
11: PC7
15: PC11
23: PF0
27: PF4
0: PF0
4: PF4
8: PC6
12: PC10
1: PF1
5: PF5
9: PC7
13: PC11
2: PF2
6: PF6
10: PC8
3: PF3
7: PF7
11: PC9
0: PF1
4: PF5
1: PF2
5: PF6
2: PF3
6: PF7
3: PF4
7: PF0
0: PF2
4: PF6
1: PF3
5: PF7
2: PF4
6: PF0
3: PF5
7: PF1
0: PF3
4: PF7
1: PF4
2: PF5
3: PF6
1: PD10
PRS_CH4
2: PD11
3: PD12
1: PD11
9: PD10
Description
Pulse Counter
PCNT0 input number 1.
31: PA0
Peripheral Reflex
System PRS, channel 1.
Peripheral Reflex
System PRS, channel 2.
12: PD13
5: PF0
10: PD11
13: PD14
6: PF1
11: PD12
14: PD15
Peripheral Reflex
System PRS, channel 3.
7: PF2
4: PD13
5: PD14
6: PD15
Peripheral Reflex
System PRS, channel 4.
4: PD14
Peripheral Reflex
System PRS, channel 5.
5: PD15
2: PD12
ec
PRS_CH5
28 - 31
Peripheral Reflex
System PRS, channel 0.
om
0: PD10
24 - 27
D
8 - 11
N
ew
PRS_CH1
4-7
fo
r
PRS_CH0
0-3
m
en
de
d
Functionality
PCNT0_S1IN
16 - 19
es
ig
ns
Alternate
3: PD13
0: PA0
8: PB13
12: PD10
16: PD14
1: PA1
5: PA5
9: PB14
13: PD11
17: PD15
2: PA2
6: PB11
10: PB15
14: PD12
3: PA3
7: PB12
0: PA1
4: PA5
8: PB14
1: PA2
5: PB11
9: PB15
2: PA3
6: PB12
10: PA0
3: PA4
7: PB13
R
4: PA4
N
ot
PRS_CH6
PRS_CH7
silabs.com | Building a more connected world.
Peripheral Reflex
System PRS, channel 6.
15: PD13
Peripheral Reflex
System PRS, channel 7.
Rev. 1.4 | 149
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
LOCATION
PRS_CH9
PRS_CH10
4-7
8 - 11
12 - 15
0: PA2
4: PB11
8: PB15
1: PA3
5: PB12
9: PA0
2: PA4
6: PB13
10: PA1
3: PA5
7: PB14
0: PA3
4: PB12
8: PA0
12: PC7
1: PA4
5: PB13
9: PA1
13: PC8
2: PA5
6: PB14
10: PA2
14: PC9
3: PB11
7: PB15
11: PC6
15: PC10
0: PC6
4: PC10
1: PC7
5: PC11
16 - 19
16: PC11
1: PC8
5: PC6
2: PC9
3: PC10
0: PA0
1: PA1
24: PF0
28: PF4
18: PD10
21: PD13
25: PF1
29: PF5
6: PB11
10: PB15
14: PC9
19: PD11
22: PD14
26: PF2
30: PF6
7: PB12
11: PC6
15: PC10
23: PD15
27: PF3
31: PF7
4: PA5
8: PB14
12: PC8
17: PD10
20: PD13
24: PF1
28: PF5
5: PB11
9: PB15
13: PC9
18: PD11
21: PD14
25: PF2
29: PF6
6: PB12
10: PC6
14: PC10
19: PD12
22: PD15
26: PF3
30: PF7
7: PB13
11: PC7
15: PC11
23: PF0
27: PF4
31: PA0
0: PA2
4: PB11
8: PB15
12: PC9
16: PD10
20: PD14
24: PF2
28: PF6
1: PA3
5: PB12
9: PC6
13: PC10
17: PD11
21: PD15
25: PF3
29: PF7
2: PA4
6: PB13
10: PC7
14: PC11
18: PD12
22: PF0
26: PF4
30: PA0
3: PA5
7: PB14
11: PC8
19: PD13
23: PF1
27: PF5
31: PA1
0: PA3
4: PB12
8: PC6
12: PC10
16: PD11
20: PD15
24: PF3
28: PF7
1: PA4
5: PB13
9: PC7
13: PC11
17: PD12
21: PF0
25: PF4
29: PA0
2: PA5
6: PB14
10: PC8
15: PD10
18: PD13
22: PF1
26: PF5
30: PA1
3: PB11
7: PB15
11: PC9
19: PD14
23: PF2
27: PF6
31: PA2
0: PA4
4: PB13
8: PC7
12: PC11
16: PD12
20: PF0
24: PF4
28: PA0
1: PA5
5: PB14
9: PC8
14: PD10
17: PD13
21: PF1
25: PF5
29: PA1
2: PB11
6: PB15
10: PC9
15: PD11
18: PD14
22: PF2
26: PF6
30: PA2
3: PB12
7: PC6
11: PC10
19: PD15
23: PF3
27: PF7
31: PA3
2: PA2
1: PA2
2: PA3
om
ec
R
N
ot
TIM0_CDTI1
20: PD12
13: PC8
3: PA4
TIM0_CDTI0
16: PC11
9: PB14
0: PA1
TIM0_CC2
12: PC7
5: PA5
3: PA3
TIM0_CC1
8: PB13
m
en
de
d
TIM0_CC0
4: PA4
fo
r
PRS_CH11
28 - 31
silabs.com | Building a more connected world.
Description
Peripheral Reflex
System PRS, channel 9.
3: PC9
4: PC11
24 - 27
Peripheral Reflex
System PRS, channel 8.
2: PC8
0: PC7
20 - 23
D
PRS_CH8
0-3
N
ew
Functionality
es
ig
ns
Alternate
Peripheral Reflex
System PRS, channel 10.
Peripheral Reflex
System PRS, channel 11.
Timer 0 Capture
Compare input /
output channel 0.
Timer 0 Capture
Compare input /
output channel 1.
Timer 0 Capture
Compare input /
output channel 2.
Timer 0 Complimentary Dead Time
Insertion channel 0.
Timer 0 Complimentary Dead Time
Insertion channel 1.
Rev. 1.4 | 150
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
LOCATION
TIM1_CC2
TIM1_CC3
16 - 19
4: PB14
1: PB11
8: PC8
13: PD10
16: PD13
20: PF1
24: PF5
28: PA1
5: PB15
9: PC9
14: PD11
17: PD14
21: PF2
25: PF6
29: PA2
2: PB12
6: PC6
10: PC10
15: PD12
18: PD15
22: PF3
26: PF7
30: PA3
3: PB13
7: PC7
11: PC11
19: PF0
23: PF4
27: PA0
0: PA0
4: PA4
8: PB13
12: PC7
16: PC11
20: PD12
24: PF0
1: PA1
5: PA5
9: PB14
13: PC8
18: PD10
21: PD13
25: PF1
2: PA2
6: PB11
10: PB15
14: PC9
19: PD11
22: PD14
26: PF2
3: PA3
7: PB12
11: PC6
15: PC10
23: PD15
27: PF3
0: PA1
4: PA5
8: PB14
12: PC8
17: PD10
20: PD13
24: PF1
1: PA2
5: PB11
9: PB15
13: PC9
18: PD11
21: PD14
25: PF2
2: PA3
6: PB12
10: PC6
14: PC10
19: PD12
3: PA4
7: PB13
11: PC7
15: PC11
0: PA2
4: PB11
8: PB15
12: PC9
1: PA3
5: PB12
9: PC6
2: PA4
6: PB13
10: PC7
3: PA5
7: PB14
11: PC8
0: PA3
4: PB12
8: PC6
1: PA4
30: PF6
28: PF5
29: PF6
26: PF3
30: PF7
23: PF0
27: PF4
31: PA0
16: PD10
20: PD14
24: PF2
28: PF6
13: PC10
17: PD11
21: PD15
25: PF3
29: PF7
14: PC11
18: PD12
22: PF0
26: PF4
30: PA0
19: PD13
23: PF1
27: PF5
31: PA1
16: PD11
20: PD15
24: PF3
28: PF7
25: PF4
29: PA0
6: PB14
10: PC8
15: PD10
18: PD13
22: PF1
26: PF5
30: PA1
7: PB15
11: PC9
19: PD14
23: PF2
27: PF6
31: PA2
4: PB11
8: PB15
12: PC9
16: PD10
20: PD14
24: PF2
28: PF6
5: PB12
9: PC6
13: PC10
17: PD11
21: PD15
25: PF3
29: PF7
6: PB13
10: PC7
14: PC11
18: PD12
22: PF0
26: PF4
30: PA0
7: PB14
11: PC8
19: PD13
23: PF1
27: PF5
31: PA1
0: PA3
4: PB12
8: PC6
12: PC10
16: PD11
20: PD15
24: PF3
28: PF7
1: PA4
5: PB13
9: PC7
13: PC11
17: PD12
21: PF0
25: PF4
29: PA0
2: PA5
6: PB14
10: PC8
15: PD10
18: PD13
22: PF1
26: PF5
30: PA1
3: PB11
7: PB15
11: PC9
19: PD14
23: PF2
27: PF6
31: PA2
0: PA4
4: PB13
8: PC7
12: PC11
16: PD12
20: PF0
24: PF4
28: PA0
1: PA5
5: PB14
9: PC8
14: PD10
17: PD13
21: PF1
25: PF5
29: PA1
2: PB11
6: PB15
10: PC9
15: PD11
18: PD14
22: PF2
26: PF6
30: PA2
3: PB12
7: PC6
11: PC10
19: PD15
23: PF3
27: PF7
31: PA3
0: PA5
4: PB14
8: PC8
13: PD10
16: PD13
20: PF1
24: PF5
28: PA1
1: PB11
5: PB15
9: PC9
14: PD11
17: PD14
21: PF2
25: PF6
29: PA2
2: PB12
6: PC6
10: PC10
15: PD12
18: PD15
22: PF3
26: PF7
30: PA3
3: PB13
7: PC7
11: PC11
19: PF0
23: PF4
27: PA0
31: PA4
1: PA3
2: PA4
om
ec
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Timer 1 Capture
Compare input /
output channel 0.
31: PF7
21: PF0
R
N
ot
US0_RTS
29: PF5
17: PD12
2: PA5
Timer 0 Complimentary Dead Time
Insertion channel 2.
28: PF4
22: PD15
12: PC10
Description
31: PA4
13: PC11
3: PA5
US0_CTS
28 - 31
9: PC7
0: PA2
US0_CS
24 - 27
5: PB13
3: PB11
US0_CLK
20 - 23
D
0: PA5
8 - 11
N
ew
TIM1_CC1
4-7
fo
r
TIM1_CC0
0-3
m
en
de
d
Functionality
TIM0_CDTI2
12 - 15
es
ig
ns
Alternate
Timer 1 Capture
Compare input /
output channel 1.
Timer 1 Capture
Compare input /
output channel 2.
Timer 1 Capture
Compare input /
output channel 3.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Clear To
Send hardware
flow control input.
USART0 Request
To Send hardware
flow control output.
Rev. 1.4 | 151
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
Functionality
US0_RX
0-3
4-7
8 - 11
12 - 15
20 - 23
0: PA1
4: PA5
8: PB14
1: PA2
5: PB11
2: PA3
24 - 27
28 - 31
12: PC8
17: PD10
20: PD13
24: PF1
28: PF5
9: PB15
13: PC9
18: PD11
21: PD14
25: PF2
29: PF6
6: PB12
10: PC6
14: PC10
19: PD12
22: PD15
26: PF3
30: PF7
3: PA4
7: PB13
11: PC7
15: PC11
23: PF0
27: PF4
0: PA0
4: PA4
8: PB13
12: PC7
16: PC11
20: PD12
24: PF0
1: PA1
5: PA5
9: PB14
13: PC8
18: PD10
21: PD13
25: PF1
2: PA2
6: PB11
10: PB15
14: PC9
19: PD11
22: PD14
26: PF2
3: PA3
7: PB12
11: PC6
15: PC10
23: PD15
27: PF3
0: PA2
4: PB11
8: PB15
12: PC9
16: PD10
20: PD14
24: PF2
28: PF6
1: PA3
5: PB12
9: PC6
13: PC10
17: PD11
21: PD15
25: PF3
29: PF7
2: PA4
6: PB13
10: PC7
14: PC11
18: PD12
22: PF0
26: PF4
30: PA0
3: PA5
7: PB14
11: PC8
19: PD13
23: PF1
27: PF5
31: PA1
0: PA3
4: PB12
8: PC6
12: PC10
16: PD11
20: PD15
24: PF3
28: PF7
1: PA4
5: PB13
9: PC7
13: PC11
17: PD12
21: PF0
25: PF4
29: PA0
2: PA5
6: PB14
10: PC8
15: PD10
18: PD13
22: PF1
26: PF5
30: PA1
7: PB15
11: PC9
19: PD14
23: PF2
27: PF6
31: PA2
4: PB13
8: PC7
12: PC11
16: PD12
20: PF0
24: PF4
28: PA0
5: PB14
9: PC8
14: PD10
17: PD13
21: PF1
25: PF5
29: PA1
6: PB15
10: PC9
15: PD11
18: PD14
22: PF2
26: PF6
30: PA2
7: PC6
11: PC10
19: PD15
23: PF3
27: PF7
31: PA3
4: PB14
8: PC8
13: PD10
16: PD13
20: PF1
24: PF5
28: PA1
31: PA0
28: PF4
29: PF5
30: PF6
31: PF7
3: PB11
0: PA4
US1_CTS
1: PA5
2: PB11
3: PB12
0: PA5
1: PB11
5: PB15
9: PC9
14: PD11
17: PD14
21: PF2
25: PF6
29: PA2
2: PB12
6: PC6
10: PC10
15: PD12
18: PD15
22: PF3
26: PF7
30: PA3
3: PB13
7: PC7
11: PC11
19: PF0
23: PF4
27: PA0
31: PA4
0: PA1
4: PA5
8: PB14
12: PC8
17: PD10
20: PD13
24: PF1
28: PF5
1: PA2
5: PB11
9: PB15
13: PC9
18: PD11
21: PD14
25: PF2
29: PF6
2: PA3
6: PB12
10: PC6
14: PC10
19: PD12
22: PD15
26: PF3
30: PF7
3: PA4
7: PB13
11: PC7
15: PC11
23: PF0
27: PF4
31: PA0
R
ec
US1_RTS
N
ot
US1_RX
fo
r
US1_CS
m
en
de
d
US1_CLK
N
ew
D
US0_TX
16 - 19
es
ig
ns
LOCATION
om
Alternate
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Description
USART0 Asynchronous Receive.
USART0 Synchronous mode Master
Input / Slave Output (MISO).
USART0 Asynchronous Transmit. Also used as receive
input in half duplex
communication.
USART0 Synchronous mode Master
Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Clear To
Send hardware
flow control input.
USART1 Request
To Send hardware
flow control output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master
Input / Slave Output (MISO).
Rev. 1.4 | 152
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
LOCATION
Functionality
US1_TX
16 - 19
20 - 23
12: PC7
16: PC11
20: PD12
24: PF0
28: PF4
9: PB14
13: PC8
18: PD10
21: PD13
25: PF1
29: PF5
6: PB11
10: PB15
14: PC9
19: PD11
22: PD14
26: PF2
30: PF6
7: PB12
11: PC6
15: PC10
23: PD15
27: PF3
es
ig
ns
Alternate
0-3
4-7
8 - 11
12 - 15
0: PA0
4: PA4
8: PB13
1: PA1
5: PA5
2: PA2
3: PA3
24 - 27
0: PA1
0: PA3
N
ew
VDAC0_OUT0 /
OPA0_OUT
0: PA5
1: PD13
2: PD15
fo
r
VDAC0_OUT0AL
T / OPA0_OUTALT
0: PD14
0: PD12
1: PA2
2: PA4
0: PA0
WTIM0_CC0
1: PA1
2: PA2
15: PB11
5: PA5
16: PB12
26: PC6
28: PC8
17: PB13
27: PC7
29: PC9
18: PB14
30: PC10
19: PB15
31: PC11
16: PB14
24: PC6
28: PC10
1: PA3
14: PB12
17: PB15
25: PC7
29: PC11
15: PB13
26: PC8
R
3: PA5
N
ot
0: PA4
WTIM0_CC2
1: PA5
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USART1 Asynchronous Transmit. Also used as receive
input in half duplex
communication.
USART1 Synchronous mode Master
Output / Slave Input (MOSI).
Digital to analog
converter VDAC0
external reference
input pin.
Digital to Analog
Converter DAC0
output channel
number 0.
Digital to Analog
Converter DAC0 alternative output for
channel 0.
Digital to Analog
Converter DAC0 alternative output for
channel 1.
13: PB11
2: PA4
Description
Digital to Analog
Converter DAC0
output channel
number 1.
0: PA2
ec
WTIM0_CC1
4: PA4
om
3: PA3
m
en
de
d
VDAC0_OUT1 /
OPA1_OUT
VDAC0_OUT1AL
T / OPA1_OUTALT
31: PF7
D
VDAC0_EXT
28 - 31
Wide timer 0 Capture Compare input / output channel
0.
Wide timer 0 Capture Compare input / output channel
1.
27: PC9
11: PB11
12: PB12
22: PC6
24: PC8
30: PD10
13: PB13
23: PC7
25: PC9
31: PD11
14: PB14
26: PC10
15: PB15
27: PC11
Wide timer 0 Capture Compare input / output channel
2.
Rev. 1.4 | 153
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
4-7
8 - 11
7: PB11
WTIM0_CDTI0
WTIM0_CDTI1
12 - 15
16 - 19
20 - 23
8: PB12
18: PC6
9: PB13
19: PC7
20: PC8
26: PD10
28: PD12
21: PC9
27: PD11
29: PD13
Description
Wide timer 0 Complimentary Dead
Time Insertion
channel 0.
22: PC10
30: PD14
11: PB15
23: PC11
31: PD15
5: PB11
8: PB14
16: PC6
20: PC10
24: PD10
6: PB12
9: PB15
17: PC7
21: PC11
25: PD11
18: PC8
26: PD12
19: PC9
27: PD13
4: PB12
14: PC6
16: PC8
22: PD10
24: PD12
5: PB13
15: PC7
17: PC9
23: PD11
25: PD13
28: PD14
29: PD15
30: PF0
Wide timer 0 Complimentary Dead
Time Insertion
channel 1.
31: PF1
28: PF0
29: PF1
N
ew
WTIM0_CDTI2
28 - 31
10: PB14
7: PB13
3: PB11
24 - 27
es
ig
ns
0-3
D
Functionality
6: PB14
18: PC10
26: PD14
30: PF2
7: PB15
19: PC11
27: PD15
31: PF3
Wide timer 0 Complimentary Dead
Time Insertion
channel 2.
Certain alternate function locations may have non-interference priority. These locations will take precedence over any other functions
selected on that pin (i.e. another alternate function enabled to the same pin inadvertently).
fo
r
Some alternate functions may also have high speed priority on certain locations. These locations ensure the fastest possible paths to
the pins for timing-critical signals.
m
en
de
d
The following table lists the alternate functions and locations with special priority.
Table 6.6. Alternate Functionality Priority
Alternate Functionality
Priority
1: PF7
High Speed
N
ot
R
ec
om
CMU_CLKI0
Location
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Rev. 1.4 | 154
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
6.6 Analog Port (APORT) Client Maps
The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs,
DACs, etc. The APORT consists of a set of shared buses, switches, and control logic needed to configurably implement the signal routing. Figure 6.4 APORT Connection Diagram on page 155 shows the APORT routing for this device family (note that available features
may vary by part number). A complete description of APORT functionality can be found in the Reference Manual.
ACMP0
PF2
PF3
NEG
1Y
2Y
3Y
4Y
NEXT1
NEXT0
POS
1X
2X
3X
4X
NEXT0
NEG
1Y
2Y
3Y
4Y
NEXT1
PF4
PF5
PF6
ADC0
AX
AY
BX
BY
PF7
POS
OPA0_P
1X
2X
3X
4X
NEG
OPA0_N
1Y
2Y
3Y
4Y
OPA0
es
ig
ns
D
DY
DX
CY
CX
OPA1_N
1Y
2Y
3Y
4Y
NEG
OPA0_P
VDAC0_OUT1ALT
OUT1ALT
ADC_EXTP
ADC_EXTN
PA0
OPA1_N
PD15
OUT
om
PA2
PA1
OPA1
VDAC0_OUT0ALT
OUT0ALT
PD14
PD13
ec
PD12
PD10
N
ot
PA4
PA3
POS
PD11
R
BUSAX, BUSBY, ...
VDAC0_OUT1ALT
OUT1ALT
OUT0
PA5
OUT1
AX, BY, …
VDAC0_OUT0ALT
OUT0ALT
OPA0_N
OPA1_P
APORTnX, APORTnY
PB11
VDAC0_OUT0ALT
VDAC0_OUT0ALT
nX, nY
PB13
PB12
1X
1Y
OUT0ALT
OUT1ALT
OUT
OUT0
OUT0ALT
OUT1
OUT2
OUT3
OUT4
NEXT0
PB14
NEG
OPA1_P
1X
2X
3X
4X
OUT1
OUT1ALT
OUT1
OUT2
OUT3
OUT4
NEXT1
PB15
ACMP1
IDAC0
m
en
de
d
EXTP
EXTN
N
ew
PF1
POS
fo
r
POS
PC6
PC7
PC8
PC9
PC10
PC11
PF0
1X
2X
3X
4X
NEXT1
NEXT0
1Y
2Y
3Y
4Y
NEXT1
NEXT0
1X
2X
3X
4X
NEXT1
NEXT0
Figure 6.4. APORT Connection Diagram
Client maps for each analog circuit using the APORT are shown in the following tables. The maps are organized by bus, and show the
peripheral's port connection, the shared bus, and the connection from specific bus channel numbers to GPIO pins.
In general, enumerations for the pin selection field in an analog peripheral's register can be determined by finding the desired pin connection in the table and then combining the value in the Port column (APORT__), and the channel identifier (CH__). For example, if pin
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Rev. 1.4 | 155
N
ot
PB14
PB11
PB11
PB13
PB15
PB15
PB13
BUSCY
BUSDX
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PD10
PD12
PD14
PA0
PA2
PA4
PD11
PD13
PD15
PA1
PA3
PA5
PD11
PD13
PD15
PA1
PA3
PA5
m
en
de
d
PB12
om
ec
R
BUSDY
PD10
PD12
PD14
PA0
PA2
PA4
fo
r
PB12
PB14
BUSCX
PC6
PC8
PC10
PC7
PC9
PC7
PC9
PC11
PF1
PF3
PF5
PF7
BUSAY
PC8
PC10
PF0
PF2
PF4
PF6
BUSAX
PC6
es
ig
ns
D
PC11
PF1
PF3
PF5
PF7
BUSBX
N
ew
PF0
PF2
PF4
PF6
BUSBY
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X Port
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
PF7 is available on port APORT2X as CH23, the register field enumeration to connect to PF7 would be APORT2XCH23. The shared
bus used by this connection is indicated in the Bus column.
Table 6.7. ACMP0 Bus and Pin Mapping
Rev. 1.4 | 156
N
ot
PB12
PB14
PB11
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PD10
PD12
PD14
PA0
PA2
PA4
PD11
PD13
PD15
PA1
PA3
PA5
PD11
PD13
PD15
PA1
PA3
PA5
PF0
PF2
PF4
PF6
BUSBY
PD10
PD12
PD14
PA0
PA2
PC6
PC8
PC10
N
ew
PA4
PB12
PB14
BUSCX
fo
r
PB11
PB13
PB15
PB15
PB13
BUSCY
BUSDX
m
en
de
d
om
ec
R
BUSDY
PC7
PC9
PC11
PF1
PF3
PF5
PF7
BUSAY
PC8
PC10
PF0
PF2
PF4
PF6
BUSAX
PC6
es
ig
ns
PC7
D
PC9
PC11
PF1
PF3
PF5
PF7
BUSBX
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X Port
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
Table 6.8. ACMP1 Bus and Pin Mapping
Rev. 1.4 | 157
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PD11
PD13
PD15
PA1
PA3
PA5
PB11
PB13
PB15
BUSCY
PD10
PD12
PD14
PA0
PA2
PA4
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
PB12
PB14
BUSDY
PB11
PD10
PD12
PD14
PA0
PA2
PA4
PD11
PD13
PD15
PA1
PA3
PA5
PD11
PD13
PD15
PA1
PA3
PA5
PD10
PD12
PD14
PA0
PA2
PC6
PC8
PC10
PF0
PF2
PF4
PF6
BUSBY
N
ew
PA4
PB12
PB14
BUSCX
fo
r
PB11
PB13
PB15
PB15
PB13
BUSCY
BUSDX
PC7
PC9
PC11
PF1
PF3
PF5
PF7
BUSAY
PC8
PC10
PF0
PF2
PF4
PF6
BUSAX
PC6
es
ig
ns
PC7
D
PC9
PC11
PF1
PF3
PF5
PF7
BUSBX
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X Port
m
en
de
d
om
CH29
CH30
CH31
Bus
ec
PB12
PB14
R
BUSCX
APORT1Y APORT1X Port
N
ot
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
Table 6.9. ADC0 Bus and Pin Mapping
Table 6.10. IDAC0 Bus and Pin Mapping
Rev. 1.4 | 158
N
ot
PB13
PB12
PB14
BUSCX
PF7
BUSBX
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PD11
PD13
PD15
PA1
PA3
PD10
PD12
PD14
PA0
PA2
PA4
PC7
PC9
PC11
PC6
PC8
PC10
fo
r
PF0
PF2
PF4
PF6
BUSAX
PD10
PD12
PD14
PA0
PA2
PA4
PB12
PB14
BUSDY
PD11
PD13
PC8
PC10
PF0
PF2
PF4
PF6
BUSBY
PC6
PC7
PC9
PC11
PF1
PF3
PF5
PF7
BUSAY
es
ig
ns
D
PD15
PA1
PA3
PA5
PB11
PB13
PB15
BUSCY
APORT4Y APORT3Y APORT2Y APORT1Y
N
ew
OPA0_P
PA5
PF1
PF3
PF5
m
en
de
d
PB11
om
ec
R
PB15
BUSDX
APORT4X APORT3X APORT2X APORT1X
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
Port
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
Table 6.11. VDAC0 / OPA Bus and Pin Mapping
OPA0_N
Rev. 1.4 | 159
N
ot
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PD10
PD12
PD14
PA0
PA2
PD11
PD13
PD15
PA1
PA3
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PC7
PC9
PC11
PF1
PF3
PF5
PF7
BUSAY
PB11
PB13
PB15
BUSDX
PB12
PB14
BUSCX
PD11
PD13
PD15
PA1
PA3
PA5
PD10
PD12
PD14
PA0
PA2
PA4
PC7
PC9
PC11
PA4
PB12
PB14
BUSDY
PC6
PC8
PC10
PD10
PD12
PD14
PD11
PD13
PD15
PA1
PC8
PC10
PF0
PF2
PF4
PF6
BUSBY
PC6
es
ig
ns
D
PA0
PA2
PA3
PA5
PB11
PB13
PB15
BUSCY
PC7
PC9
PC11
PF1
PF3
PF5
PF7
BUSAY
APORT4Y APORT3Y APORT2Y APORT1Y
N
ew
PF0
PF2
PF4
PF6
BUSAX
fo
r
PF1
PF3
PF5
PF7
BUSBX
m
en
de
d
om
ec
R
BUSBY
VDAC0_OUT0 / OPA0_OUT
PA5
PB11
PB13
PB15
BUSCY
APORT4X APORT3X APORT2X APORT1X
OPA1_P
PA4
PB12
PB14
BUSDY
APORT4Y APORT3Y APORT2Y APORT1Y
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
Port
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
OPA1_N
Rev. 1.4 | 160
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PD10
PD12
PD14
PA0
PD11
PD13
PD15
PA1
PA3
PA5
PB11
PB13
PB15
BUSCY
PC8
PC10
PF0
PF2
PF4
PF6
BUSBY
PC6
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PA2
PA4
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PB12
PB14
BUSDY
PC7
PC9
PC11
PF1
PF3
PF5
PF7
BUSAY
APORT4Y APORT3Y APORT2Y APORT1Y
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
Bus
Port
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Pin Definitions
VDAC0_OUT1 / OPA1_OUT
Rev. 1.4 | 161
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
QFN48 Package Specifications
7. QFN48 Package Specifications
Figure 7.1. QFN48 Package Drawing
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7.1 QFN48 Package Dimensions
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QFN48 Package Specifications
Table 7.1. QFN48 Package Dimensions
Min
Typ
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
0.20 REF
b
0.18
0.25
D
6.90
7.00
E
6.90
7.00
D2
4.60
4.70
E2
4.60
4.70
0.50 BSC
L
0.30
K
0.20
R
0.09
7.10
7.10
4.80
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0.30
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A3
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Dimension
aaa
4.80
0.40
0.50
—
—
—
0.14
0.15
0.10
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bbb
ccc
0.10
0.05
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fff
0.08
0.10
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Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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QFN48 Package Specifications
Figure 7.2. QFN48 PCB Land Pattern Drawing
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7.2 QFN48 PCB Land Pattern
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
QFN48 Package Specifications
Table 7.2. QFN48 PCB Land Pattern Dimensions
Typ
S1
6.01
S
6.01
L1
4.70
W1
4.70
e
0.50
W
0.26
L
0.86
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Dimension
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Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 4x4 array of 0.75 mm square openings on a 1.00 mm pitch can be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
QFN48 Package Specifications
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EFR32
PPPPPPPPPP
YYWWTTTTTT
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7.3 QFN48 Package Marking
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Figure 7.3. QFN48 Package Marking
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The package marking consists of:
• PPPPPPPPP – The part number designation.
1. Family Code (B | M | F)
2. G (Gecko)
3. Series (1, 2,...)
4. Device Configuration (1, 2,...)
5. Performance Grade (P | B | V)
6. Feature Code (1, 2,...)
7. TRX Code (3 = TXRX | 2 = RX | 1 = TX)
8. Band (1 = Sub-GHz | 2 = 2.4 GHz | 3 = Dual-band)
9. Flash (J = 1024K | H = 512K | G = 256K | F = 128K | E = 64K | D = 32K)
10. Temperature Grade (G = -40 to 85 | I = -40 to 125)
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
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QFN32 Package Specifications
8. QFN32 Package Specifications
Figure 8.1. QFN32 Package Drawing
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8.1 QFN32 Package Dimensions
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
QFN32 Package Specifications
Table 8.1. QFN32 Package Dimensions
Min
Typ
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
0.20 REF
b
0.18
0.25
D/E
4.90
5.00
D2/E2
3.40
3.50
E
0.50 BSC
0.30
0.40
K
0.20
—
R
0.09
5.10
3.60
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L
0.30
D
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Dimension
—
aaa
0.50
—
0.14
0.15
bbb
0.10
ccc
0.10
0.05
fo
r
ddd
eee
0.08
0.10
m
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fff
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Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
silabs.com | Building a more connected world.
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
QFN32 Package Specifications
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8.2 QFN32 PCB Land Pattern
Figure 8.2. QFN32 PCB Land Pattern Drawing
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Table 8.2. QFN32 PCB Land Pattern Dimensions
Dimension
S1
S
L1
W1
om
e
W
4.01
4.01
3.50
3.50
0.50
0.26
0.86
ec
L
Typ
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Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 3x3 array of 0.85 mm square openings on a 1.00 mm pitch can be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.4 | 169
EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
QFN32 Package Specifications
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EFR32
PPPPPPPPPP
YYWWTTTTTT
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8.3 QFN32 Package Marking
Figure 8.3. QFN32 Package Marking
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The package marking consists of:
• PPPPPPPPP – The part number designation.
1. Family Code (B | M | F)
2. G (Gecko)
3. Series (1, 2,...)
4. Device Configuration (1, 2,...)
5. Performance Grade (P | B | V)
6. Feature Code (1, 2,...)
7. TRX Code (3 = TXRX | 2 = RX | 1 = TX)
8. Band (1 = Sub-GHz | 2 = 2.4 GHz | 3 = Dual-band)
9. Flash (J = 1024K | H = 512K | G = 256K | F = 128K | E = 64K | D = 32K)
10. Temperature Grade (G = -40 to 85 | I = -40 to 125)
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Revision History
9. Revision History
Revision 1.4
December, 2020
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• Removed EFR32MG14P731F256GM48-B from Table 2.1 Ordering Information on page 3.
• Changed maximum available number of GPIO from 32 to 31 throughout document due to the removal of OPN
EFR32MG14P731F256GM48-B.
• Removed section 6.3 QFN48 Sub-GHz Device Pinout.
• Removed PD9 from all pin functionality and pin mapping tables throughout document.
Revision 1.3
In 1. Feature List, removed Wake on Radio reference.
In the front page block diagram, updated the lowest energy mode for LETIMER.
Updated 3.6.4 Low Energy Timer (LETIMER) lowest energy mode.
In 4.1.2.1 General Operating Conditions for fCORE :
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September, 2020
• Added conditions for all usable wait state settings
• Corrected maximum specification from 20 MHz to 7 MHz for test condition VSCALE0, MODE = WS0
• In, 4.1.14 General-Purpose I/O (GPIO), added footnotes to VIL, VIH (footnote 1), and RPUD (footnote 2).
• In 4.1.15 Voltage Monitor (VMON), updated test conditions for IVMON.
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• In 4.1.18 Digital to Analog Converter (VDAC), updated test conditions for IDAC, 200 Hz refresh rate.
• SPUROOB_FCC_20
• SPURHARM_FCC_14
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• Updated External PA supply connection conditions for SPURHARM_ETSI and SPUROOB_ETSI in section 4.1.10.3 Sub-GHz RF Transmitter characteristics for 868 MHz Band.
• In 4.1.10.1 Sub-GHz RF Transmitter characteristics for 915 MHz Band:
• Corrected FCC reference for non-restricted bands in:
• SPURHARM_FCC_20
• SPUROOB_FCC_14
• Updated typical and maximum specifications for restricted bands (30-88 MHz) in:
• SPUROOB_FCC_20
• SPUROOB_FCC_14
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• Added footnote to PSD.
• In 4.1.10.2 Sub-GHz RF Receiver Characteristics for 915 MHz Band, updated typical and maximum specifications for SPURRX_ARIB,
930-1000 MHz, RBW=100 kHz.
• In 7.3 QFN48 Package Marking, updated feature code.
• In 8.3 QFN32 Package Marking, updated feature code.
• Minor typographical, style, and phrasing changes throughout document.
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• Removed TRNG.
• “PAVDD” references in Sub-GHz specification tables clarified to refer to “External PA Supply”. The PAVDD pin is for the 2.4 GHz
radio.
• GPIO Functionality table re-sorted to list pins alphabetically by GPIO Name column.
• Added EFR32MG14P731F256GM48-B part number and associated pinout information.
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EFR32MG14 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Revision History
Revision 1.1
March, 2018
Removed PLFRCO.
Removed 2 Mbps sensitivity plot from Figure 4.11 2.4 GHz RF Receiver Sensitivity on page 110.
Figure 6.4 APORT Connection Diagram on page 155: Corrected OPA output connections to route through "Y" buses.
Removed "Confidential" watermark.
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•
Revision 1.0
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October, 2017
• Front Page: Fixed PLFRCO EM mode color.
• Front Page and Feature List: Updated highlighted features for consistency across product line.
• Multiprotocol support added to Ordering Information descriptions.
• Ordering Code Key Figure: Removed L (BGA) from package designation.
• System Overview: Memory maps updated with LE peripherals and new formatting.
• Absolute Maximum Ratings Table: Added footnote to clarify VDIGPIN specification for 5V tolerant GPIO.
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• General Operating Conditions Table: Added footnote for additional information on peak current during voltage scaling operations.
• Updated all specification table values, conditions, and footnotes according to latest characterization data, spec standards, and production test limits.
• Sub-GHz RF Receiver Characteristics for 868 MHz Band Table: Removed BPSK DSSS signal specifications from table and footnotes.
• 2.4 GHz RF Transmitter Output Power Figure: Extended temperature range to 125 C.
• 2.4 GHz RF Receiver Sensitivity Figure: Updated with latest characterization data and added 125 C operational plots.
• Updated pinout table formatting.
• Removed 2 Mbps BLE RX and TX specification tables and associated information.
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Revision 0.1
June 21, 2017
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Initial release.
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Rev. 1.4 | 172
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Simplicity Studio
IoT Portfolio
www.silabs.com/IoT
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One-click access to MCU and wireless
tools, documentation, software, source
code libraries & more. Available for
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www.silabs.com/community
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Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and “Typical”
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information.
Without prior notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons. Such changes will not alter the specifications or
the performance of the product. Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly
grant any license to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any FDA Class III devices, applications for which FDA
premarket approval is required, or Life Support Systems without the specific written consent of Silicon Labs. A “Life Support System” is any product or system intended to support or
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