ESD7351, SZESD7351
Series
ESD Protection Diode
The ESD7351 Series is designed to protect voltage sensitive
components that require ultra−low capacitance from ESD and
transient voltage events. Excellent clamping capability, low
capacitance, low leakage, and fast response time, make these parts
ideal for ESD protection on designs where board space is at a
premium. Because of its low capacitance, it is suited for use in high
frequency designs such as USB 2.0 high speed and antenna line
applications.
•
•
•
•
•
•
•
•
•
Low Capacitance (0.6 pF Max, I/O to GND)
Low Clamping Voltage
Stand−off Voltage: 3.3 V
Low Leakage
Response Time is < 1 ns
Low Dynamic Resistance < 1 W
IEC61000−4−2 Level 4 ESD Protection
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MARKING
DIAGRAMS
2
1
2
X, XX
M
1
Cathode
Value
Unit
±20
±20
kV
°PD°
150
mW
TJ, Tstg
−55 to +150
°C
TL
260
°C
Contact
Air
Total Power Dissipation on FR−5 Board
(Note 1) @ TA = 25°C
Junction and Storage Temperature Range
Lead Solder Temperature − Maximum
(10 Second Duration)
AE
1
2
AD M
= Specific Device Code
= Date Code
PIN CONFIGURATION
AND SCHEMATIC
MAXIMUM RATINGS
IEC 61000−4−2 (ESD)
AF
M
SOD−923
CASE 514AB
• RF Signal ESD Protection
• RF Switching, PA, and Antenna ESD Protection
• Near Field Communications
Symbol
SOD−523
CASE 502
1
Typical Applications
Rating
SOD−323
CASE 477
M
Features
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2
Anode
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
See Application Note AND8308/D for further description of survivability specs.
© Semiconductor Components Industries, LLC, 2014
November, 2018 − Rev. 5
1
Publication Order Number:
ESD7351/D
ESD7351, SZESD7351 Series
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
IF
Parameter
Symbol
IPP
Maximum Reverse Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
IR
VBR
IT
VC VBR VRWM
Working Peak Reverse Voltage
V
IR VF
IT
Maximum Reverse Leakage Current @ VRWM
Breakdown Voltage @ IT
Test Current
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
IPP
Uni−Directional
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage (Note 2)
Symbol
Conditions
Min
Typ
VRWM
VBR
IT = 1 mA
Max
Unit
3.3
V
50
nA
5.0
V
Reverse Leakage Current
IR
VRWM = 3.3 V
< 1.0
Clamping Voltage (Note 3)
VC
IPP = 1 A
8.0
V
Clamping Voltage (Note 3)
VC
IPP = 3 A
10
V
Junction Capacitance
CJ
VR = 0 V, f = 1 MHz
VR = 0 V, f < 1 GHz
0.43
0.43
0.6
0.6
pF
Dynamic Resistance
RDYN
TLP Pulse
0.35
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Breakdown voltage is tested from pin 1 to 2.
3. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−5 waveform.
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2
ESD7351, SZESD7351 Series
1.0
1.E−03
1.E−04
0.8
CAPACITANCE (pF)
1.E−05
I (A)
1.E−06
1.E−07
1.E−08
1.E−09
1.E−10
0.6
0.4
0.2
1.E−11
1.E−12
0
1
2
3
4
5
6
7
0
0
8
1
2.5
VBias (V)
Figure 2. CV Characteristics
3
3.5
2.0
1.8
1.6
CAPACITANCE (pF)
−2
−4
TBD
−6
−8
−10
1.4
1.2
1.0
0.8
0.6
0.4
−12
0.2
−14
1.E+08
1.E+09
0.0
0.5
1.E+10
1.5
2.5
FREQUENCY (Hz)
3.5
4.5
5.5
6.5
7.5
8.5
9.5
FREQUENCY (GHz)
Figure 3. RF Insertion Loss
Figure 4. Capacitance over Frequency
8
16
−16
14
8
6
10
−12
6
−10
4
8
6
2
4
2
−8
4
−6
−4
2
−2
0
NOTE:
2
4
6
8
10
12
14
16
18
0
20
0
0
2
4
6
8
10
12
14
16
VC, VOLTAGE (V)
VC, VOLTAGE (V)
Figure 5. Positive TLP I−V Curve
Figure 6. Negative TLP I−V Curve
18
0
20
TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
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3
EQUIVALENT VIEC (kV)
EQUIVALENT VIEC (kV)
TLP CURRENT (A)
−14
12
TLP CURRENT (A)
2
V (V)
0
0
1.5
Figure 1. IV Characteristics
2
dB
0.5
ESD7351, SZESD7351 Series
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 7. IEC61000−4−2 Spec
Device
ESD Gun
Under
Oscilloscope
Test
50 W
50 W
Cable
Figure 8. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 9. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 10 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
L
S Attenuator
÷
50 W Coax
Cable
10 MW
IM
50 W Coax
Cable
VM
DUT
VC
Oscilloscope
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
Figure 9. Simplified Schematic of a Typical TLP
System
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4
ESD7351, SZESD7351 Series
Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
ORDERING INFORMATION
Package
Shipping†
ESD7351HT1G,
SZESD7351HT1G*
SOD−323
(Pb−Free)
3000 / Tape & Reel
ESD7351XV2T1G,
SZESD7351XV2T1G*
SOD−523
(Pb−Free)
3000 / Tape & Reel
ESD7351XV2T5G,
SZESD7351XV2T5G*
SOD−523
(Pb−Free)
8000 / Tape & Reel
ESD7351P2T5G,
SZESD7351P2T5G*
SOD−923
(Pb−Free)
8000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
2
1
STYLE 1
SOD−323
CASE 477−02
ISSUE H
2
SCALE 4:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. LEAD THICKNESS SPECIFIED PER L/F DRAWING
WITH SOLDER PLATING.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
5. DIMENSION L IS MEASURED FROM END OF RADIUS.
HE
D
b
1
2
E
A3
A
C
NOTE 3
DATE 13 MAR 2007
1
STYLE 2
L
A1
NOTE 5
MILLIMETERS
DIM MIN
NOM MAX
A
0.80
0.90
1.00
A1 0.00
0.05
0.10
A3
0.15 REF
b
0.25
0.32
0.4
C 0.089
0.12 0.177
D
1.60
1.70
1.80
E
1.15
1.25
1.35
L
0.08
HE
2.30
2.50
2.70
INCHES
NOM MAX
0.035 0.040
0.002 0.004
0.006 REF
0.010 0.012 0.016
0.003 0.005 0.007
0.062 0.066 0.070
0.045 0.049 0.053
0.003
0.090 0.098 0.105
MIN
0.031
0.000
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
XX M
0.63
0.025
STYLE 1
0.83
0.033
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
2.85
0.112
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DESCRIPTION:
98ASB17533C
SOD−323
STYLE 2
XX = Specific Device Code
M = Date Code
1.60
0.063
DOCUMENT NUMBER:
XX M
STYLE 1:
PIN 1. CATHODE (POLARITY BAND)
2. ANODE
STYLE 2:
NO POLARITY
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
2
2
1
1
STYLE 1
STYLE 2
SOD−523
CASE 502−01
ISSUE E
SCALE 4:1
−X−
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.
−Y−
E
M
2
X Y
DIM
A
b
c
D
E
HE
L
L2
TOP VIEW
A
c
HE
MILLIMETERS
MIN
NOM
MAX
0.50
0.60
0.70
0.25
0.30
0.35
0.07
0.14
0.20
1.10
1.20
1.30
0.70
0.80
0.90
1.50
1.60
1.70
0.30 REF
0.15
0.20
0.25
GENERIC
MARKING DIAGRAM*
SIDE VIEW
2X
XX
L
1
XX
2
1
STYLE 1
2X
XX
M
L2
RECOMMENDED
SOLDERING FOOTPRINT*
PACKAGE
OUTLINE
= Specific Device Code
Date Code
STYLE 1:
PIN 1. CATHODE (POLARITY BAND)
2. ANODE
1.80
0.48
2
STYLE 2
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
BOTTOM VIEW
2X
M
b
0.08
1
M
2X
DATE 28 SEP 2010
2X
STYLE 2:
NO POLARITY
0.40
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON11524D
SOD−523
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOD−923
CASE 514AB
ISSUE D
STYLE 1
DATE 03 SEP 2020
STYLE 2
SCALE 8:1
D
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
5. DIMENSION L WILL NOT EXCEED 0.30mm.
−Y−
E
1
2X b
0.08 X Y
2
TOP VIEW
c
HE
SIDE VIEW
2X
2X
BOTTOM VIEW
XM
XM
STYLE 1
STYLE 2
X
M
SOLDERING FOOTPRINT*
= Specific Device Code
= Date Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
1.20
2X
INCHES
MIN
NOM MAX
0.013 0.015 0.016
0.006 0.008 0.010
0.003 0.005 0.007
0.030 0.031 0.033
0.022 0.024 0.026
0.037 0.039 0.041
0.007 REF
0.002 0.004 0.006
GENERIC
MARKING DIAGRAM*
L
L2
2X
0.36
MILLIMETERS
MIN
NOM MAX
0.34
0.37
0.40
0.15
0.20
0.25
0.07
0.12
0.17
0.75
0.80
0.85
0.55
0.60
0.65
0.95
1.00
1.05
0.19 REF
0.05
0.10
0.15
DIM
A
b
c
D
E
HE
L
L2
A
0.25
STYLE 1:
PIN 1. CATHODE (POLARITY BAND)
2. ANODE
PACKAGE
OUTLINE
STYLE 2:
NO POLARITY
DIMENSIONS: MILLIMETERS
See Application Note AND8455/D for more mounting details
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON23284D
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SOD−923, 1.0X0.6X0.37, MAX HEIGHT 0.40
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
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