H-Bridge in APM16 Series
for LLC and Phase-shifted
DC-DC Converter
FAM65HR51DS1
Features
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• SIP or DIP H−Bridge Power Module for On−board Charger (OBC) in
•
•
•
•
•
•
EV or PHEV
5 kV/1 sec Electrically Isolated Substrate for Easy Assembly
Creepage and Clearance per IEC60664−1, IEC 60950−1
Compact Design for Low Total Module Resistance
Module Serialization for Full Traceability
Lead Free, RoHS and UL94V−0 Compliant
Automotive Qualified per AEC Q101 and AQG324 Guidelines
APMCA−A16
16 LEAD
CASE MODGF
Applications
• DC−DC Converter for On−board Charger in EV or PHEV
Benefits
• Enable Design of Small, Efficient and Reliable System for Reduced
•
Vehicle Fuel Consumption and CO2 Emission
Simplified Assembly, Optimized Layout, High Level of Integration,
and Improved Thermal Performance
MARKING DIAGRAM
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= Specific Device Code
= Lot ID
= Assembly & Test Location
= Year
= Work Week
= Serial Number
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2018
May, 2021 − Rev. 4
1
Publication Order Number:
FAM65HR51DS1/D
FAM65HR51DS1
ORDERING INFORMATION
Part Number
Package
Lead Forming
Snubber
Capacitor Inside
DBC
Material
FAM65HR51DS1
APM16−CAA
Y−Shape
Yes
Al2O3
Pb−Free and
Operating
RoHS Compliant Temperature (TA)
Yes
Pin Configuration and Description
Figure 1. Internal Block Diagram
Table 1. PIN DESCRIPTION
Pin Number
Pin Name
Pin Description
1, 2
AC1
Phase 1 Leg of the H−Bridge
3
Q1 Sense
Source Sense of Q1
4
Q1 Gate
Gate Terminal of Q1
5, 6
B+
Positive Battery Terminal
7, 8
B−
Negative Battery Terminal
9
Q2 Sense
Source Sense of Q2
10
Q2 Gate
Gate Terminal of Q2
11
Q4 Sense
Source Sense of Q4
12
Q4 Gate
Gate Terminal of Q4
13
Q3 Sense
Source Sense of Q3
14
Q3 Gate
Gate Terminal of Q3
15, 16
AC2
Phase 2 Leg of the H−Bridge
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2
−40°C ~ 125°C
Packing
Method
Tube
FAM65HR51DS1
INTERNAL EQUIVALENT CIRCUIT
Figure 2. Internal Block Diagram
Table 2. ABSOLUTE MAXIMUM RATINGS (TJ = 25°C, Unless Otherwise Specified)
Max
Unit
VDS (Q1~Q4)
Drain−to−Source Voltage
Parameter
650
V
VGS (Q1~Q4)
Gate−to−Source Voltage
±20
V
Drain Current Continuous (TC = 25°C, VGS = 10 V) (Note 1)
33
A
Drain Current Continuous (TC = 100°C, VGS = 10 V) (Note 1)
21
A
Single Pulse Avalanche Energy (Note 2)
623
mJ
Symbol
ID (Q1~Q4)
EAS (Q1~Q4)
PD
Power Dissipation (Note 1)
135
W
TJ
Maximum Junction Temperature
−55 to +150
°C
TC
Maximum Case Temperature
−40 to +125
°C
Storage Temperature
−40 to +125
°C
TSTG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum continuous current and power, without switching losses, to reach TJ = 150°C respectively at TC = 25°C and TC = 100°C; defined
by design based on MOSFET RDS(ON) and RqJC and not subject to production test
2. Starting TJ = 25°C, IAS = 6.5 A, RG = 25 W
Table 3. COMPONENTS (Note 3)
Device
Capacitor (Snubber)
AEC Q200 qualified
Parameter
Capacitance
Condition
Min
Typ
Max
Unit
TJ = 25°C
135
150
165
nF
−
630
−
V
Rated Voltage
3. These values are obtained from the specification provided by the manufacturer.
DBC Substrate
Compliance to RoHS Directives
0.63 mm Al2O3 alumina with 0.3 mm copper on both sides.
DBC substrate is NOT nickel plated.
The power module is 100% lead free and RoHS compliant
2000/53/C directive.
Lead Frame
Solder
OFC copper alloy, 0.50 mm thick. Plated with 8 um to
25.4 um thick Matte Tin
Solder used is a lead free SnAgCu alloy.
Solder presents high risk to melt at temperature beyond
210°C. Base of the leads, at the interface with the package
body, should not be exposed to more than 200°C during
mounting on the PCB or during welding to prevent the
re−melting of the solder joints.
Flammability Information
All materials present in the power module meet UL
flammability rating class 94V−0.
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3
FAM65HR51DS1
Table 4. ELECTRICAL SPECIFICATIONS (TJ = 25°C, Unless Otherwise Specified)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
BVDSS
Drain−to−Source Breakdown Voltage
ID = 1 mA, VGS = 0 V
650
−
−
V
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 3.3 mA
3.0
−
5.0
V
RDS(ON)
Q1 – Q4 MOSFET On Resistance
VGS = 10 V, ID = 20 A
−
44
51
mW
RDS(ON)
Q1 – Q4 MOSFET On Resistance
VGS = 10 V, ID = 20 A, TJ = 125°C (Note 4)
−
79
−
mW
VDS = 20 V, ID = 20 A (Note 4)
−
30
−
S
gFS
Forward Transconductance
IGSS
Gate−to−Source Leakage Current
VGS = ±20 V, VDS = 0 V
−100
−
+100
nA
IDSS
Drain−to−Source Leakage Current
VDS = 650 V, VGS = 0 V
−
−
10
mA
VDS = 400 V
VGS = 0 V
f = 1 MHz
−
4864
−
pF
−
109
−
pF
−
16
−
pF
VDS = 0 to 520 V
VGS = 0 V
−
652
−
pF
f = 1 MHz
−
2
−
W
VDS = 380 V
ID = 20 A
VGS = 0 to 10 V
−
123
−
nC
−
37.5
−
nC
−
49
−
nC
VDS = 400 V
ID = 20 A
VGS = 10 V
RG = 4.7 W
−
87
−
ns
−
47
−
ns
−
43
−
ns
Turn−off Time
−
148
−
ns
Turn−off Delay Time
−
118
−
ns
Turn−off Fall Time
−
29
−
ns
ISD = 20 A, VGS = 0 V
−
0.95
−
V
VDS = 520 V, ID = 20 A,
dI/dt = 100 A/ms (Note 4)
−
133
−
ns
−
669
−
nC
DYNAMIC CHARACTERISTICS (Note 4)
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Coss(eff)
Effective Output Capacitance
Rg
Qg(tot)
Gate Resistance
Total Gate Charge
Qgs
Gate−to−Source Gate Charge
Qgd
Gate−to−Drain “Miller” Charge
SWITCHING CHARACTERISTICS (Note 4)
ton
Turn−on Time
td(on)
Turn−on Delay Time
tr
Turn−on Rise Time
toff
td(off)
tf
BODY DIODE CHARACTERISTICS
VSD
Source−to−Drain Diode Voltage
Trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Defined by design, not subject to production test
Table 5. THERMAL RESISTANCE
Parameters
Min
Typ
Max
Unit
RθJC (per chip)
Q1~Q4 Thermal Resistance Junction−to−Case (Note 5)
−
0.66
0.92
°C/W
RθJS (per chip)
Q1~Q4 Thermal Resistance Junction−to−Sink (Note 6)
−
1.2
−
°C/W
5. Test method compliant with MIL STD 883−1012.1, from case temperature under the chip to case temperature measured below the package
at the chip center, Cosmetic oxidation and discoloration on the DBC surface allowed
6. Defined by thermal simulation assuming the module is mounted on a 5 mm Al−360 die casting material with 30 um of 1.8 W/mK thermal
interface material
Table 6. ISOLATION (Isolation resistance at tested voltage from the base plate to control pins or power terminals.)
Test
Test Conditions
Isolation Resistance
Unit
Leakage @ Isolation Voltage (Hi−Pot)
VAC = 5 kV, 60 Hz
100M <
W
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4
FAM65HR51DS1
PARAMETER DEFINITIONS
Reference to Table 4: Parameter of Electrical Specifications
BVDSS
Q1 – Q4 MOSFET Drain−to−Source Breakdown Voltage
The maximum drain−to−source voltage the MOSFET can endure without the avalanche breakdown of the body− drain
P−N junction in off state.
The measurement conditions are to be found in Table 4.
The typ. Temperature behavior is described in Figure 13
VGS(th)
Q1 – Q4 MOSFET Gate to Source Threshold Voltage
The gate−to−source voltage measurement is triggered by a threshold ID current given in conditions at Table 5.
The typ. Temperature behavior can be found in Figure 12
RDS(ON)
Q1 – Q4 MOSFET On Resistance
RDS(on) is the total resistance between the source and the drain during the on state.
The measurement conditions are to be found in Table 4.
The typ behavior can be found in Figure 10 and Figure 11 as well as Figure 17
gFS
Q1 – Q4 MOSFET Forward Transconductance
Transconductance is the gain in the MOSFET, expressed in the Equation below.
It describes the change in drain current by the change in the gate−source bias voltage: gfs = [ DIDS / DVGS ]VDS
IGSS
Q1 – Q4 MOSFET Gate−to−Source Leakage Current
The current flowing from Gate to Source at the maximum allowed VGS
The measurement conditions are described in the Table 4.
IDSS
Q1 – Q4 MOSFET Drain−to−Source Leakage Current
Drain – Source current is measured in off state while providing the maximum allowed drain−to-source voltage and the
gate is shorted to the source.
IDSS has a positive temperature coefficient.
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5
FAM65HR51DS1
Figure 3. Timing Measurement Variable Definition
Table 7. PARAMETER OF SWITCHING CHARACTERISTICS
Turn−On Delay (td(on))
This is the time needed to charge the input capacitance, Ciss, before the load current ID starts flowing.
The measurement conditions are described in the Table 4.
For signal definition please check Figure 3 above.
Rise Time (tr)
The rise time is the time to discharge output capacitance, Coss.
After that time the MOSFET conducts the given load current ID.
The measurement conditions are described in the Table 4.
For signal definition please check Figure 3 above.
Turn−On Time (ton)
Is the sum of turn−on−delay and rise time
Turn−Off Delay (td(off))
td(off) is the time to discharge Ciss after the MOSFET is turned off.
During this time the load current ID is still flowing
The measurement conditions are described in the Table 4.
For signal definition please check Figure 3 above.
Fall Time (tf)
The fall time, tf, is the time to charge the output capacitance, Coss.
During this time the load current drops down and the voltage VDS rises accordingly.
The measurement conditions are described in the Table 4.
For signal definition please check Figure 3 above.
Turn−Off Time (toff)
Is the sum of turn−off−delay and fall time
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6
FAM65HR51DS1
TYPICAL CHARACTERISTICS
40
0.6
0.4
0.2
RqJC = 0.92°C/W
0
25
50
75
100
125
20
15
10
RqJC = 0.92°C/W
25
50
75
100
125
150
175
TC, CASE TEMPERATURE (°C)
TC, CASE TEMPERATURE (°C)
Figure 4. Normalized Power Dissipation vs.
Case
Figure 5. Maximum Continuous ID vs. Case
Temperature
VDS = 20 V
40
TJ = 25°C
30
20
TJ = 150°C
10
TJ = −55°C
3
4
5
6
7
8
VGS = 0 V
100
10
TJ = 150°C
1
TJ = 25°C
0.1
0.01
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VGS, GATE−TO−SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 6. Transfer Characteristics
Figure 7. Forward Diode
100
80
VGS = 15 V
70
10 V
90
8.0 V
60
50
7.0 V
40
30
6.0 V
20
5.5 V
10
0
25
0
150
50
0
30
5
IS, REVERSE DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
60
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
0.8
0
VGS = 10 V
35
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
5.0 V
0
1
2
3
4
5
6
7
8
9
10
80
VGS = 15 V
70
10 V
60
8.0 V
50
7.0 V
40
30
6.0 V
20
5.5 V
10
0
5.0 V
0
10
20
30
40
50
60
70
80
90 100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 8. On Region Characteristics (255C)
Figure 9. On Region Characteristics (1505C)
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FAM65HR51DS1
TYPICAL CHARACTERISTICS
TJ = 150°C
100
TJ = 25°C
50
5.5
6.5
7.5
8.5
1.5
1.0
0.5
0
−75 −50 −25
0
25
50
75
100 125 150 175
VGS, GATE−TO−SOURCE VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 10. On−Resistance vs. Gate−to−Source
Voltage
Figure 11. RDS(norm) vs. Junction Temperature
ID = 3.3 mA
1.0
0.8
0.6
−75 −50 −25
0
25
50
75
100 125 150 175
1.2
ID = 10 A
1.1
1.0
0.9
0.8
−75 −50 −25
0
25
50
75
100 125 150 175
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 12. Normalized Gate Threshold Voltage
vs. Temperature
Figure 13. Normalized Breakdown Voltage vs.
Temperature
100K
30
25
CAPACITANCE (pF)
10K
20
Eoss (mJ)
ID = 20 A
VGS = 10 V
2.0
9.5
1.2
15
10
CISS
1K
COSS
100
CRSS
VGS = 0 V
f = 1 MHz
10
5
0
2.5
RDS(ON), NORMALIZED DRAIN−TO−
SOURCE ON−RESISTANCE
150
0
NORMALIZED GATE THRESHOLD VOLTAGE
ID = 20 A
NORMALIZED DRAIN−TO−SOURCE
BREAKDOWN VOLTAGE
RDS(ON), ON−RESISTANCE (mW)
200
0
100
200
300
400
500
600
1
700
0.1
1
10
100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 14. Eoss vs. Drain−to−Source Voltage
Figure 15. Capacitance Variation
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8
1000
FAM65HR51DS1
0.060
10
VDD = 130 V
8
TC = 25°C
RDS(on), DRAIN−TO−SOURCE ON
RESISTANCE (W)
VGS, GATE−TO−SOURCE VOLTAGE (V)
TYPICAL CHARACTERISTICS
0.055
VDD = 400 V
6
VGS = 10 V
0.050
4
0.045
2
0
VGS = 20 V
0
40
80
120
0.040
160
0
20
40
ID, DRAIN CURRENT (A)
Figure 16. Gate Charge Characteristics
Figure 17. ON−Resistance Variation with Drain
Current and Gate Voltage
For temperatures above 25°C
derate peak current as follows:
100
ZqJA, NORMALIZED THERMAL IMPEDANCE (°C/W)
IDM, PEAK CURRENT (A)
ID, DRAIN CURRENT (A)
VGS = 10 V
10
TC = 25°C
Single Pulse
RqJC = 0.92°C/W
RDS(on) Limit
Thermal Limit
Package Limit
1
10
1 ms
10 ms
100 ms
1s
100
I + I 25
1000
100 ms
0.1
80
QG, GATE CHARGE (nC)
10,000
1
60
150 * T C
125
TC = 25°C
100
Limited IDM 206 A
Single Pulse
10
0.000001 0.00001 0.0001
1000
Ǹ
NOTES:
RqJC = 0.92°C/W
Duty Cycle, D = t1/t2
Peak TJ = PDM x ZqJC(t) + TC
0.001
0.01
0.1
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
t, PULSE WIDTH (sec)
Figure 18. Safe Operating Area
Figure 19. Peak Current Capability
1
10
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
0.01 0.01
Single Pulse
0.001
0.00001
0.0001
0.001
0.1
0.01
t, RECTANGULAR PULSE DURATION (sec)
Figure 20. Transient Thermal Impedance
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9
1
10
100
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
APMCA−A16 / 16LD, AUTOMOTIVE MODULE
CASE MODGF
ISSUE C
GENERIC
MARKING DIAGRAM*
XXXXXXXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
DOCUMENT NUMBER:
DESCRIPTION:
XXXX
ZZZ
AT
Y
W
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98AON94732G
= Specific Device Code
= Lot ID
= Assembly & Test Location
= Year
= Work Week
= Serial Number
DATE 03 NOV 2021
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
APMCA−A16 / 16LD, AUTOMOTIVE MODULE
PAGE 1 OF 1
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