FAN65004B

Synchronous PWM Buck Regulator, Voltage Mode, High Performance, 65 V, 6 A FAN65004B Description www.onsemi.com FAN65004B is a wide VIN highly efficient synchronous buck regulator, with integrated high side and low side power MOSFETs. The device incorporates a fixed frequency voltage mode PWM controller supporting a wide voltage range from 4.5 V to 65 V and can handle continuous currents up to 6 A. FAN65004B includes a 0.67% accurate reference voltage to achieve tight regulation. The switching frequency can be programmed from 100 kHz to 1 MHz. To improve efficiency at light load condition, the device can be set to discontinuous conduction mode with pulse skipping operation. FAN65004B has dual LDOs to minimize power loss and integrated current sense circuit that provides cycle−by−cycle current limiting. This single phase buck regulator offers complete protection features including Over current protection, Thermal shutdown, Under−voltage lockout, Over voltage protection, Under voltage protection and Short−circuit protection. FAN65004B uses ON Semiconductor’s high performance PowerTrench® MOSFETs that reduces ringing in switching applications. FAN65004B integrates the controller, driver, and power MOSFETs into a thermally enhanced, compact 6 x 6 mm PQFN package. With an integrated approach, the complete DC/DC converter is optimized from the controller and driver to MOSFET switching performance, delivering a high power density solution. PQFN35 6x6 CASE 483BE MARKING DIAGRAM ZXYYKK FAN 65004B 1 Z = Assembly Location X = Year / Lead Free YY = Week KK = Lot FAN65004B = Specific Device Code Features • Wide Input Voltage Range: 4.5 V to 65 V • Continuous Output Current: 6 A • Fixed Frequency Voltage Mode PWM Control with Input Voltage ORDERING INFORMATION See detailed ordering and shipping information on page 23 of this data sheet. Feed−forward • 0.6 V Reference Voltage with 0.67% Accuracy • Adjustable Switching Frequency: 100 kHz to 1 MHz • Dual LDOs for Single Supply Operation and to Reduce • • • • • • • High Performance Low Profile 6 mm x 6 mm PQFN Package • This Device is Pb−Free and RoHS Compliant Power Loss Selectable CCM PWM Mode or PFM Mode for Light Loads External Compensation for Wide Operation Range Adjustable Soft−Start & Pre−Bias Startup Enable Function with Adjustable Input Voltage Under−Voltage−Lock−Out (UVLO) Power Good Indicator Over Current Protection, Thermal Shutdown, Over Voltage Protection, Under Voltage Protection and Short−circuit Protection © Semiconductor Components Industries, LLC, 2017 November, 2019 − Rev. 2 Applications • High Voltage POL Module • Telecommunications: Base Station Power Supplies • Networking: Computing, Battery Management Systems, USB−PD • Industrial Equipment: Automation, Power Tools, Slot Machines 1 Publication Order Number: FAN65004B/D FAN65004B EN / UVLO VIN C1 4.5 V~65 V VIN PWM Controller with Driver PVCC R4 VCC MODE C6 C3 VCC SYNC C4 C5 RBOOT PH R3 BOOT C2 R2 HVBIAS TYPICAL APPLICATION SS R5 PGOOD EXTBIAS L VO SW COMP C7 R8 R9 C10 C9 C8 RT R10 FB R6 PGND R7 AGND ILIM R11 Figure 1. Typical Application Table 1. APPLICATION DESIGN EXAMPLE L to be used (mH) CO from VO_RIPPLE (mF) CO from VOS (mF) CO from VUS (mF) 65.2 CO to be used fCO (Hz) Phase margin (⁰) 718.2 18.0k 69.4 R11 (W) R9 (W) R8 (W) C9 (F) C7 (F) C8 (F) VIN (V) VO (V) L (mH) 35 24 16.762 2.6 30.9 35 28 12.444 2.2 22.7 83.5 613.4 22.6k 67.5 35 30 9.524 2.1 19.8 103.6 571.6 22.6k 67.5 48 24 26.667 2.6 30.9 30.9 718.2 48 28 25.926 2.2 22.7 31.4 48 30 25.000 2.1 19.8 32.3 571.6 60 24 32.000 2.6 30.9 20.8 718.2 60 28 33.185 2.2 22.7 19.9 613.4 60 30 33.333 2.1 19.8 19.8 571.6 NOTE: 22.00 R10 (W) 75.2 28010 613.4 *Iout = 5 A, Fsw = 300 KHz www.onsemi.com 2 365 1.0k 2.7n 220n 470p RT (=R6) (W) 3.75E+04 FB SS UVLO EN/ 15 17 22 Start Soft PVCC Figure 2. Block Diagram www.onsemi.com 16 VCC 23 V REF FB PGOOD 20 Control Good Fault / Power Fault Control PWM 27 VCC HVBIAS VIN Feed−forward 18 GND Comparator Ramp COMP SW E/A PCL 19 RT Ramp Generator 13 V REF I SEN Limiting (PCL) Peak Current 21 MODE Sync Control and Frequency PWM Operation Startup Pre−bias VCC UVLO/POR Sleep Mode/ SYNC 14 LDO1 25 GND PCL Level Shift 24 PVCC PCL Protection Over Temp Control Deadtime LDO2 UVLO 26 EXTBIAS PVCC 29 BOOT I LG 12 Low−side I SEN High−side VIN 1−3, 31−35 PGND PH VINMON SW 30 28 7−10 3 4−6 ILIM FAN65004B BLOCK DIAGRAM FAN65004B 24 VCC 23 EN/UVLO 22 SYNC 21 PGOOD 20 RT 19 GND 18 11 10 LG MODE ILIM FB 17 16 15 14 13 COMP SS VIN VIN 1 VIN 2 VIN 3 VIN 4 PGND 5 PGND 6 PGND 12 9 8 7 SW PVCC SW 25 SW GND SW 26 31 32 33 34 35 NC EXTBIAS VIN 29 30 VIN BOOT 28 VIN VINMON 27 PH HVBIAS PIN CONFIGURATION Figure 3. Pin Assignment (Bottom View) Table 2. PIN DESCRIPTION Name Pin/Pad VIN 1−3, 31−35, VIN Pad PGND 4−6, PGND Pad SW 7−10 NC 11 No Connection LG 12 Gate of low side MOSFET MODE 13 Configures pulse modulation/frequency synchronization modes. See MODE description for details ILIM 14 Connect a resistor to GND to set the high-side MOSFET peak current limit FB 15 Feedback Voltage Input COMP 16 Output of internal error amplifier for external compensation SS 17 Set up soft-start time. Connect a capacitor between SS and PGND to set the soft start time. If left floating, part enters hiccup mode GND 18, 25 RT 19 Connect a resistor to GND to set switching frequency. If left floating, part enters hiccup mode PGOOD 20 Power good indicator, open-drain output. Level HIGH indicates VOUT is within set limits SYNC 21 The pin is used to synchronize frequency in when in Non-Master mode or out when in master mode EN/UVLO 22 Enable/VIN Under-Voltage-Lockout set pin. When used as enable function in-dependent of input voltage, connect this pin to a voltage > 1.22 V to enable or PGND to disable. When used as enable function at specific input voltage level, connect a resistor divider between input voltage and PGND to this pin Description Input voltage to power stage Power ground for power stage and PVCC Switching node, junction of high- and low-side MOSFETs Analog ground for VCC, RT, SYNC, MODE, etc. VCC 23 Bias power for internal analog circuits PVCC 24 LDO output and the bias supply for gate driver circuit EXTBIAS 26 Input voltage to the secondary LDO. Typically connect to VO when VO ≥ 5 V HVBIAS 27 Input voltage to the primary LDO. Also used for the feed-forward function. Connect it to power stage input with a small RC filter VINMON 28 Current sense positive pin. Do NOT connect anything BOOT 29 Bootstrap supply for high-side driver. Connect a low impedance capacitor between this pin and PH pin PH 30 High-side source connection (SW node) for the bootstrap capacitor www.onsemi.com 4 FAN65004B Table 3. ABSOLUTE MAXIMUM RATINGS Symbol Min Max Unit VIN Pin Voltage (System Supply) with regard to PGND −0.3 70 V VHVBIAS HVBIAS Pin Voltage with regard to PGND −0.3 70 VEXTBIAS EXTBIAS Pin Voltage with regard to PGND −0.3 70 VEN/UVLO EN/UVLO Pin Voltage with regard to PGND −0.3 8.4 VPH PH Pin Voltage with regard to PGND −0.3 70 VSW SW Pin Voltage with regard to PGND −0.3 70 SW Pin Voltage with regard to PGND (Pulse, 100 ns) −5.0 75 SW Pin Voltage with regard to PGND (Pulse, 30 ns) −7.5 75 BOOT Pin Voltage with regard to PGND −0.3 75 BOOT Pin Voltage with regard to PH Pin −0.3 6.5 ILIM Pin Voltage with regard to GND −0.3 6.5 PVCC Pin Voltage with regard to PGND −0.3 6.5 FB Pin Voltage with regard to GND −0.3 VCC + 0.3 VCOMP COMP Pin Voltage with regard to GND −0.3 VCC + 0.3 VPGOOD PGOOD Pin Voltage with regard to GND −0.3 VCC + 0.3 LG Pin Voltage with regard to PGND −0.3 VPVCC + 0.3 MODE Pin Voltage with regard to GND −0.3 VCC + 0.3 VRT RT Pin Voltage with regard to GND −0.3 VCC + 0.3 VSS SS Pin Voltage with regard to PGND −0.3 VCC + 0.3 VSYNC SYNC Pin Voltage with regard to GND −0.3 VCC + 0.3 VGND GND Pin Voltage with regard to PGND −0.3 0.3 ESD Human Body Model, ANSI/ESDA/JEDEC JS−001−2012 − 1000 Charged Device Model, JESD22−C101 − 500 Thermal Calculation − Tjn = kj1 • QLS + kj2 • QController + kj3 • QHS + kLead5 • TLead5 + kLead25 • TLead25 + kLead32 • TLead32 + kamb • Ta °C Junction Operating Temperature −55 150 °C Device Storage Temperature −55 150 VIN VBOOT VILIM VPVCC VFB VLG VMODE TJN (Note 1) TJ TSTG Parameter Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Units, temperatures must be in degrees Celsius, power values (Q) must be in watts. Measured on 2s2p board, 80 x 80 mm2 with 546 mm2 top layer spreader. Use coefficients as per below table: FAN65004B kj1 kj2 kj3 kLead5 kLead25 kLead32 kamb 2s2p board, 80 mm x 80 mm with 546 mm2 top layer spreader LS coefficients 8.7 4.6 2.8 0.39 0.10 0.24 0.26 LDO coefficients 4.6 46.0 2.0 0.24 0.29 0.18 0.29 HS coefficients 3.0 2.1 6.6 0.16 0.05 0.56 0.22 www.onsemi.com 5 FAN65004B Table 4. RECOMMENDED OPERATING CONDITIONS Symbol Min Typ Max Unit VIN Pin Voltage (System Supply) with regard to PGND 4.5 − 65 V VHVBIAS HVBIAS Pin Voltage with regard to PGND 4.5 − 65 VSW SW Pin Voltage with regard to PGND (DC) −0.3 − VIN VEXTBIAS EXTBIAS Pin Voltage with regard to PGND 4.5 − 65 VEN/UVLO EN/UVLO Pin Voltage with regard to PGND − − 7.5 VPG_SPLY PGOOD Pin Voltage with regard to GND VIN Parameter − − 5.4 TA Operating Ambient Temperature −40 − 125 °C TJ Junction Operating Temperature −40 − 125 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Table 5. ELECTRICAL CHARACTERISTICS (Typical application circuit shown in Figure 1 is used. VIN = VHVBIAS = 48 V, VOUT = 5 V, VPVCC = VCC = 5 V, −40°C < TJ = TA < +125°C. TA = TJ = +25°C for typical values.) Symbol Parameter Conditions Min Typ Max Unit mA SUPPLY IHVBIAS_Q_PWM Forced CCM Quiescent Current VEN = 2.0 V, MODE = 5 V through a 100 kW resistor, VFB = 0.64 V − 1.2 − IHVBIAS_Q_PSM DCM with Pulse Skipping Quiescent Current VEN = 2.0 V, MODE = 0 V through a 100 kW resistor, VFB = 0.64 V − 1.4 − IHVBIAS_SDN Shutdown Current VEN = 0 V − 5 9 mA VHVBIAS_TH HVBIAS UVLO Threshold HVBIAS Rising − 3.92 − V VHVBIAS_HYS HVBIAS UVLO Hysteresis HVBIAS Falling − 1.0 − LDO Output Voltage IPVCC = 1 mA and EXTBIAS pin is open 4.75 5.00 5.25 VEXTBIAS = 12 V, IPVCC = 1 mA LDOs VPVCC V 4.75 5.00 5.25 VHVBIAS_D LDO1 Dropout Voltage VHVBIAS = 5.0 V, LDO Output Current = 150 mA − 1.0 2.0 VEXTBIAS_D LDO2 Dropout Voltage VEXTBIAS = 5.0 V, LDO Output Current = 150 mA − 0.33 0.66 Switchover Voltage above which LDO1 is Disabled and LDO2 is Enabled VEXTBIAS is rising − 4.7 − VLDOSWO_HYS Switchover Voltage Hysteresis VEXTBIAS is falling − 100 − mV VSWTOLDO Threshold Voltage above which the LDO is in LDO mode VHVBIAS or VEXTBIAS is rising − 5.5 − V VLDOTOSW Threshold Voltage below which the LDO is in switch mode VHVBIAS or VEXTBIAS is falling − 5.4 − VLDOSWO VCC SUPPLY VCC Start Voltage VCC Rising 3.8 4.0 4.4 VCC_UVLO VCC UVLO Threshold VCC Falling 3.6 3.8 4.1 VCC_UVLO_HYS VCC UVLO Hysteresis − 0.2 − VCC_ON www.onsemi.com 6 V FAN65004B Table 5. ELECTRICAL CHARACTERISTICS (continued) (Typical application circuit shown in Figure 1 is used. VIN = VHVBIAS = 48 V, VOUT = 5 V, VPVCC = VCC = 5 V, −40°C < TJ = TA < +125°C. TA = TJ = +25°C for typical values.) Symbol Parameter Conditions Min Typ Max Unit TJ = 25°C, VIN = 4.5 V to 65 V 0.596 0.600 0.604 V TJ = −40°C to 125°C (Note 2) 0.594 − 0.606 REFERENCE VOLTAGE VREF Reference Voltage ENABLE AND UNDER VOLTAGE LOCK OUT VEN_TH EN/UVLO Threshold EN/UVLO Rising 1.141 1.22 1.296 V VEN_HYS EN/UVLO Hysteresis EN/UVLO Falling − 115 − mV REN_PD EN/UVLO Internal Pull down Resistance − 500 − kW VEN_CLP EN/UVLO Clamp Voltage − 2.5 − V REN_CLP EN/UVLO Clamp Resistance − 200 − kW IEN_CLP EN/UVLO Clamp Current − 22 − mA Resistor Connected to Mode Pin for Master Synchronization Mode 70 100 130 kW Resistor Connected to Mode Pin for Non-Master Synchronization Mode 1 − 5 kW 100 − 1000 kHz RT = 199 kW 85 100 125 RT = 8.0 kW 900 1000 1200 fSW3 RT Pin is Short-Circuited to VCC Pin 215 250 280 fSW4 RT Pin is Short-Circuited to GND Pin 425 500 575 TBD VEN = 2.5 V MODE RMASTER RNON_MASTER OSCILLATOR fSW Frequency Range fSW1 Switching Frequency Set by RT fSW2 FREQUENCY SYNCHRONIZATION VSYNC_IN_H SYNC Input Logic HIGH 2 − − VSYNC_IN_L SYNC Input Logic LOW − − 0.8 tHIGH_IN_MIN Input HIGH Level Pulse Width 150 − − tLOW_IN_MIN Input LOW Level Pulse Width 150 − − fSYNC tRT_SYNC_DL V ns Synchronizable Frequency Percentage of frequency set by RT 70 − 130 % Transition Delay from RT Set Frequency to Sync Frequency In Number of External Clock Cycles in 2 ms time period − 64 − Cycles RSYNC_PD SYNC Pin Pull down Resistance − 100 − kW RSYNC_DR_PU SYNC output Driver Pull-up Resistance − 10 − W RSYNC_DR _PD SYNC output Driver Pull-down Resistance − 13 − DSYNC_OUT SYNC Output Frequency Duty Cycle − 50 − % CL_SYNC SYNC Pin Lead Capacitance − − 200 pF www.onsemi.com 7 FAN65004B Table 5. ELECTRICAL CHARACTERISTICS (continued) (Typical application circuit shown in Figure 1 is used. VIN = VHVBIAS = 48 V, VOUT = 5 V, VPVCC = VCC = 5 V, −40°C < TJ = TA < +125°C. TA = TJ = +25°C for typical values.) Symbol Parameter Conditions Min Typ Max Unit − 25 − V/V ns RAMP AND PWM MODULATOR kPWM PWM Modulator Gain, VIN/DVRAMP VIN = VHVBIAS = 4.5 to 65 V TON_MIN PWM Minimum ON time − 150 200 TOFF_MIN PWM Minimum OFF time − 150 200 ERROR AMPLIFIER GBW Unit Gain Bandwidth − 10 − MHz G DC Gain − 80 − dB IFB FB Bias Current −50 5 50 nA COMP Source Current 2 7 − mA COMP Sink Current 2 8.5 − mA Enable High to Soft Start Ramp Start Delay − 1 3 ms 4.3 5 5.9 mA V ICOMP_SOURCE ICOMP_SINK VFB = 0.6 V SOFT START tSS_DL ISS Charging Current to SS Capacitor BOOT VBT_SWITCH Bootstrap Switch Voltage Drop BOOT Current, IBOOT = 50 mA − 0.1 − VBT_UVLO_TH BOOT UVLO Voltage with regard to PH BOOT Falling − 3.20 − VBT_UVLO_HYS BOOT UVLO Hysteresis with regard to PH BOOT Rising − 0.35 − Current Source Creating Current Limit Reference Voltage on R_ILIM − 8.5 − mA kILIM_HS High-side MOSFET current limit scale factor (ILIM_HS = kILIM_HS × RILIM) − 59.3 − mA/W kILIM_LS Low-side MOSFET current limit scale factor (ILIM_LS = kILIM_LS × RILIM) − 17.9 − CURRENT PROTECTION ILIM_S nCYCLE_OCP nCYCLE_SCP Number of Switching Cycle(s) before Entering Hiccup Mode ILIM_HS ≤ ISEN_PEAK < 130% ILIM_HS − 1024 − ISEN_PEAK ≥ 130%ILIM_HS − 1 − FB Pin Voltage for PGOOD to Be De-asserted When Down from Regulation FB Falling 88 92 96 FB Pin Voltage for PGOOD to Be De-asserted When up into OVP1 FB Rising 110 115 120 FB Pin Voltage for PGOOD to Be Asserted When Down from OVP1 FB Falling − 110 − FB Pin Voltage for PGOOD to Be Asserted When up into Regulation FB Rising − 94 − Cycle POWER GOOD VFB_NPG_TH VFB_PG_TH www.onsemi.com 8 %VREF FAN65004B Table 5. ELECTRICAL CHARACTERISTICS (continued) (Typical application circuit shown in Figure 1 is used. VIN = VHVBIAS = 48 V, VOUT = 5 V, VPVCC = VCC = 5 V, −40°C < TJ = TA < +125°C. TA = TJ = +25°C for typical values.) Symbol Parameter Conditions Min Typ Max Unit − 500 − ms − 5 − ms − 6 10 mV 110 115 120 %VREF 124 130 136 − 35 − − 1 − s °C POWER GOOD tPG_DL PGOOD Delay tPG_FLT PGOOD De-glitch Filter Duration VPG_L PGOOD Output LOW Voltage Time from when FB Reaches VFB_PG_TH to when PGOOD becomes HIGH VFB = 70%VREF, IPGOOD = −1 mA VOLTAGE PROTECTION VFB_OVP1 FB Pin Voltage for Level 1 Over Voltage Detection VFB_OVP2 FB Pin Voltage for Level 2 Over Voltage Detection VFB_UVP_TH FB Pin Voltage for Under Voltage Detection FB Voltage Rising FB Voltage Falling HICCUP tHICCUP Hiccup Time THERMAL SHUTDOWN TJ_SD Thermal Shutdown Threshold Temperature Rising − 150 − TJ_SD_HYS Thermal Shutdown Hysteresis Temperature Falling − 20 − Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Guaranteed by design www.onsemi.com 9 FAN65004B TYPICAL PERFORMANCE CHARACTERISTICS (Test at TA = 25°C, VHVBIAS = VIN = 48 V and VO = 28 V unless otherwise specified) 18 0.0020 FSW = 300 KHz QUIESCENT CURRENT (mA) LINE REGULATION (%) 0.0018 0.0016 0.0014 0.0012 0.0010 0.0008 0.0006 0.0004 0.0002 0 −50 −25 0 25 50 75 100 17 16 15 14 13 12 −40 125 −20 0 Figure 4. Line Regulation vs. Temperature 100 120 4.84 4.8 4.6 4.4 4.82 4.80 4.78 4.76 4.74 4.72 4.2 −40 −20 0 20 40 60 80 100 4.70 −40 120 −20 0 TEMPERATURE (°C) 20 40 60 80 100 120 TEMPERATURE (°C) Figure 6. Over Current vs. Temperature Figure 7. Shutdown Current vs. T at VHVBIAS = 48 V 4.3 3.3 4.2 3.2 VHVBIAS_TH_N (V) VHVBIAS_TH_P (V) 80 4.86 IHVBIAS_SDN (mA) OVER CURRENT (A) 5.0 60 Figure 5. VIN Quiescent Current vs. Temperature Vin = 48 V Vout = 12 V Fsw = 300 KHz R_LIM = 115 K 5.2 40 TEMPERATURE (°C) TEMPERATURE (°C) 5.4 20 4.1 4.0 3.9 3.8 3.7 3.1 3.0 2.9 2.8 2.7 3.6 −40 −20 0 20 40 60 80 100 2.6 −40 120 TEMPERATURE (°C) −20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 8. HVBIAS Rising Threshold vs. T Figure 9. HVBIAS Falling Threshold vs. T www.onsemi.com 10 120 FAN65004B TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) (Test at TA = 25°C, VHVBIAS = VIN = 48 V and VO = 28 V unless otherwise specified) 0.6010 1.2210 0.6005 1.2205 1.2200 0.5995 VEN_TH (V) VREF (V) 0.6000 0.5990 0.5985 1.2195 1.2190 1.2185 0.5980 1.2180 0.5975 0.5970 −40 −20 0 20 40 60 80 1.2175 −40 120 100 20 40 60 80 100 120 TEMPERATURE (°C) Figure 10. VREF vs T at VHVBIAS = 48 V Figure 11. EN/UVLO Threshold Voltage vs. T at VHVBIAS = 48 V 1400 150 1200 140 130 FSW (kHz) VEN_HYS (mV) 0 TEMPERATURE (°C) 160 120 110 1000 800 600 100 400 90 200 80 −40 −20 0 20 40 60 80 100 0 120 0 50 100 150 200 TEMPERATURE (°C) RT (kW) Figure 12. EN/UVLO Hysteresis Voltage vs. T at VHVBIAS = 48 V Figure 13. Switching Frequency vs. RT at VHVBIAS = 48 V and T = 255C 1020 251.5 251.0 FSW3 (kHz) 1019 FSW2 (kHz) −20 1018 1017 1016 1015 −40 250.5 250.0 249.5 249.0 −20 0 20 40 60 80 100 248.5 −40 120 −20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 14. Switching Frequency vs. T at VHVBIAS = 48 V and RT = 8.06 kW Figure 15. Switching Frequency vs. T at VHVBIAS = 48 V and RT shorted to VCC www.onsemi.com 11 120 FAN65004B TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) (Test at TA = 25°C, VHVBIAS = VIN = 48 V and VO = 28 V unless otherwise specified) 24.9 520 518 24.8 24.7 514 KPWM (V/V) FSW (kHz) 516 512 510 508 24.3 504 −20 0 20 40 60 80 24.2 −40 120 100 −20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 16. Switching Frequency vs. T at VHVBIAS = 48 V and RT shorted to GND Figure 17. PWM Modulator Gain, VIN / DVRAMP, vs. T at VHVBIAS = 48 V 154.2 154.4 154.0 154.2 153.8 154.0 153.6 TOFF_MIN (ns) 154.6 153.8 153.6 153.4 153.4 153.2 153.0 153.2 152.8 153.0 152.6 152.8 −40 −20 0 20 40 60 80 100 152.4 −40 120 −20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 18. TON_MIN vs. T at VHVBIAS = 48 V Figure 19. TOFF_MIN vs. T at VHVBIAS = 48 V 16 14 12 ILIM_S (mA) TON_MIN (ns) 24.5 24.4 506 502 −40 24.6 10 8 6 4 2 0 −40 −20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 20. 8.5 mA Current Source for Current Limit Purpose vs. T at VHVBIAS = 48 V www.onsemi.com 12 120 FAN65004B TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) (Test at TA = 25°C, VHVBIAS = VIN = 48 V and VO = 28 V unless otherwise specified) Figure 21. System Startup with No Load Figure 22. System Startup with No Load Figure 23. System Startup with 25% Pre-bias www.onsemi.com 13 FAN65004B TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) (Test at TA = 25°C, VHVBIAS = VIN = 48 V and VO = 28 V unless otherwise specified) Figure 24. System Startup with 75% Pre-bias Figure 25. Transition from Native Frequency to Sync Frequency in Non-Master Mode Figure 26. SYNC Output Frequency Duty Cycle in Master Mode Figure 27. Over-current Protection with 280 kHz Switching Frequency Figure 28. Power Good at Startup with No Load Figure 29. Power Good at Startup with No Load www.onsemi.com 14 FAN65004B TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) (Test at TA = 25°C, VHVBIAS = VIN = 48 V and VO = 28 V unless otherwise specified) Figure 30. OVP1 at VFB . 115% VREF Figure 31. OVP1 Release at VFB 3 110% VREF Figure 32. OVP2 at VFB . 130% VREF Figure 33. OVP2 Release at VFB 3 100% VREF Figure 34. UVP due to Deep Over-current Figure 35. Switching and Voltage Ripple www.onsemi.com 15 FAN65004B TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) (Test at TA = 25°C, VHVBIAS = VIN = 48 V and VO = 28 V unless otherwise specified) 99% Efficiency (%) 97% 95% 93% 35V VIN = 48V 60V VO = 28V fSW = 300kHz 91% 89% 87% 0 1 2 3 4 5 6 Load Current (A) Figure 36. Load Step between 50% and 100% Load Figure 37. System Efficiency 5 System Power Loss (W) Load Regulation (%) 0.15% 0.10% 0.05% 0.00% 35V VIN = 48V 60V VO = 28V fSW = 300kHz -0.05% -0.10% -0.15% 0 1 2 3 4 5 4 3 2 1 0 6 35V VIN = 48V 60V VO = 28V fSW = 300kHz 0 Figure 38. Load Regulation NOTE: 1 2 3 4 5 6 Load Current (A) Load Current (A) Figure 39. System Power Loss EXTBIAS is connected to VO for Figures 21−39 Functional Description the output voltage will be reduced in current limiting condition. Other protection functions include over temperature shut-down and over-voltage protection. At the beginning of each switching cycle, the clock signal initiates a PWM signal to turn on high-side MOSFET, and at the same time, the ramp signal starts to rise up. A reset pulse is generated by the comparator when the ramp signal intercepts the COMP signal. This reset pulse turns off high-side MOSFET and turns on low-side MOSFET until next clock cycle comes. In the case that current limit is hit, a peak current limiting (PCL) signal is generated to turn off the high-side MOSFET until the next PWM signal. This is cycle by cycle current limit protection. When certain faulty condition is met, the device enters hiccup mode to further protect itself. FAN65004B is a high-efficiency synchronous buck converter with integrated controller, driver and two power MOSFETs. It can operate over a 4.5 V to 65 V input voltage range, and delivers 6 A load current. The internal reference voltage is 0.6 V ±1% over −40°C to 125°C temperature range. FAN65004B uses voltage mode PWM control scheme with input voltage feed-forward feature for the wide input voltage range. The high bandwidth error amplifier monitors the output voltage and generates the control signal for the pulse width modulation block. By adjusting the external compensation network, the system performance can be optimized based on the application parameters. The switching frequency is set by an external resistor and can be synchronized to an external clock signal. To improve light load efficiency (low IQ mode), either low-side MOSFET is turned off when the inductor current drops to zero or pulse skipping is implemented when load current further decreases. The high-side MOSFET current sense circuit is adopted for the peak current limiting function and LDOs Two LDOs are included in FAN65004B to provide internal supply and to balance power loss from them. The LDO block diagram is shown below. www.onsemi.com 16 FAN65004B PVCC together with a ceramic capacitor between VCC and GND to form a filter for the VCC bias supply for the internal control circuits. When VCC voltage drops below its UVLO, the regulator control circuit blocks are disabled. BOOT EXTBIAS LDO2 VIN: 4.5 V~65 V HVBIAS LDO1 Sync Control C2 Enable and Under Voltage Lock-Out EN/UVLO signal is used for device enable/disable when its voltage is higher/lower than the threshold, VEN_TH, which is typical 1.22 V. The precision threshold voltage of this signal can also be used to set a system input voltage level, above which FAN65004B will be enabled and below which disabled. Figure 41 shows the EN/UVLO block diagram and application configuration. A resistor divider (R2 and R3 as shown in Figure 1) can be used to set the level of input voltage, VIN_UVLO, which enables the device. Selection of R3 is determined by Equation 1. Internal Bias and Feed-forward Feature REG Figure 40. LDO Block Diagram Since LDO1 input, HVBIAS, is also used for initial internal bias and for input voltage feed-forward compensation, system input voltage, VIN, should always be connected to HVBIAS pin and an RC filter is recommended between VIN and HVBIAS to filter any noise from high frequency switching. During power up, LDO1 is always selected. After the system finishes soft start, which LDO block is selected depends on voltages appearing on both HVBIAS and EXTBIAS pins. If there is a voltage at EXTBIAS pin and it is above 4.7 V, LDO2 will be selected, otherwise LDO1 will continue to supply power to the device. EXTBIAS can be left open for single LDO operation all the time. In the case that EXTBIAS is connected to a voltage, VEXT, and VEXT > 4.7 V and also VEXT > VHVBIAS, LDO2 will be selected. This makes power loss on LDO2 greater than that on LDO1 if LDO1 were selected. So it’s the designer’s responsibility to make sure VEXT < VHVBIAS while VEXT > 4.7 V. Both LDOs work in switch mode when their input voltages are lower than 5.4 V. This allows very low voltage drop on both LDOs and ensures high enough voltage level on PVCC for internal bias and MOSFET drive. Assuming VEXT < VHVBIAS while VEXT > 4.7 V, Table 6 shows which LDO will be selected and the LDO work status. (• indicates which LDO and mode are selected and × means disabled) R3 + V EN_TH V IN_UVLO R EN_PD1 Assuming i, in mA, is the current flowing through R2 when working input voltage is VIN , then R2 is determined by Equation 2. R2 + V IN_UVLO * V EN_TH V IN V IN_UVLO i (eq. 2) VIN = 4.5 V~65 V VCC i R2 REN_CLP = 200 kW EN/UVLO 2.5 V VEN < 1 V R3 PGND VEN > 1 V EN/UVLO Threshold 1.22 V LDO2 HVBIAS (V) EXTBIAS (V) Switch LDO Switch LDO 4.5−4.7 4.5−4.7 • × × × 4.7−5.5 4.5−4.7 • × × × 4.7−5.5 × × • × 4.5−4.7 × • × × 4.7−5.5 × × • × 5.5−50 × × × • 5.5−65 R2 * V EN_TH R2 and R3 are both in kW. Work Mode LDO1 (eq. 1) R EN_PD1 R EN_PD1 * V EN_TH Table 6. LDO SELECTION AND WORK MODE Input R2 REN_PD2 = 500 kW R1 REN_PD1 = 150 kW VEXT Figure 41. EN/UVLO Block Diagram For example, a converter has nominal input voltage of VIN = 48 V. It’s desired that the device is enabled when input voltage is above 35 V, which makes VIN_UVLO = 35 V. If 50 mA is chosen, then Equations 1 and 2 yield R2 and R3 in Equations 3 and 4 respectively: R2 + Both LDOs are designed to deliver up to 150 mA current. A 4.7 mF ceramic capacitor between PVCC and PGND placed as close as possible to PVCC pin is recommended to decouple any noise from high frequency driver currents. A 1 W resistor can be used between PVCC and VCC R3 + 35 48 35 17 50 10 *6 10 3 + 926.5 kW 1.22 926.5 150 150 * 1.22 926.5 * 1.22 + 43.1 kW www.onsemi.com (35 * 1.22) 150 (eq. 3) (eq. 4) FAN65004B Pre-bias Startup Choose the closest standard 1% resistor values of R1 = 931 kW and R2 = 43.2kW. What value is chosen for i is a power loss matter. The greater the i is, the greater the power loss will be, and vice versa. But if the current is too low, the EN/UVLO signal will be vulnerable to noise. Choose the highest possible current that only creates negligible power loss to the system. In the example shown above, the power loss in this EN/UVLO branch is P = VIN × i = 48 V × 50 mA = 2.4 mW. When the device is disabled, only a few micro-ampere current is required to support essential blocks like bandgap. Only after the device is enabled, major functions like, LDO, oscillator, soft start, driver, logic control, start to run. The device is disabled if the EN/UVLO pin is floating. A pre-biased regulator is one that, before the regulator is powered, has output voltage above 0, and so for the FB pin. FAN65004B is able to start in such a case. When soft start is initiated, both high- and low-side MOSFETs are forced off until the SS pin is charged up to the pre-biased FB voltage. The following startup process will be a normal soft start process as stated in “Soft Start” section. Switching Frequency The internal clock generator can be programmed from 100 kHz to 1 MHz by a resistor connected between the RT pin and the GND pin. To set the desired switching frequency, the resistor can be calculated by Equation 5 as shown below: f SW + min Soft Start The soft start block diagram is shown in Figure 42. ƪRT10) 2.5 ) 50, 1300ƫ 4 (eq. 5) where fSW is in kHz and RT is in kW. VCC The switching frequency vs. the external resistor curve is shown below. Switching Frequency, fSW vs. RT 5 mA 1400 _ SS Switching Frequency, fSW (kHz) FB EA + + C6 VREF Figure 42. Soft Start Block Diagram 1200 1000 800 600 400 200 0 1 10 100 1000 RT (kW) The soft start function is enabled with a delay of maximum 3 ms after EN is high. During the delay, the SS capacitor is discharged if there is any residual voltage. If SS voltage is still not 0 after this delay, a fault condition is created and the device enters hiccup mode, otherwise soft start process is initiated. A typical 5 mA constant current flows out of SS pin to charge the capacitor at SS pin. The error amplifier regulates the converter output voltage according to the lower value of SS pin voltage and the fixed 0.6 V reference voltage. With the constant current, SS voltage linearly ramps up from 0, and the regulator output voltage follows the SS voltage to ramp up. SS voltage continues to rise after it exceeds the 0.6 V reference voltage, at which point, the SS voltage is out of the loop and the converter output voltage is regulated to the reference voltage of 0.6 V. When SS capacitor is charged to 1.5 V, the SS timer stops counting and the device checks if FB has reached 94% VREF. If not, the device enters hiccup mode, otherwise, the device considers the soft start successful and continues to charge SS capacitor until it reaches VCC. If the SS pin is floating, device enters hiccup. Figure 43. Relationship between RT and fSW As soon as the device is enabled, it will go through a set of routine to check the RT pin configuration to determine the switching frequency or if there is any fault. If RT is tied to VCC, the switching frequency is 250 kHz, and 500 kHz if short-circuited to GND. If RT pin is floating initially or becomes open from any non-open state, the device enters hiccup mode. Frequency Synchronization FAN65004B can be set to work in either master mode or non-master mode. When in master mode, it sends out clock signal through SYNC pin; when in non-master mode, it either takes in clock signal from an external source on SYNC pin in ±30% of RT set frequency or uses RT to set its clock. Both modes are configured via MODE pin. 1. Master mode: A 100 kW resistor connected between MODE pin and either VCC or GND will enable master mode. In this mode, FAN65004B www.onsemi.com 18 FAN65004B CCM) and discontinuous conduction with pulse skipping modulation (Short-formed DCM with Pulse Skipping). When in DCM with Pulse Skipping, device works in discontinuous conduction mode when inductor current hit 0 and may skip pulses when load becomes even lighter; device transits to fixed frequency operation and works in continuous conduction mode when inductor current valley is higher than 0. Frequency synchronization refers to master or non-master mode. If low output voltage ripple is desired, Forced CCM PWM operation can be selected. In this mode, continuous conduction fixed switching frequency applies regardless of light load or heavy load and negative current appears at light load condition. This results in greater power loss at light load. To reduce the power loss at light load, DCM with Pulse Skipping can be chosen. When at light load, the device works in discontinuous conduction mode and skips pulses, so that the power loss is reduced. The relationship between the MODE configuration and the actual mode is illustrated in the following table: generates its ramp and PWM signal by its own and sends out PWM clock through SYNC pin with 180 degree phase shift and 50% duty cycle. If an external clock is detected on SYNC pin that is in conflict with the internal one, FAN65004B makes SYNC pin high impedance until fault is cleared. 2. Non-master mode: The MODE pin connected to either VCC or GND through a 1 kW~5 kW resistor or left floating enables this mode. In this mode, the device keeps checking the SYNC pin for incoming clocks every 2 ms. If 64 cycles of clock are detected and the clock frequency is in ±30% of RT set frequency, the device is in sync with the clock appearing on SYNC pin. If no clocks are detected, the number of clocks in 2 ms does not reach 64, or the clock frequency is not within ±30% of RT set frequency, the device uses RT to set the clock. The synchronization block diagram is shown below. VCC Master Mode HiZ SYNC 10 W 100 kW Table 7. OPERATION MODES WITH MODE CONFIGURATION CLK_PWM 10 W RX MODE Pin Configuration SCLK LOGIC CONTROL SCLK_Present SCLK_IN AGND Figure 44. Frequency Synchronization Block Diagram FAN65004B implements fault protection in case SYNC pin is short-circuited to either GND or VCC. The logic checks voltage levels of both internal driving clock and SYNC pin except for a 100 ns time period at every clock transition, which is used to mask the transition glitches due to propagation delay. These 2 logic levels are expected to be the same when there is no pin fault. When SYNC pin fault is detected, the driver is disabled by using high impedance for 8 clock cycles, which makes worst case duty cycle of ~1.67% with 1 MHz frequency. SYNC pin fault is only a local fault and doesn’t trigger global hiccup or stop device operation. Figure 44 shows the frequency synchronization block diagram. Operation Mode Pulse Modulation Freq Sync VCC ← R = 1 kW~5 kW → MODE Forced CCM Non-master VCC ← R = 100 kW ±30% → MODE Forced CCM Master GND ← R = 1 kW~5 kW → MODE DCM with Pulse Skipping Non-master GND ← R = 100 kW ±30% → MODE DCM with Pulse Skipping Master Floating Forced CCM Non-master Power Good A comparator monitors the FB voltage and controls an open drain MOSFET. The PGOOD pin is connected to the Drain of this MOSFET. To correctly use the PGOOD signal, a pull-up resistor connected to an external voltage source is required. When FB voltage exceeds 94% of VREF (typical 0.6 V), PGOOD signal is asserted after a delay, tPG_DL, and when it’s below 92% of VREF it is de-asserted. PGOOD signal is valid only after device is enabled and soft start is completed (SS ramps above 0.6 V). When OVP1 is detected, PGOOD is de-asserted. PGOOD is re-asserted with 5% hysteresis. Figure 45 shows the internal circuitry connected to PGOOD pin. Operation Modes The MODE pin controls 2 functions: pulse modulation and frequency synchronization. Pulse modulation refers to continuous conduction fixed frequency pulse width modulation (short-formed Forced www.onsemi.com 19 FAN65004B The worst case of over current is such conditions as short-circuited output or saturated inductor, in which the current exceeds 130% of current limit. In this case, device initiates short circuit protection and enters hiccup mode immediately. For low-side MOSFET, FAN65004B performs cycle by cycle protection if its current limit is hit. At each cycle of low-side MOSFET turn-on, its current is checked. If the current exceeds its current limit, ILIM_LS, the low-side MOSFET will be turned off immediately and remains off until next switching cycle. This process repeats until the over current event is released (low-side MOSFET current becomes less than ILIM_LS). Low-side MOSFET over current protection doesn’t affect high-side MOSFET switching, i.e. high-side MOSFET remains normal switching if high-side MOSFET over current event does not occur. External Voltage VCC RPG PGOOD NOT Power Good Figure 45. PGOOD Block Diagram Setting Current Limit A resistor, R_ILIM, connected between ILIM pin and GND is used to set the current limit for both high- and low-side MOSFETs. An 8.5 mA internal current source flows through R_ILIM, creating a reference voltage, and the voltage drops on RDSON of both high- and low-side MOSFETs are used to compare with this reference voltage. This comparison generates an over current event. The high-side MOSFET current is monitored in forward direction, i.e. current flows from drain to source, while low-side MOSFET current is monitored in a reverse direction. When low-side MOSFET turns on in a normal condition, its current flows from ground to switching node. Current is NOT monitored in this case. If current flows from switching node to ground, it is considered abnormal and is monitored. The current limit for both high- and low-side MOSFETs is calculated the same way, ILIM = kILIM × RILIM, and kILIM parameters for both high- and low-side MOSFETs are shown in the Electrical Characteristic Table. If ILIM is tied to VCC, system is in standby mode, enabling all blocks except driver. R_ILIM below 60 kW is defined as short-circuit, above 350 kW is considered to be open. Hiccup Mode Hiccup mode is described as follows. When a fault condition is met, both high- and low-side MOSFETs turn off for a period of time, tHICCUP (typical 1 s), and soft start capacitor is discharged. Then device enters soft start. After soft start, if the fault condition is met again, both high- and low-side MOSFETs turn off for tHICCUP again and soft start capacitor is discharged…System returns to normal operation after the fault event is released. Over Voltage Protection (OVP) There are 2 levels of over voltage protection: over voltage protection 1 (OVP1) and over voltage protection 2 (OVP2), which are defined below respectively. 1. OVP1 is protection when FB voltage is above 115% but below 130% of VREF. When OVP1 is triggered, both high- and low-side MOSFETs are turned off immediately. When FB falls to or below VREF, the system returns to normal operation and initiates a new PWM signal at the next clock cycle. 2. OVP2 is protection when FB voltage is above 130% of VREF. When OVP2 is triggered, the high-side MOSFET is turned off immediately while the low-side MOSFET is turned ON. If over current event occurs during the low-side MOSFET ON time, cycle by cycle protection will be performed as described in “Over Current Protection (OCP) and Short Circuit Protection (SCP)” section. As soon as over current event is released, the low-side MOSFET will be kept on again until FB voltage drops to or below VREF. One hiccup cycle is initiated once FB voltage reaches 100%VREF. After the hiccup, the part will go into a soft start sequence and try to regulate. If OVP2 happens during the hiccup timing period, nothing will happen. Over Current Protection (OCP) and Short Circuit Protection (SCP) FAN65004B implements over current protection for high-side and low-side MOSFETs differently. For high-side MOSFET, FAN65004B sets two levels of over load protection according to the current limit setting: over current protection (OCP) and short circuit protection (SCP). OCP happens when the high-side MOSFET current, iDS_HS, is in the range of; 100% ILIM_HS ≤ iDS_HS < 130% ILIM_HS, and SCP occurs when iDS_HS ≥ 130% ILIM_HS. FAN65004B monitors MOSFET current constantly and provides cycle by cycle peak current limit. The high-side MOSFET is turned off whenever its current exceeds the limit. Once the current limit is hit, FAN65004B counts. If 1024 consecutive OC events have reached, regardless of the FB voltage, the system enters hiccup mode. In the case of OVP, power good signal is de-asserted and re-asserted after VFB comes down to 110%VREF. www.onsemi.com 20 FAN65004B Under Voltage Protection (UVP) C MIN + Under voltage is a condition when output voltage is below 35% of its regulated level (checked on FB pin). If VFB ≤ 35% is met, then under voltage protection (UVP) is initiated, where IC enters hiccup mode. F SW @ DI L @D (eq. 6) I CIN(RMS) + I OUT @ 2 8 @ F SW @ L @ C OUT DI L(pp) Ǹ12 DIL(pp) 2 12 Ǔ (eq. 12) Selecting External Compensation: The FAN65004B is a voltage mode buck regulator with an error amplifier compensated by external components to achieve accurate output voltage regulation and to respond to fast transient events. The goal of the compensation network is to provide a loop gain function with the highest cross−over frequency at adequate phase and gain margins. The output stage (LC) of the buck regulator is a double pole system. The resonance frequency of this lowpass filter is shown below: (eq. 7) ƒ p0 + 1 2p @ ǸLC OUT (eq. 13) The output filter has a zero that is calculated from the output capacitance and output capacitor ESR: ƒ z0 + 1 2p @ ESR @ C OUT (eq. 14) The bode plot of the power stage, error amplifier and the desired loop gain are drawn in the figure below. The first zero (fz1) compensates the phase lag of the pole located at the origin followed by a second zero (fz2) to compensate for one of the poles of the LC filter in order to crossover (fc) at −20 dB slope. The second pole (fp2) is aimed to cancel the ESR zero and finally the third pole (fp3) is to provide attenuation for frequencies above fsw/2. (eq. 8) And the RMS current through it is I COUT(RMS) + I OUT @ ǒ D@ 1*D) Loop Compensation In general, the output capacitors should be selected to meet the dynamic regulation requirements including ripple voltage and load transients. 1. For ripple voltage considerations; the output bulk maintains the DC output voltage. The use of ceramic capacitors is recommended to sustain a low output voltage ripple. At switching frequency the ceramic capacitors are capacitance dominante use the following equation for calculating Cout where the ripple output voltage is within 1% of Vout. D OUT + Ǹ Ceramic capacitors are best known for low ESR and are highly recommended. Output Capacitor Selection V OUT @ (1 * D) (eq. 11) Voltage and RMS current rating of the input capacitors are critical factors. Typically input capacitor is designed based on input voltage ripple of 2%. Capacitor voltage rating must be at least 1.25x greater than max input voltage . Maximum RMS current supplied by the input capacitance occurs at 50% duty cycle and when Vin =2 x Vout. RMS current varies with load as shown below: Lower ripple current reduced core losses in the inductor and output voltage ripple. Highest efficiency is obtained at low frequency with small ripple current, however with a disadvantage of using a large inductor. Inductor value can be chosen based on the equation below in order to not exceed a max ripple current (usually 30% to 70% of max inductor current) Lw DI L 2 Input Capacitor Selection The output inductor is selected to meet the output ripple requirements. The inductor value determines the converter’s ripple current DIL. Largest ripple current occurs at highest Vin voltage. ǒVIN * VOUTǓ (eq. 10) * V OUT 2 Where CMIN is the minimum value of output capacitor required, L is the output inductor, IPK is the peak load current, VOV is the increase in output voltage during a load release, VOUT is output voltage. Output Inductor Selection F SW @ L @ V IN 2 I PEAK + I OUT,MAX * The device keeps monitoring the junction temperature. When the sensed temperature is above the protection point, TJ_SD, over temperature protection (OTP) event occurred and the system shuts down. OTP is released when the sensed temperature is 20° lower than the trip point, TJ_SD, where the system resets through soft-start. ǒVIN * VOUTǓǒV OUTǓ ǒV OV ) VOUTǓ where IPK is defined as: Over Temperature Protection (OTP) DIL + L @ I PK 2 (eq. 9) 2. The maximum capacitor value required to provide the full, rising step, transient load current during the response time of the inductor is shown www.onsemi.com 21 FAN65004B Layout Guidelines 1. Place RT resistor and SS capacitor close to RT and SS pins. 2. Use a low impedance source such as a logic gate to drive the SYNC pin and keep the PCB trace as short as possible. 3. Components of digital signals like EN/UVLO, PGOOD and SYNC can be placed far away from device. 4. Place BOOT capacitor right next to BOOT and PH pins. If flexibility of high−side MOSFET driving strength is desired, place a resistor in series with this BOOT capacitor. For Vin > 40 V, use Rboot = 2 ohm. 5. Place inductor on top layer. Restrict the SW trace to only cover the inductor pin but keep its trace as wide as possible for thermal relief. 6. Avoid all the compensation components from passing through, above or underneath switching trace. 7. Keep the switching nodes away from sensitive small signal nodes (FB). Ideally the switch nodes printed circuit traces should be routed away and separated from the IC and especially the quiet side of the IC. Separate the high dv/dt traces from sensitive small−signal nodes with ground traces or ground planes. 8. Place decoupling caps right next to PVCC, VCC , HVBIAS and EXTBIAS. 9. The output capacitors should be placed as close to the load as possible. Use short wide copper regions to connect output capacitors to load to avoid inductance and resistances. Figure 46. Power Stage, Loop Gain and Compensator Bode Plots For ease of calculation, with C1 >> C3: ƒ z1 + 1 2p @ (R10 ) R9) @ C9 ƒ z2 + 1 2p @ R8 @ C7 ƒ p2 + 1 2p @ R9 @ C9 ƒ p3 + 1 2p @ R8 @ C8 ƒc + V IN 2p @ V Ramp @ R10 @ C7 Thermal Considerations The temperature gradients on the FAN65004B are shown below. While measuring the thermal performance, place the thermocouple at the hottest spot of the IC (not at the center of the part). www.onsemi.com 22 FAN65004B Table 8. ORDERING INFORMATION Part Number Current Rating (A) Input Voltage Max. (V) Frequency Max. (kHz) Package FAN65004B 6 65 1000 PQFN 6.0 × 6.0 mm www.onsemi.com 23 FAN65004B PACKAGE DIMENSIONS PQFN35 6X6, 0.5P CASE 483BE ISSUE O www.onsemi.com 24 FAN65004B PACKAGE DIMENSIONS PQFN35 6X6, 0.5P CASE 483BE ISSUE O www.onsemi.com 25 FAN65004B PowerTrench is a registered trademark of of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ◊ N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 www.onsemi.com 26 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative FAN65004B/D