DATA SHEET
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Constant-Voltage
Primary-Side-Regulation
PWM Controller for Power
Factor Correction
FL7740
SOIC10
CASE 751EE
MARKING DIAGRAM
Description
The FL7740 provides accurate CV regulation in the steady state
with differentiated dynamic function to minimize overshoot and
undershoot of output voltage in line and load transient condition.
Standby power is less than 0.3 W for smart lighting application and
power factor is higher than 0.9 even at half load condition when
enabling PF optimizer for wide output power scalability.
Startup time is less than 0.2 sec with built−in high voltage startup
circuit and output voltage quickly reaches to the target CV level by
loop gain transition technique during startup.
Various protections such as Overload, output diode short, sensing
resistor short, output short and output over voltage protection
guarantee high system reliability.
Z = Plant code
X = 1 digit year code
Y = 1 digit week code
KK = 2 digit lot traceability code
M = Package code
A = Product version
PIN CONNECTIONS
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
ZXYKK
FL7740
MA
Wide Universal Input Range (90 VAC ~ 305 VAC)
Precise CV Regulation in the Steady State: < ±3 %
CV Regulation in the load Transient: < ±10 %
Overshoot−Less Fast HV Start Up Time (< 0.2 s)
Low Standby Power
PF Higher than 0.9 at High−Line and Half load by PF Optimizer
Pulse−by−Pulse Current Limit
Output Short Protection
Output Over Voltage Protection
Output Diode Short Protection
Sensing Resistor Short & Open protection
Over Load Protection
These Devices are Pb−Free Devices
VDD
1
HV
GND
NC
GATE
COMV
CS
BIAS
VS
PF
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 13 of
this data sheet.
Typical Applications
• LED Lighting System
• AC−DC Adapters, TVs, Monitors
• Off Line Appliances Requiring Power Factor Correction
© Semiconductor Components Industries, LLC, 2016
April, 2022 − Rev 5
1
Publication Order Number:
FL7740/D
FL7740
BLOCK DIAGRAM
VOUT.MAIN
Secondary
DC−DC
Converter
VAC
FL7740
VDD
HV
GND
NC
GATE
Dimming
Signal
VOUT.BIAS
Dimming
Control
Module
COMV
CS
BIAS
VS
PF
0−10, DALI,
Wireless, etc.
Figure 1. Application Schematic
Dynamic
control
GND
VDYN−REF1,2,3
VS
HV
GM amp.
VREF
VEAV
S/H
NC
JFET
VDD
COMV
Gain control at startup
Digital Duty Control
BIAS
PF
5V regulator
Protection
VIN.PK
VOUT open/short protection
RCS open/short protection
Over current protection
Over load protection
Thermal shutdown
Digital PF
optimizer
CPF detector
Driver
VDYN−REF
control
Shutdown
Figure 2. Simplified Block Diagram
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2
GATE
CS
VDD
EAV
FL7740
FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
Description
1
VDD
IC Supply
2
GND
Ground
3
GATE
PWM Driver
Output
This pin uses the internal totem−pole output driver to drive the power MOSFET.
4
CS
Current Sense
Connected to a current sense resistor to detect the MOSFET current for pulse−
by− pulse current limit.
5
VS
Voltage Sense
This pin is connected to the auxiliary winding of the transformer via a resistor
divider to detect the output voltage.
6
PF
Power Factor
This pin is connected to a resistor to optimize power factor.
7
BIAS
Internal Circuit
BIAS
Bypass pin for the internal supply, which powers all control circuitry on the IC.
8
COMV
Loop
Compensation
This pin is connected to a capacitor between COMV and GND for compensation.
9
NC
No Connection
10
HV
High Voltage
IC operating current and MOSFET driving current are supplied using this pin.
Controller ground pin.
This pin is connected to the rectified input voltage via a resistor for fast startup.
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3
FL7740
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Ratings
Units
VHV(MAX)
HV Pin Voltage Range
560
V
VMV(MAX)
VDD, GATE Pin Voltage Range
−0.3 to 30
V
VLV(MAX)
COMV, PF, BIAS, VS, CS Pin Voltage Range
−0.3 to 6
V
VS, CS Pin Negative Pulse Voltage at ILV < 0.2 A and tPULSE <
300 ns
−1.5
V
PD(MAX)
Maximum Power Dissipation (TA < 50°C)
663
mW
TJ(max)
Maximum Junction Temperature
150
°C
VLV(PULSE)
TSTG
Storage Temperature Range
−55 to 150
°C
RJA
Junction−to−Ambient Thermal Impedance
158
°C/W
RJC
Junction−to−Case Thermal Impedance
39
°C/W
ESDHBM
ESD Capability, Human Body Model (Note 2)
2
kV
ESDCDM
ESD Capability, Charged Device Model (Note 2)
2
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78
RECOMMENDED OPERATING RANGES
Symbol
TA
Parameter
Ambient Temperature
Min
Max
Unit
−40
125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS
VDD = 18 V and TJ = −40 ~ 125°C unless otherwise specified
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
VDD Section
VDD−ON
Turn−On Threshold Voltage
14.5
16.0
17.5
V
VDD−OFF
Turn−Off Threshold Voltage
6.75
7.75
8.75
V
3
5
6.5
mA
1
mA
IDD−OP
Operating Current
IDD−AR
Operating Current during Auto Restart
VDD−OVP
VBIAS
CLOAD = 1 nF, VDD = 18V
0.3
VDD Over−Voltage−Protection
VBIAS Voltage
24
25
26
V
4.85
5.00
5.15
V
0.2
V
GATE Section
VOL
Output Voltage Low
VOH
Output Voltage High
VDD = 18 V
Peak Sourcing Current
Design guaranteed
Isource
17.8
V
mA
180
210
CLOAD = 1 nF, VDD = 20 V
CLOAD = 1 nF, VDD = 23 V
Peak Sinking Current
Design guaranteed
CLOAD = 1 nF, VDD = 20 V
CLOAD = 1 nF, VDD = 23 V
tr
Rising Time
CLOAD = 1 nF
110
150
190
ns
tf
Falling Time
CLOAD = 1 nF
40
60
80
ns
Supply Current From HV Pin
VHV = 560 V, VDD = 0 V
3
9
mA
Isink
mA
385
435
HW Section
IHV
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4
FL7740
ELECTRICAL CHARACTERISTICS (continued)
VDD = 18 V and TJ = −40 ~ 125°C unless otherwise specified
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
1
10
A
400
500
600
ms
HW Section
IHV−LC
Leakage Current after Startup
tR−JFET
JFET Regulation Time at Startup
Design guaranteed
VDD−JFET−HL
VDD High Limit during JFET Regulation
17.5
19.0
20.5
V
VDD−JFET−LL
VDD Low Limit during JFET Regulation
15.5
17.0
18.5
V
PWM Section
TON−MIN−MIN
Min. Turn−on Time Min. Limit
Design guaranteed
0.40
s
TON−MIN−MAX
Min. Turn−on Time Max. Limit
Design guaranteed
2.0
s
Max. Turn−on Time
Design guaranteed
23.3
s
TON−MAX
Oscillator Section
f
MAX
Max. Frequency
60
65
70
kHz
f
Min. Frequency
0.72
0.80
0.88
kHz
MIN
Current Sense Section
t
LEB
Leading−Edge Blanking Time
Design guaranteed
t
Propagation Delay to GATE
Design guaranteed
50
100
150
ns
tDIS Blanking Time at VS Sampling
Design guaranteed
0.95
1.00
1.05
s
VS Clamping Voltage
IVS=1 mA
IVS=10 A
−0.1
0.35
V
3.535
V
+0.7
+1.2
%
PD
300
ns
Voltage Sense Section
t
DIS−BNK
VVS−CLAMP
VREF
CVREGULATION
gM
ICOMV−SINK
ICOMV−SOURCE
Reference Voltage
CV Regulation Tolerance
3.465
VVS = 3.5 V, TJ = 25°C
VVS = 3.5 V, TJ = −40~125°C
Transconductance
3.5
−0.7
−1.2
16
20
24
mho
COMV Sink Current
VVS = 4 V
8
10
12
A
COMV Source Current
VVS = 3 V
8
10
12
A
VCOMV−HGH
COMV High Voltage
VCOMV−LOW
COMV Low Voltage
4.7
V
0.1
V
Start Sequence Section
tSOFT−START
Soft Start Time
Design guaranteed
25.6
ms
tSS1−MIN
SS1 Minimum Time
tSS1−MAX
SS1 Maximum Time
Design guaranteed
2
ms
Design guaranteed
100
ms
tSS21
tSS22
SS21 Time
Design guaranteed
45
ms
SS22 Maximum Time
Design guaranteed
30
ms
Dynamic Section
VDYN−REF−SET
DYN Reference Set Threshold
0.72
tDYN−REF−SET
DYN Reference Set Time
Design guaranteed
VOV−REF5
OV Reference 5
Design guaranteed
VOV−REF4
OV Reference 4
VOV−REF3
OV Reference 3
+9
VOV−REF2
OV Reference 2
+4.7
VOV−REF1
OV Reference 1
+1.86
VUV−REF1
UV Reference 1
VUV−REF2
UV Reference 2
VUV−REF3
UV Reference 3
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5
0.88
5
+15
V
s
+20
+14
Design guaranteed
0.80
%
+16
%
+10
+11
%
+5.7
+6.7
%
+2.86
+3.86
%
−3.86
−2.86
−1.86
%
−6.7
−5.7
−4.7
%
−10
%
FL7740
ELECTRICAL CHARACTERISTICS (continued)
VDD = 18 V and TJ = −40 ~ 125°C unless otherwise specified
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Protection Section
tAR
Auto Restart Delay Time
Design guaranteed
3
s
VVS−OS−H
’H’ VS Ouptut Short Hys. Voltage
0.85
0.90
0.95
V
VVS−OS−L
’L’ VS Ouptut Short Hys. Voltage
0.65
0.70
0.75
V
tOSP−DELAY
OSP Delay Time
Design guaranteed
35
ms
VCS−HIGH−CL
High Current Limit Threshold
1.13
1.20
1.27
V
VCS−LOW−CL
Low Current Limit Threshold
0.15
0.20
0.25
V
VCS−OCP
Over Current Protection Voltage
VCS−SRSP
CS Threshold Voltage for SRSP
tTON−MAX−SRSP
1.8
V
0.040
0.075
0.125
V
7.5
1.3
10.0
1.6
12.5
1.9
s
Max. Turn−on Time for SRSP
IVS = 100 A
IVS = 700 A
TOTP
Threshold Temperature for OTP
Design guaranteed
150
°C
TOTP−HYS
Junction Temperature Hysteresis
Design guaranteed
30
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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FL7740
TYPICAL CHARACTERISTICS
20
6.0
19
5.8
5.6
5.4
17
VBIAS (V)
VDD−ON (V)
18
16
15
5.0
4.8
4.6
14
4.4
13
4.2
4.0
12
−40 −20
0
20
40
60
80
100
120
−40 −20
140
40
60
80
100
Figure 3. VDD−ON vs. Temperature
Figure 4. VBIAS vs. Temperature
1.40
8.75
1.35
120
140
1.30
VCS−HIGH−CL (V)
8.25
8.00
7.75
7.50
7.25
7.00
1.25
1.20
1.15
1.10
1.05
6.75
6.50
1.00
−40 −20
0
20
40
60
80
100
−40 −20
120 140
TJ, JUNCTION TEMPERATURE (5C)
80 100 120 140
0
20
40 60
TJ, JUNCTION TEMPERATURE (5C)
Figure 6. VCS−HIGH−CL vs. Temperature
Figure 5. VDD−OFF vs. Temperature
3.60
2.00
3.58
1.95
3.56
1.90
VCS−OCP (V)
3.54
VREF (V)
20
TJ, JUNCTION TEMPERATURE (5C)
9.00
3.52
3.50
3.48
3.46
1.85
1.80
1.75
3.44
1.70
3.42
1.65
3.40
−40
0
TJ, JUNCTION TEMPERATURE (5C)
8.50
VDD−OFF (V))
5.2
−20
40
60
80 100 120
0
20
TJ, JUNCTION TEMPERATURE (5C)
1.60
−40 −20
140
Figure 7. VREF vs. Temperature
0
20
40
60 80 100 120 140
TJ, JUNCTION TEMPERATURE (5C)
Figure 8. VCS−OCP vs. Temperature
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7
FL7740
1.0
10.5
0.8
10.4
0.6
10.3
0.4
10.2
VOV−REF3 (%)
CVREGULATION (%)
TYPICAL CHARACTERISTICS (continued)
0.2
10.1
0.0
10.0
−0.2
−0.4
9.9
9.8
−0.6
9.7
−0.8
9.6
−1.0
−40
−20
0
20
40
60
80 100 120
TJ, JUNCTION TEMPERATURE (5C)
9.5
−40 −20
140
Figure 9. CVREGULATIO N vs. Temperature
−2.10
3.45
3.30
−2.25
3.15
−2.55
VUV−REF1 (%)
VOV−REF1 (%)
−2.40
3.00
−2.70
2.85
−2.85
2.70
−3.00
2.55
−3.15
2.40
−3.30
2.25
−3.45
−20
0
20
40
60
80
100
120
−3.60
−40 −20
140
TJ, JUNCTION TEMPERATURE (5C)
6.2
−5.2
6.1
−5.3
6.0
−5.4
5.9
−5.5
5.8
5.7
5.6
5.5
120 140
−5.6
−5.7
−5.8
−5.9
5.4
−6.0
5.3
−6.1
−20
0
20
40
60
80 100
TJ, JUNCTION TEMPERATURE (5C)
Figure 12. VUV−REF1 vs. Temperature
VUV−REF2 (%)
VOV−REF2 (%)
Figure 11. VOV−REF1 vs. Temperature
5.2
−40
140
Figure 10. VOV−REF3 vs. Temperature
3.60
2.10
−40
40
60
80 100 120
0
20
TJ, JUNCTION TEMPERATURE (5C)
0
20
40
60
80 100 120 140
TJ, JUNCTION TEMPERATURE (5C)
−6.2
−40
Figure 13. VOV−REF2 vs. Temperature
−20
0
20
40
60
80 100 120 140
TJ, JUNCTION TEMPERATURE (5C)
Figure 14. VUV−REF2 vs. Temperature
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FL7740
APPLICATION INFORMATION
General
sophisticated digital PF optimizer, FL7740 significantly
improves power factor in the wide load range.
FL7740 is high power factor flyback controller with
accurate primary side constant voltage regulation for smart
LED lighting and ac−dc adapter, TV & monitors application.
Precise output voltage detection and dynamic function
manage good CV regulation. Startup is fast with internal HV
biasing circuit with overshoot−less gain control. It
guarantees high system reliable protection functions such as
output over voltage, output short, over load, over current and
thermal shut down protections.
Pulse−By−Pulse Current Limit
When CS pin voltage reaches to 1.2 V current limit
reference, GATE turn−on is terminated to limit primary peak
current.
Auto Restart at Protection
Once protection is triggered, IC operation stops for 3 sec
and begin the operation for auto restart.
Constant Voltage Regulation
Output Short Protection
VS pin detects output voltage information (= VEAV)
during secondary side diode conduction time and internal
gm amplifier regulates the detected voltage at 3.5 V.
When VEAV is less than 0.7 V continuously for 35 ms,
output short protection is triggered.
Output Over Voltage Protection
Dynamic Response at Load Transient
When VEAV is higher than VVS−OVP threshold or VDD is
higher than VDD−OVP, output over voltage protection is
triggered.
At load transient condition, VEAV is shortly out of
regulation due to the narrow PFC loop bandwidth. When
VEAV is far from 3.5 V regulation reference, duty is quickly
changed to bring the VEAV back to 3.5 V by dynamic control
function.
Output Diode Short Protection
Once output diode is short circuited, high di/dt in the
primary winding is occurred by leakage inductance. Once
CS pin voltage reaches to 1.7 V, switching is shut down.
HV Biasing at Startup
Internal HV biasing circuit quickly charges external VDD
capacitor to begin IC operation at plug−in. After 500 ms
initial time, HV biasing stops for low standby power.
Sensing Resistor Short Protection
At first switching, sensing resistor short condition is
monitored by detecting CS pin voltage. If CS is less
than 75 mV during first GATE turn−on time, sensing
resistor short protection is triggered.
Overshoot−Less Gain Control at Startup
Once IC operation starts, feedback loop is dominantly
controlled in proportional gain to speed up the output
capacitor charging. Once output voltage is settled down
close to the regulation target, gain control is smoothly
changed to integration gain with no output voltage
overshoot.
When output is over loaded, pulse−by−pulse current limit
event is occurred. If this event lasts for 60 half line cycles,
over load protection is triggered.
Digital PF Optimizer
Thermal Shut Down
Over Load Protection
FL7740 compensates input current phase shift caused by
EMI filter capacitor current in a half line period. With
If internal junction temperature is higher than 150°C,
protection is triggered and released with 30°C hysteresis.
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FL7740
Primary Side Constant Voltage Regulation
during startup sequence (SS1 + SS2) by using internal
resistive load at the output of the error amplifier.
In SS1, CCM prevent operation is enabled for the initial
2 ms. When output voltage is 0 V, deep CCM could be
entered at initial startup and CS could touch OCP level with
startup failure. So, pulse−by−pulse current limit is 0.2 V and
switching frequency is 22 kHz during the 2 ms CCM prevent
time. Also, duty is gradually increased for 26 ms for soft
startup. Once 5 V pulled−up COMV voltage drops less than
4.5 V as VEAV is close to VREF, SS1 is ended. Maximum SS1
time is limited up to 100 ms.
In SS2, VCOMV drops from 5 V and goes into p−gain
steady state in which VEAV is little bit lower than VREF due
to the error amplifier input error in p−gain. Once p−gain
steady state is settled down in 45 ms, SS2 is finished at min.
VCOMV range not to make overshoot when transitioning to
i−gain after SS2. FL7740 ends SS2 by monitoring VIN
1.5 ms after VIN.PK detection moment where VCOMV is
generally in the min range.
FL7740 utilizes auxiliary winding to detect output voltage
during secondary side diode conduction time (= TDIS). The
true output voltage level without secondary diode forward
voltage drop is at the end of secondary diode conduction
time. In order to detect the right output voltage, 85% of TDIS
at previous switching cycle is sampling time for VEAV
detection at current switching cycle.
TDIS
detection
NAUX
VS
Error
Amp.
VREF
S/H
VEAV
COMV
VIN.PK
Duty
Control
Figure 15. Primary Side Regulation
VIN.PK
VIN
GATE
1.5 ms
VCOMV
5.0 V
4.5 V
26 ms soft start
Duty
VEAV sampling
VS
VEAV
2 ms CCM prevent
85% TDIS
at previous
switching
VREF
45 ms
SS1
SS2
Startup time by P−gain
I−gain
Figure 17. Start up sequnce
TDIS
Figure 16. VEAV Detection
Dynamic CV Regulation
Due to the narrow loop bandwidth, PFC controller
generally does not guarantee good CV regulation at load
transient. Especially in secondary side regulation, primary
side controller does not know the output voltage level and it
only monitors the output of feedback signal through
opto−coupler. Therefore, output voltage undershoot is
severely happened at no to full load transient in the
conventional SSR PFC control.
In order to overcome this, FL7740 utilizes the benefit of
PSR with onsemi’s proprietary dynamic duty control by
monitoring the output voltage. For example, when VEAV is
less than VUVD.EN (Under Voltage Dynamic Enable
threshold), duty is quickly increased not to allow undershoot
anymore. Once VEAV rises higher than VUVD.DIS (Under
Voltage Dynamic Disable threshold), duty quickly drops
and follows COMV voltage. During the VEAV hiccup
operation, COMV voltage slowly increases and dynamic
operation is terminated when COMV voltage is close to
steady state level.
The sampled VEAV is compared with 3.5 V VREF at the
input of the error amplifier. Several hundreds nF capacitor
is connected to the output of the error amplifier at COMV
pin to keep feedback loop slow in PFC control. COMV
voltage controls duty to regulate VEAV same as VREF in the
system.
Turn−on time is controlled by both COMV voltage and
VIN.PK information in line feedforward operation in order to
keep the constant COMV voltage in the wide input voltage
range. So, turn−on time is proportional to COMV voltage
and inversely proportional to VIN.PK.
Startup
After plug−in, external VDD capacitor is quickly charged
by internal HV biasing supply. Even after VDD is higher
than 16 V VDD−ON, internal HV biasing is still enabled for
500 ms, so HV biasing can relieve VDD capacitor
discharging until auxiliary winding builds up VDD voltage.
In order to speed up large output capacitor charging
without overshoot, FL7740 starts with proportional gain
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10
FL7740
V EAV
COMV
VOVD .EN 2
VREF
Duty
Generator
VEAV
GATE
VOVD .EN 1
GM amp.
V OVD . DIS
VOVD.EN2
VREF
VOVD.EN1
VCOMV
Over
Voltage
Dynamic
(OVD)
VOVD.DIS
Duty
VUVD.EN
VUVD.DIS
Figure 20. Full to No Load Transient
Under
Voltage
Dynamic
(UVD)
In case of OVD (Over Voltage Dynamic) function, it has
two enable levels (VOVD.EN1 and VOVD.EN2). If output
voltage overshoot at load transient is too high, VEAV
increases to VOVD.EN2 passing by VOVD.EN1. Duty quickly
drops when reaching VOVD.EN1 and drops to min. level at
once not to allow severe output over voltage when VEAV
increases higher than VOVD.EN2.
FL7740 provides two sets of dynamic triggering
threshold. When user prefers narrow output voltage
variation at load transient with large output capacitor, SET0
can be selected without capacitor at PF pin. If wider output
voltage variation is allowed and output capacitor should be
small due to system size, SET1 can be selected with
connection of capacitor around 0.5 nF at PF pin. FL7740
detects capacitance at PF pin at the beginning of switching
startup and maintains the SET# until UVLO is triggered.
During the 1st switching, PF pin is pulled down to 0 V. In the
2nd switching, PF pull down is disabled and PF voltage is
monitored 5 s after 2nd switching period begins. If the PF
voltage is higher than 0.8 V VDYN−REF−SET, SET0 is
decided. If not, SET1 is determined.
Figure 18. Dynamic Function Block
V EAV
VREF
V UVD . DIS
VUVD .EN
VCOMV
Duty
Figure 19. No to Full Load Transient
Table 1. DYNAMIC THRESHOLD AT SET0 AND SET1
VVS.OVP
VOV−REF5 + 20% VREF
SET1
VOV−REF4 + 15% VREF
SET0
VOV−REF3 + 10% VREF
VOVD.EN2
VOVD.EN1
VOVD.DIS
VUVD.DIS
VUVD.EN
SET1
SET0
SET1
VOV−REF2 + 5.7% VREF
SET0
VOV−REF1 + 2.9% VREF
SET1
SET0
VUV−REF1 − 2.9% VREF
SET0
VUV−REF2 − 5.7% VREF
SET1
VUV−REF3 − 10% VREF
SET0
SET1
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FL7740
Digital PF Optimizer
As VPF increases, the coefficient in the PF optimizer
calculation is larger with better PF, but THD is worse due to
the input current distortion at input voltage zero cross.
Therefore, VPF adjustment by changing PF resistors is
recommended to bring the best PF and THD performance to
meet user’s target. When VPF is lower than 1.5 V, PF
optimizer is disabled.
As line voltage increases and output load decreases, PF is
degraded due to the effect of EMI filter capacitor
charging/discharging current. Input current is the sum of
EMI Filter capacitor current and flyback input current.
Whether the flyback input current is exactly in−phase
sinusoidal current with line voltage, 90° phase shifted EMI
filter cap current worsens displacement factor of the overall
system input current.
The onsemi‘s proprietary PF optimizer accurately
compensates the EMI filter capacitor current and improves
PF more than 0.1 at high line and half load condition.
The calculation coefficient in the PF optimizer is
externally programmable by supplying a certain level of
voltage at PF pin with external resistive divider from 5 V
BIAS pin. Before 1st switching, FL7740 converts the PF
voltage into digital value without switching noise and keeps
the digital value for the coefficient until UVLO is triggered.
Protection
• Auto−restart:
Once protection is triggered, FL7740 terminates
switching and internal 3 sec counter makes delay time. In
3 sec, VDD voltage is regulated between 17 V and 19 V
by internal HV biasing not to fall in UVLO. After 3 sec,
VDD falls down to 7.75 V VDD−OFF and IC is reset with
released protection. When VDD voltage is up again to
16 V VDD−ON, FL7740 begins startup sequence.
VDD regulation
for 3 sec
VDD
19 V
17 V
16 V
VIN
IFLYBACK
7.75 V
IIN
GATE
Ideal IIN
IEMI.CAP
Protection
triggered
IC
reset
IC
restart
Figure 23. Auto Restart
GATE
TON
• Output Over Voltage Protection:
Figure 21. With PF Optimizer
VIN
IFLYBACK
•
IIN
Ideal IIN
•
IEMI.CAP
GATE
TON
•
Figure 22. With PF Optimizer
Recommended VPF is in Equation 1, where LM is
magnetizing inductance and CEMI is total EMI filter
capacitance.
V PF + 5
10 9
LM
C EMI ) 1.5
•
(eq. 1)
Output over voltage is hardly triggered due to the
powering limit by dynamic function. But, in the abnormal
condition, output OVP is triggered when VEAV is higher
than 4.0 V @ SET0 / 4.2 V @ SET1 for 4 switching cycles
or VDD voltage is higher than 25 V for 10 s delay.
Output Short Protection:
At output short condition, VEAV is less than 0.7 V. If this
condition lasts for continuous 35 ms switching time, OSP
is triggered.
Over Current Protection:
When CS voltage is higher than 1.8 V over the 1.2 V
pulse−by−pulse current limit, protection is immediately
triggered. OCP protects output diode short, sensing
resistor open and transformer saturation condition.
Sensing Resistor Short Protection:
1st switching is 0.2 V current mode. If CS doesnt reach
over 75 mV threshold during 1st turn−on time, SRSP is
triggered. Max. turn−on time at 1st switching is inversely
proportional to input voltage to limit the primary peak
current.
Over Load Protection:
At over load condition, CS reaches to 1.2 V pulse−by−
pulse current limit. FL7740 generates internal ZC (Zero
www.onsemi.com
12
FL7740
• Thermal Shut Down:
Cross) signal and OLP is triggered if the event (1.2 V
current limit event between the two close ZC signals) is
occurred for consecutive 60 ZC signals.
When internal junction temperature is higher than 150°C,
TSD is triggered and protection is released when the
junction temperature drops under 120°C.
VIN
1.2 V
current limit
event
CS
ZC
OLP Count 0
0
3
2
1
60
59
58
57
OLP
Figure 24. Over Load Protection
AC Input
Bridge
diode
Secondary
DC−DC
Converter
Dimming
Signal
R HV1
PG
(Power GND)
PG line goes
under RHV 1
R HV2
MCU
module
R HV3
SG line goes
under RHV 3
FL7740
HV
NC
VDD
3
COMV
4
GND
2
1
GATE
BIAS
CS
PF
VS
1
G−GATE and S−GND distance should be short.
2
SG and PG are connected close at GND pin.
3
COMV,BIAS,PF,VS circuit ground and aux. winding
VDD circuit ground are connected close at GND pin
.
4
SMD filter cap is connected close at VDD and GND pin.
5
Powering lines (Drain and PG) are closely placed and
away from FL7740 control circuits
.
RGATE
CS line goes
under RGATE
G
D
S
SG
(Signal GND)
5
VDD line goes
under RHV 2
Figure 25. Single Layer PCB Layout Guidance
ORDERING INFORMATION
Product Number
Package
Shipping†
FL7740MX
10 Lead SOIC, JDEC MS−012, 150” Narrow Body
(Pb−Free)
2500 / Tape and Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC10, 4.9x6.0, 1.0P
CASE 751EE
ISSUE A
DATE 28 MAY 2019
GENERIC
MARKING DIAGRAM*
XXXXXXXXX
ALYWX
XXXX
A
L
Y
W
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13738G
SOIC10, 4.9x6.0, 1.0P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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