MOSFET – P-Channel, QFET)
-200 V, -11.5 A, 470 mW
FQB12P20
General Description
These P−Channel enhancement mode power field effect transistors
are produced using ON Semiconductor’s proprietary, planar stripe,
DMOS technology.
This advanced technology has been especially tailored to minimize
on−state resistance, provide superior switching performance, and
withstand high energy pulse in the avalanche and commutation mode.
These devices are well suited for high efficiency switching DC/DC
converters.
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VDSS
RDS(ON) MAX
ID MAX
−200 V
0.47 @ −10 V
−11.5 A
S
Features
•
•
•
•
•
•
•
G
−11.5 A, −200 V, RDS(on) = 0.47 @ VGS = −10 V
Low Gate Charge (Typical 31 nC)
Low Crss (typical 30 pF)
Fast Switching
100% Avalanche Tested
Improved dv/dt Capability
These Devices are Pb−Free and are RoHS Compliant
D
P−CHANNEL MOSFET
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
VDSS
ID
IDM
VGSS
Parameter
FQB12P20
Unit
Drain−Source Voltage
−200
V
Drain Current − Continuous (TC = 25°C)
− Continuous (TC = 100°C)
−11.5
A
−7.27
A
Drain Current − Pulsed (Note 1)
−46
A
Gate−Source Voltage
+30
V
810
mJ
−11.5
A
EAS
Single Pulsed Avalanche Energy (Note 2)
IAR
Avalanche Current (Note 1)
EAR
Repetitive Avalanche Energy (Note 1)
12
mJ
dv/dt
Peak Diode Recovery dv/dt (Note 3)
−5.5
V/ns
Power Dissipation (TA = 25°C) *
3.13
W
Power Dissipation (TC = 25°C)
− Derate above 25°C
120
W
0.96
W/°C
−55 to +150
°C
300
°C
PD
TJ, TSTG
TL
Operating and Storage Temperature
Range
Maximum lead temperature for soldering
purposes, 1/8” from case for 5 seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
*When mounted on the minimum pad size recommended (PCB Mount)
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 9.2 mH, IAS = −11.5 A, VDD = −50 V, RG = 25 , Starting TJ = 25°C
3. ISD ≤ −11.5 A, di/dt ≤ 300 A/s, VDD ≤ BVDSS, Starting TJ = 25°C
© Semiconductor Components Industries, LLC, 2008
December, 2019 − Rev. 2
1
D2PAK−3 (TO−263, 3−LEAD)
CASE 418AJ
MARKING DIAGRAM
$Y&Z&3&K
FQB
12P20
FQB12P20
$Y
&Z
&3
&K
= Specific Device Code
= ON Semiconductor Logo
= Assembly Plant Code
= Digit Date Code
= Lot Run Traceability Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
Publication Order Number:
FQB12P20/D
FQB12P20
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Typ
Max
Unit
RJC
Thermal Resistance, Junction−to−Case
Parameter
−
1.04
°C/W
RJA
Thermal Resistance, Junction−to−Ambient *
−
40
°C/W
RJA
Thermal Resistance, Junction−to−Ambient
−
62.5
°C/W
*When mounted on the minimum pad size recommended (PCB Mount)
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise specified)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BVDSS
Drain−Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
−200
−
−
V
ID = −250 A, Referenced to 25°C
−
−
−
V/°C
VDS = −200 V, VGS = 0 V
−
−
−1
A
VDS = −160 V, TC = 125°C
−
−
−10
A
VGS = 0 V, ID = −250 A
BVDSS / TJ Breakdown Voltage Temperature Coefficient
IGSSF
Gate−Body Leakage Current, Forward
VGS = −30 V, VDS = 0 V
−
−
−100
nA
IGSSR
Gate−Body Leakage Current, Reverse
VGS = 30 V, VDS = 0 V
−
−
100
nA
ON CHARACTERISTICS
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = −250 A
−3.0
−
−5.0
V
RDS(on)
Static Drain−Source On−Resistance
VGS = −10 V, ID = −5.75 A
−
0.36
0.47
Forward Transconductance
VDS = −40 V, ID = −5.75 A (Note 4)
−
6.4
−
S
VDS = −25 V, VGS = 0 V, f = 1.0 MHz
−
920
1200
pF
gFS
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
−
190
250
pF
Crss
Reverse Transfer Capacitance
−
30
40
pF
−
20
50
ns
−
195
400
ns
SWITCHING CHARACTERISTICS
td(on)
Turn−On Delay Time
tr
Turn−On Rise Time
td(off)
VDD = −100 V, ID = −11.5 A,
RG = 25
(Note 4, 5)
Turn−Off Delay Time
−
40
90
ns
tf
Turn−Off Fall Time
−
60
130
ns
Qg
Total Gate Charge
−
31
40
nC
Qgs
Gate−Source Charge
−
8.1
−
nC
Qgd
Gate−Drain Charge
−
16
−
nC
VDS = −160 V, ID = −11.5 A,
VGS = −10 V
(Note 4, 5)
DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUMUM RATINGS
Maximum Continuous Drain−Source Diode Forward Current
−
−
−11.5
A
ISM
Maximum Pulsed Drain−Source Diode Forward Current
−
−
−46
A
VSD
Drain−Source Diode Forward Voltage
VGS = 0 V, IS = −11.5 A
−
−
−5.0
V
trr
Reverse Recovery Time
−
180
−
ns
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = −11.5 A,
dIF / dt = 100 A/s (Note 4)
−
1.44
−
C
IS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: Pulse width ≤ 300 s, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
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2
FQB12P20
TYPICAL CHARACTERISTICS
VGS
−15.0 V
−10.0 V
−8.0 V
−7.0 V
−6.5 V
−6.0 V
Bottom: −5.5 V
101
−ID, Drain Current (A)
−ID, Drain Current (A)
Top:
100
101
150°C
−55°C
100
25°C
Notes:
1. VDS = −40 V
2. 250 s Pulse Test
Notes:
1. 250 s Pulse Test
2. TC = 25°C
10−1
10−1
100
10−1
101
2
4
−VDS, Drain−Source Voltage (V)
10
Figure 2. Transfer Characteristics
2.0
−IDR, Reverse Drain Current (A)
RDS(on), Drain−Source On−Resistance ()
8
−VGS, Gate−Source Voltage (V)
Figure 1. On Characteristics
1.5
VGS = − 10 V
1.0
VGS = − 20 V
0.5
101
100
150°C
Notes:
1. VGS = 0 V
2. 250 s Pulse Test
25°C
Note: TJ = 25°C
0.0
0
10
20
30
10−1
0.0
40
0.5
−ID, Drain Current (A)
2400
2.0
2.5
3.0
12
−VGS, Gate−Source Voltage (V)
1600
Ciss
1200
Coss
800
1.5
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current and Temperature
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
2000
1.0
−VSD, Source−Drain Voltage (V)
Figure 3. On−Resistance Variation vs. Drain Current
and Gate Voltage
Capacitance (pF)
6
Crss
400
VDS = −40 V
10
VDS = −100 V
VDS = −160 V
8
6
4
2
Note: ID = 11.5 A
0
10−1
100
0
101
−VDS, Drain−Source Voltage (V)
0
5
10
15
20
25
30
QG, Total Gate Charge (nC)
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
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3
35
FQB12P20
TYPICAL CHARACTERISTICS (continued)
2.5
RDS(on), (Normalized) Drain−Source
On−Resistance ()
−BVDSS, (Normalized)
Drain−Source Breakdown Voltage
1.2
1.1
1.0
0.9
Notes:
1. VGS = 0 V
2. ID = 250 A
0.8
−100
−50
0
50
100
150
2.0
1.5
1.0
0.5
Notes:
1. VGS = −10 V
2. ID = −5.75 A
0.0
−100
200
−50
0
50
100
150
TJ, Junction Temperature (°C)
TJ, Junction Temperature (°C)
Figure 7. Breakdown Voltage Variation vs.
Temperature
Figure 8. On−Resistance Variation vs.
Temperature
200
12
Operation in This Area
is Limited by RDS(on)
−ID, Drain Current (A)
10
100 s
1 ms
101
10 ms
DC
100
Notes:
1. TC = 25°C
2. TJ = 150°C
3. Single Pulse
10−1
100
8
6
4
2
101
0
102
25
50
75
100
125
−VDS, Drain−Source Voltage (V)
TC, Case Temperature (°C)
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current vs.
Case Temperature
100
ZJC (t), Thermal Response
ID, Drain Current (A)
102
D = 0.5
0.2
10−1
Notes:
1. ZJC (t) = 1.04°C/W Max.
2. Duty Factor, D = t1 / t2
3. TJM − TC = PDM * ZJC (t)
0.1
0.05
0.02
P DM
0.01
single pulse
t1
10−2
10−5
10−4
10−3
10−2
10−1
t1, Square Wave Pulse Duration (s)
Figure 11. Capacitance Characteristics
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4
t2
100
101
150
FQB12P20
12 V
200 nF
V GS
Same Type
as DUT
50 k
Qg
−10 V
300 nF
V DS
V GS
Q gs
Q gd
DUT
−3 mA
Charge
Figure 12. Gate Charge Test Circuit & Waveform
VDS
RG
RL
V DD
VGS
t on
td(on)
VGS
t off
tr
t d(off)
tf
10%
DUT
−10 V
VDS
90%
Figure 13. Resistive Switching Test Circuit & Waveforms
L
E AS +
VDS
tp
ID
RG
VDD
DUT
−10 V
BV DSS
1 2
LI
2 AS BV DSS * V DD
VDD
VDS (t)
ID (t)
IAS
tp
BVDSS
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
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5
Time
FQB12P20
+
VDS
DUT
_
I SD
L
Driver
RG
Compliment of DUT
(N−Channel)
VGS
VGS
(Driver)
VDD
S dv/dt controlled by RG
S ISD controlled by pulse period
D=
Gate Pulse Width
Gate Pulse Period
10 V
Body Diode Reverse Current
ISD
IRM
(DUT)
di/dt
IFM , Body Diode Forward Current
VSD
VDS
(DUT)
Body Diode
Forward Voltage Drop
VDD
Body Diode Recovery dv/dt
Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
PACKAGE MARKING AND ORDERING INFORMATION
Device
FQB12P20TM
Marking
Package
Reel Size
Tape Width
Shipping†
FQB12P20
D2PAK
(Pb−Free)
330 mm
24 mm
800 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
QFET is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK−3 (TO−263, 3−LEAD)
CASE 418AJ
ISSUE F
SCALE 1:1
GENERIC MARKING DIAGRAMS*
XX
XXXXXXXXX
AWLYWWG
IC
DOCUMENT NUMBER:
DESCRIPTION:
XXXXXXXXG
AYWW
Standard
98AON56370E
AYWW
XXXXXXXXG
AKA
Rectifier
XXXXXX
XXYMW
SSG
DATE 11 MAR 2021
XXXXXX = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
W
= Week Code (SSG)
M
= Month Code (SSG)
G
= Pb−Free Package
AKA
= Polarity Indicator
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
D2PAK−3 (TO−263, 3−LEAD)
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