FQD3P50TM-AM002BLT

MOSFET – P-Channel, QFET) FQD3P50 -500 V, 4.9 W, -2.1 A Description www.onsemi.com This P−Channel enhancement mode power MOSFET is produced using ON Semiconductor’s proprietary planar stripe and DMOS technology. This advanced MOSFET technology has been especially tailored to reduce on−state resistance, and to provide superior switching performance and high avalanche energy strength. These devices are suitable for switched mode power supplies, active power factor correction (PFC), and electronic lamp ballasts. D G S DPAK3 CASE 369AS Features • −2.1 A, −500 V, RDS(on) = 4.9 W (Max.) @ VGS = −10 V, • • • • S ID = −1.05 A Low Gate Charge (Typ. 18 nC) Low Crss (Typ. 9.5 pF) 100% Avalanche Tested These Devices are Pb−Free and are RoHS Compliant G D ABSOLUTE MAXIMUM RATINGS (TC = 20°C unless otherwise noted) Symbol Value Unit Drain−Source Voltage −500 V Drain Current − Continuous (TC = 25°C) − Continuous (TC = 100°C) −2.1 −1.33 Drain Current − Pulsed (Note 1) −8.4 A Gate−Source Voltage ±30 V EAS Single Pulsed Avalanche Energy (Note 2) 250 mJ IAR Avalanche Current (Note 1) −2.1 A EAR Repetitive Avalanche Energy (Note 1) 5.0 mJ dv/dt Peak Diode Recovery dv/dt (Note 3) −4.5 V/ns Power Dissipation (TA = 25°C) (Note 4) 2.5 W Power Dissipation (TC = 25°C) − Derate above 25°C 50 0.4 W W/°C −55 to +150 °C VDSS ID IDM VGSS PD TJ, TSTG TL Parameter Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8″ from case for 5 seconds A September, 2019 − Rev. 4 $Y&Z&3&K FQD 3P50 $Y &Z &3 &K FQD3P50 = ON Semiconductor Logo = Assembly Code = Date Code (Year and Week) = Lot Code = Specific Device Code ORDERING INFORMATION °C 300 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Repetitive Rating: Pulse width limited by maximum junction temperature. 2. L = 102 mH, IAS = −2.1 A, VDD = −50 V, RG = 25 W, Starting TJ = 25°C. 3. ISD ≤ −2.7 A, di/dt ≤ 200 A/ms, VDD ≤ BVDSS, Starting TJ = 25°C. 4. When mounted on the minimum pad size recommended (PCB Mount). © Semiconductor Components Industries, LLC, 2009 MARKING DIAGRAM 1 Device FQD3P50 Package Shipping† DPAK3 (Pb−Free) 2,500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: FQD3P50/D FQD3P50 THERMAL CHARACTERISTICS Symbol Parameter FQD3P50 Unit RθJC Thermal Resistance, Junction−to−Case, Max. 2.5 °C/W RθJA Thermal Resistance, Junction−to−Ambient, Max. (Note 5) 50 °C/W RθJA Thermal Resistance, Junction−to−Ambient, Max. 110 °C/W 5. When mounted on the minimum pad size recommended (PCB Mount). ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Symbol Characteristic Test Conditions Min Typ Max Unit OFF CHARACTERISTICS BVDSS DBVDSS/DTJ IDSS Drain−Source Breakdown Voltage VGS = 0 V, ID = −250 mA −500 − − V Breakdown Voltage Temperature Coef- ID = −250 mA, Referenced to 25°C ficient − 0.42 − V/°C Zero Gate Voltage Drain Current VDS = −500 V, VGS = 0 V − − −1 mA VDS = −400 V, TC = 125°C − − −10 mA VGS = −30 V, VDS = 0 V − − −100 nA − − 100 nA IGSSF Gate−Body Leakage Current, Forward IGSSR Gate−Body Leakage Current, Reverse VGS = 30 V, VDS = 0 V ON CHARACTERISTICS VGS(th) Gate Threshold Voltage VDS = VGS, ID = −250 mA −3.0 − −5.0 V RDS(on) Static Drain−Source On−Resistance VGS = −10 V, ID = −1.05 A − 3.9 4.9 W Forward Transconductance VDS = −50 V, ID = −1.05 A − 2.1 − S VDS = −25 V, VGS = 0 V, f = 1.0 MHz − 510 660 pF gFS DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance − 70 90 pF Crss Reverse Transfer Capacitance − 9.5 12 pF − 12 35 ns − 56 120 ns ns SWITCHING CHARACTERISTICS td(on) Turn−On Delay Time tr Turn−On Rise Time td(off) VDD = −250 V, ID = −2.7 A, RG = 25 W (Note 6) Turn−Off Delay Time − 35 80 tf Turn−Off Fall Time − 45 100 ns Qg Total Gate Charge − 18 23 nC Qgs Gate−Source Charge − 3.6 − nC Qgd Gate−Drain Charge − 9.2 − nC Maximum Continuous Drain−Source Diode Forward Current − − −2.1 A Maximum Pulsed Drain−Source Diode Forward Current VDS = −400 V, ID = −2.7 A, VGS = −10 V (Note 6) DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS ISM VSD Drain−Source Diode Forward Voltage VGS = 0 V, IS = −2.1 A trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = −2.7 A, dIF / dt = 100 A/ms − − −8.4 A − − −5.0 V − 270 − ns − 1.5 − mC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Essentially independent of operating temperature. www.onsemi.com 2 FQD3P50 TYPICAL PERFORMANCE CURVES VGS −15.0 V −10.0 V −8.0 V −7.0 V −6.5 V −6.0 V Bottom: −5.5 V 1 −ID, DRAIN CURRENT (A) −ID, DRAIN CURRENT (A) Top: 0.1 Notes: 1. 250 ms Pulse Test 2. TC = 25°C 150°C 1 25°C −55°C 0.1 0.01 1 0.1 4 2 10 Figure 1. On−Region Characteristics −IDR, REVERSE DRAIN CURRENT (A) RDS(on), DRAIN SOURCE ON−RESISTANCE (W) 7 VGS = −10 V 6 VGS = −20 V 5 4 2 Note: 1. TJ = 25°C 2 0 4 6 8 0.1 0.5 0.0 −VGS, GATE−SOURCE VOLTAGE (V) Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 800 C iss 600 C oss Notes: 1. VGS = 0 V 2. f = 1 MHz 0 0.1 C rss 1 1.0 Notes: 1. VGS = 0 v 2. 250 ms Pulse Test 1.5 2.0 2.5 3.0 Figure 4. Body Diode Forward Voltage Variant vs. Source Current and Temperature 1200 200 25°C 150°C −VSD, SOURCE−DRAIN VOLTAGE (V) Figure 3. On−Resistance Variation vs. Drain Current and Gate Voltage 400 10 1 −ID, DRAIN CURRENT (A) 1000 8 Figure 2. Transfer Characteristics 8 3 6 −VGS, GATE−SOURCE VOLTAGE (V) −VDS, DRAIN−SOURCE VOLTAGE (V) CAPACITANCE (pF) Notes: 1. VDS = 50 V 2. 250 ms Pulse Test 10 12 VDS = −100 V 10 VDS = −250 V 8 VDS = −400 V 6 4 2 Note: ID = −2.7 A 0 0 2 4 6 8 10 12 14 16 QG, TOTAL GATE CHARGE (nC) −VDS, DRAIN−SOURCE VOLTAGE (V) Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics www.onsemi.com 3 18 20 FQD3P50 −BVDSS, (NORMALIZED) DRAIN−SOURCE BREAKDWON VOLTAGE TYPICAL PERFORMANCE CURVES (CONTINUED) 1.2 RDS(on), (NORMALIZED) DRAIN−SOURCE ON−RESISTANCE 2.5 2.0 1.1 1.5 1.0 1.0 Notes: 1. VGS = 0 V 2. ID = −250 mA 0.9 0.8 −100 −50 0 50 100 150 Notes: 1. VGS = −10 V 2. ID = −1.35 A 0.5 0.0 −100 200 −50 0 50 100 150 200 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On−Resistance Variation vs. Temperature −ID, DRAIN CURRENT (A) 10 100 μ s 1 ms 10 ms 1 DC Notes: 1. TC = 25°C 2. TJ = 150°C 3. Single Pulse 0.1 0.01 10 1 100 1000 2.0 1.5 1.0 0.5 0.0 50 25 TJ, JUNCTION TEMPERATURE (°C) 1 75 100 Figure 10. Maximum Drain Current vs. Case Temperature D=0.5 Notes: 1. ZqJC(t) = 2.5°C/W Max. 2. Duty Factor, D = t1/t2 3. TJM − TC = PDM × ZqJC(t) 0.2 0.1 0.05 0.1 0.02 P DM 0.01 t1 single pulse t2 0.01 0.00001 0.0001 0.001 125 TC, CASE TEMPERATURE (°C) Figure 9. Maximum Safe Operation Area ZqJC, THERMAL RESPONSE −ID, DRAIN CURRENT (A) 2.5 Operation in This Area is Limited by RDS(on) 0.01 0.1 1 t1, SQUARE WAVE PULSE DURATION (s) Figure 11. Transient Thermal Response Curve www.onsemi.com 4 10 150 FQD3P50 50 kW 200 nF Same Type as DUT VGS Qg 300 nF −10 V VDS VGS Qgs Qgd DUT −3 mA Charge Figure 12. Gate Charge Test Circuit & Waveform RL VDS VDS 90% 90% 90% VDD VGS RG VGS DUT −10 V 10% td(on) 10% tr tf td(off) ton toff Figure 13. Resistive Switching Test Circuit & Waveforms L BV DSS 2 E AS + 1 @ LI AS @ 2 BV DSS * V DD VDS tp ID RG VDD VDS(t) VDD ID(t) DUT −10 V IAS tp BVDSS Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms www.onsemi.com 5 Time FQD3P50 + VDS DUT − ISD L Driver RG Same Type as DUT VDD VGS VGS (Driver) − dv/dt controlled by RG − ISD controlled by pulse period D+ Gate Pulse Width 10 V Gate Pulse Period Body Diode Reverse Current ISD (DUT) IRM di/dt IFM, Body Diode Forward Current VSD VDS (DUT) Body Diode Forward Voltage Drop VDD Body Diode Recovery dv/dt Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms QFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK3 (TO−252 3 LD) CASE 369AS ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON13810G DPAK3 (TO−252 3 LD) DATE 30 SEP 2016 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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