FS6377
Programmable 3-PLL Clock Generator IC
1.0 Key Features
•
•
•
•
•
•
•
•
•
Three on-chip PLLs with programmable reference and feedback dividers
Four independently programmable muxes and post dividers
I2C™-bus serial interface
Programmable power-down of all PLLs and output clock drivers
One PLL and two mux/post-divider combinations can be modified by SEL_CD input
Tristate outputs for board testing
5V to 3.3V operation
Accepts 5MHz to 27MHz crystal resonators
Commercial and industrial temperature ranges offered
2.0 General Description
The FS6377 is a CMOS clock generator IC designed to minimize cost and component count in a variety of electronic systems. Three
2
I C-programmable phase locked loops (PLLs) feeding four programmable muxes and post dividers provide a high degree of flexibility.
Figure 1: Pin Configuration
©2008 SCILLC. All rights reserved.
May 2008 – Rev. 4
Publication Order Number:
FS6377/D
FS6377
Figure 2: Block Diagram
Table 1: Pin Descriptions
Pin
Type
Name
Description
U
SDA
Serial interface data input/output
SEL_CD
Selects one of two PLL C, mux D/C and post divider C/D combinations
PD
Power-down input
VSS
Ground
1
DI O
2
DI
U
3
DI
U
4
P
5
AI
XIN
Crystal oscillator input
6
AO
XOUT
Crystal oscillator output
7
DI
8
P
9
DI
10
DO
U
U
OE
Output enable input
VDD
Power supply (5V to 3.3V)
ADDR
Address select
CLK_D
D clock output
11
P
VSS
Ground
12
DO
CLK_C
C clock output
13
DO
CLK_B
B clock output
14
P
VDD
Power supply (5V to 3.3V)
15
DO
16
DI
U
CLK_A
A clock output
SCL
Serial interface clock output
Key: AI: Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-up; DID = Input with Internal Pull-down; DIO = Digital Input/Output;
DI-3 = Three-level Digital Input; DO = Digital Output; P = Power/Ground; # = Active Low Pin
Rev. 4 | Page 2 of 24 | www.onsemi.com
FS6377
3.0 Functional Block Description
3.1 Phase Locked Loops (PLLs)
Each of the three on-chip PLLs is a standard phase- and frequency-locked loop architecture that multiplies a reference frequency to a
desired frequency by a ratio of integers. This frequency multiplication is exact.
As shown in Figure 3, each PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop
filter, a voltage-controlled oscillator (VCO), and a feedback divider.
During operation, the reference frequency (fREF), generated by the on-board crystal oscillator, is first reduced by the reference divider.
The divider value is called the "modulus," and is denoted as NR for the reference divider. The divided reference is then fed into the PFD.
The PFD controls the frequency of the VCO (fVCO) through the charge pump and loop filter. The VCO provides a high speed, low noise,
continuously variable frequency clock source for the PLL. The output of the VCO is fed back to the PFD through the feedback divider
(the modulus is denoted by NF) to close the loop.
The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at
the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is:
Figure 3: PLL Diagram
3.1.1. Reference Divider
The reference divider is designed for low phase jitter. The divider accepts the output of the reference oscillator and provides a divideddown frequency to the PFD. The reference divider is an 8-bit divider, and can be programmed for any modulus from 1 to 255 by
programming the equivalent binary value. A divide-by-256 can also be achieved by programming the eight bits to 00h.
3.1.2. Feedback Divider
The feedback divider is based on a dual-modulus prescaler technique. The technique allows the same granularity as a fully
programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also
called a prescaler) is placed between the VCO and the programmable feedback divider because of the high speeds at which the VCO
can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall
power consumption of the divider.
Rev. 4 | Page 3 of 24 | www.onsemi.com
FS6377
For example, a fixed divide-by-eight could be used in the feedback divider. Unfortunately, a divide-by-eight would limit the effective
modulus of the entire feedback divider to multiples of eight. This limitation would restrict the ability of the PLL to achieve a desired inputfrequency-to-output frequency ratio without making both the reference and feedback divider values comparatively large.
A large feedback modulus means that the divided VCO frequency is relatively low, requiring a wide loop bandwidth to permit the low
frequencies. A narrow loop bandwidth tuned to high frequencies is essential to minimizing jitter; therefore, divider moduli should always
be as small as possible.
To understand the operation, refer to Figure 4. The M-counter (with a modulus always equal to M) is cascaded with the dual-modulus
prescaler. The A-counter controls the modulus of the prescaler. If the value programmed into the A-counter is A, the prescaler will be
set to divide by N+1 for A prescaler outputs. Thereafter, the prescaler divides by N until the M-counter output resets the A-counter, and
the cycle begins again. Note that N=8 and A and M are binary numbers.
Suppose that the A-counter is programmed to zero. The modulus of the prescaler will always be fixed at N; and the entire modulus of
the feedback divider becomes MxN.
Next, suppose that the A-counter is programmed to a one. This causes the prescaler to switch to a divide-by-N+1 for its first divide
cycle and then revert to a divide-by-N. In effect, the A-counter absorbs (or "swallows") one extra clock during the entire cycle of the
feedback divider. The overall modulus is now seen to be equal to MxN+1.
This example can be extended to show that the feedback divider modulus is equal to MxN+A, where A VDD)
Output clamp current, dc (VI < 0 or VI > VDD)
Storage temperature range (non-condensing)
Ambient temperature range, under bias
Junction temperature
Re-flow solder profile
Input static discharge voltage protection (MIL-STD 883E, Method 3015.7)
Symbol
VDD
V1
VO
IIK
IOK
TS
TA
TJ
Min.
VSS – 0.5
VSS – 0.5
VSS – 0.5
-50
-50
-65
-55
Max.
7
VDD + 0.5
VDD + 0.5
50
50
150
125
150
2
Units
V
V
V
mA
mA
°C
°C
°C
Per IPC/JEDEC J-STD-020B
kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional
operation of the device of these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for
extended conditions may affect device performance, functionality and reliability.
CAUTION: ELETROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic
discharge.
Table 11: Operating Conditions
Parameter
Supply voltage
Symbol
VDD
Ambient operating temperature range
TA
Crystal resonator frequency
Crystal resonator load capacitance
Serial data transfer rate
Output driver load capacitance
fXIN
CXL
Table 12: DC Electrical Specifications
Parameter
Overall
Supply current, dynamic, with load outputs
Conditions/Descriptions
5V ± 10%
3.3V ± 10%
Commercial
Industrial
Parallel resonant, AT cut
Standard mode
Min.
4.5
3
0
-40
5
Typ.
5
3.3
Max.
5.5
3.6
70
85
27
18
10
100
15
CL
Symbol
IDD
Supply current, static
IDDL
Power-Down, Output Enable Pins (PD, OE)
High-level input voltage
VIH
Low-level input voltage
VIL
Hysteresis voltage
Vhys
High-level input current
Low-level input current (pull-up)
Serial Interface I/O (SCL, SDA)
IIH
IIL
High-level input voltage
VIH
Low-level input voltage
VIL
Hysteresis voltage
Vhys
High-level input current
Low-level input current (pull-up)
Low-level output sink current (SDA)
IIH
IIL
IOL
Conditions/Descriptions
Min.
VDD = 5.5V, fCLK = 50MHz, CL = 15pF
See Figure 10 for more information
VDD = 5.5V, device powered down
VDD = 5.5V
VDD = 3.6V
VDD = 5.5V
VDD = 3.6V
VDD = 5.5V
VDD = 3.6V
VIL = 0V
VDD = 5.5V
VDD = 3.6V
VDD = 5.5V
VDD = 3.6V
VDD = 5.5V
VDD = 3.6V
VIL = 0V
VOL = 0.4V, VDD = 5.5V
Rev. 4 | Page 15 of 24 | www.onsemi.com
Units
V
°C
MHz
pF
kb/s
pF
Typ.
Max.
43
mA
0.3
3.85
2.52
VSS - 0.3
VSS - 0.3
-1
-20
3.85
2.52
VSS - 0.3
VSS - 0.3
-1
-20
mA
VDD +0.3
VDD +0.3
1.65
1.08
2.20
1.44
-36
V
V
V
1
-80
VDD +0.3
VDD +0.3
1.65
1.08
2.20
1.44
-36
26
Units
µA
µA
V
V
V
1
-80
µA
µA
mA
FS6377
Table 12: DC Electrical Specifications (continued)
Mode and Frequency Select Inputs (ADDR, SEL_CD)
High-level input voltage
VIH
Low-level input voltage
VIL
High-level input current
Low-level input current (pull-up)
Crystal Oscillator Feedback (XIN)
IIH
IIL
Threshold bias voltage
VTH
IIH
High-level input current
Low-level input current
IIL
Crystal loading capacitance*
CL(xtal)
Input loading capacitance*
CL(XIN)
Crystal Oscillator Driver (XOUT)
High-level output source current
IOH
Low-level output sink current
IOL
Clock Outputs (CLK_A, CLK_B, CLK_C, CLK_D)
High-level output source current
IOH
Low-level output sink current
IOL
ZOH
Output impedance
ZOL
Tristate output current
IZ
Short circuit source current*
ISCH
Short circuit sink current*
ISCL
VDD = 5.5V
VDD = 3.6V
VDD = 5.5V
VDD = 3.6V
2.4
2.0
VSS - 0.3
VSS - 0.3
-1
-20
VDD = 5.5V
VDD = 3.6V
VDD = 5.5V
VDD = 5.5V, oscillator powered down
VDD = 5.5V
As seen by an external crystal
connected to XIN and XOUT
As seen by an external clock driver on
XOUT; XIN unconnected
VDD = V(XIN) = 5.5V, VO = 0V
VDD = 5.5V, V(XIN) = 0V, VO = 5.5V
-36
2.9
1.7
54
5
-25
10
-10
VO = 2.4V
VO = 0.4V
VO = 0.5VDD; output driving high
VO = 0.5VDD; output driving low
-54
V
V
µA
µA
V
15
-75
µA
mA
µA
18
pF
36
pF
21
-21
30
-30
-125
23
29
27
-10
VDD = 5.5V, VO = 0V; shorted for 30s,
max.
VDD = VO = 5.5V; shorted for 30s, max.
VDD +0.3
VDD +0.3
0.8
0.8
1
-80
mA
mA
mA
mA
Ω
10
µA
-150
mA
123
mA
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent
nominal characterization data and are not currently production tested on any specific limits. Min. and max. characterization data are ± 3σ from typical. Negative currents
indicate current flows out of the device.
Low Drive Current (mA)
Voltage
Min.
Typ.
(V)
0
0
0
0.2
9
11
0.5
22
25
0.7
29
34
1
39
46
1.2
44
52
1.5
51
61
1.7
55
66
2
60
73
2.2
62
77
2.5
65
81
2.7
65
83
3
66
85
3.5
67
87
4
68
88
4.5
69
89
5
91
5.5
Max.
0
12
29
40
55
64
76
83
92
97
104
108
112
117
119
120
121
123
High Drive Current (mA)
Voltage
Min.
Typ.
Max.
(V)
0
-87
-112
-150
0.5
-85
-110
-147
1
-83
-108
-144
1.5
-80
-104
-139
2
-74
-97
-131
2.5
-65
-88
-121
2.7
-61
-84
-116
3
-53
-77
-108
3.2
-48
-71
-102
3.5
-39
-62
-92
3.7
-32
-55
-85
4
-21
-44
-74
4.2
-13
-36
-65
4.5
0
-24
-52
4.7
-15
-43
5
0
-28
5.2
-11
5.5
0
The data in this table represents nominal characterization data only.
Figure 9: CLK_A, CLK_B, CLK_C, CLK_D Clock Outputs
Rev. 4 | Page 16 of 24 | www.onsemi.com
FS6377
Figure 10: Dynamic Current vs. Output Frequency
Rev. 4 | Page 17 of 24 | www.onsemi.com
FS6377
Table 13: AC Timing Specifications
Parameter
Symbol
Conditions/Descriptions
Clock
(MHz)
Min.
Typ.
Max.
Units
Overall
Output frequency*
fO
VCO frequency*
fVCO
VCO gain*
Loop filter time constant*
AVCO
Rise time*
tr
Fall time*
tr
Tristate enable delay*
Tristate disable delay*
Clock stabilization time*
tPZL, tPZH
tPZL, tPZH
tSTB
VDD = 5.5V
VDD = 3.6V
VDD = 5.5V
VDD = 3.6V
0.8
0.8
40
40
Jitter, period (peak-peak)*
tj(ΔP)
tj(ΔP)
1
1
Output active from power-up, via PD pin
After last register is written
On rising edges 500µs apart at 2.5V relative to an
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, all other PLLs active (B = 60MHz,
C = 40MHz, D = 14.318MHz)
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, no other PLLs active
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, all other PLLs active (B = 60MHz,
C = 40MHz, D = 14.318MHz)
Clock Outputs (PLL B clock via CLK_B pin) Approximate
Duty cycle*
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
tj(LT)
On rising edges 500µs apart at 2.5V relative to an
Jitter, long term (σy(τ))*
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, no other PLLs active
Jitter, period (peak-peak)*
400
7
20
1.9
1.6
1.8
1.5
LFTC bit = 0
LFTC bit = 1
VO = 0.5V to 4.5V; CL = 15pF
VO = 0.3V to 3.0V; CL = 15pF
VO = 4.5V to 0.5V; CL = 15pF
VO = 3.0V to 0.3V; CL = 15pF
Divider Modulus
Feedback divider
NF
See Table 2
Reference divider
NR
Post divider
NP
See Table 8
Clock Outputs (PLL A clock via CLK_A pin) Approximate
Duty cycle*
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
tj(LT)
On rising edges 500µs apart at 2.5V relative to an
Jitter, long term (σy(τ))*
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, no other PLLs active
On rising edges 500µs apart at 2.5V relative to an
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, all other PLLs active (A = 50MHz,
C = 40MHz, D = 14.318MHz)
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, no other PLLs active
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, all other PLLs active (A = 50MHz,
C = 40MHz, D = 14.318MHz)
Rev. 4 | Page 18 of 24 | www.onsemi.com
150
100
230
170
µs
ns
ns
8
8
1
8
1
1
2047
255
50
45
55
100
45
50
165
100
110
50
390
MHz
MHz/V
100
100
MHz
ns
ns
µs
ms
%
ps
ps
100
45
55
100
45
60
75
100
120
60
400
%
ps
ps
FS6377
Table 13: AC Timing Specifications continued
Clock Outputs (PLL_C clock via CLK_C pin) Approximate
Duty cycle*
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
tj(LT)
On rising edges 500µs apart at 2.5V relative to an
Jitter, long term (σy(τ))*
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, no other PLLs active
Jitter, period (peak-peak)*
tj(ΔP)
On rising edges 500µs apart at 2.5V relative to an
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, all other PLLs active (A = 50MHz,
B = 60MHz, D = 14.318MHz)
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, no other PLLs active
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, all other PLLs active (A = 50MHz,
B = 60MHz, D = 14.318MHz)
Clock Outputs (Crystal Oscillator via CLK_D pin) Approximate
Duty cycle*
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
tj(LT)
On rising edges 500µs apart at 2.5V relative to an
Jitter, long term (σy(τ))*
ideal clock, CL = 15pF, fXIN = 14.318MHz, no other
PLLs active
100
45
55
100
45
40
105
100
120
40
440
%
ps
ps
14.318
45
55
14.318
20
14.318
40
14.318
90
14.318
450
%
ps
Jitter, period (peak-peak)*
tj(ΔP)
From rising edges to the next at 2.5V, CL = 15pF,
fXIN = 14.318MHz, all other PLLs active (A = 50MHz,
B = 60MHz, C = 40MHz)
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, no other PLLs active
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, all other PLLs active
(A = 50MHz, B = 60MHz, C = 40MHz)
ps
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent
nominal characterization data and are not currently production tested to any specific limits. Min. and max. characterization data are ±3σ from typical.
Table 14: Serial Interface Timing Specifications
Parameter
Symbol
Clock frequency
Bus free time between STOP and
START
Set-up time, START (repeated)
Hold time, START
Set-up time, data input
Hold time, data input
fSCL
tsu:STA
tnd:STA
tsu:DAT
thd:DAT
Output data valid from clock
tAA
Rise time, data and clock
Fall time, data and clock
High time, clock
Low time, clock
Set-up time, STOP
tR
tF
tHI
tLO
Tsu:STO
Conditions/Description
SCL
tBUF
SDA
SDA
Minimum delay to bridge undefined region of
the falling edge of SCL to avoid unintended
START or STOP
SDA, SCL
SDA, SCL
SCL
SCL
Standard Mode
Min.
Max.
0
100
4.7
4.7
4.0
250
0
4.0
4.7
4.0
Units
kHz
µs
µs
µs
ns
µs
3.5
µs
1000
300
ns
ns
µs
µs
µs
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*)
represent nominal characterization data and are not currently production tested to any specific limits. Min. and max. characterization data are ±3σ from typical.
Rev. 4 | Page 19 of 24 | www.onsemi.com
FS6377
Figure 11: Bus Timing Data
Figure 12: Data Transfer Sequence
8.0 Package Information – For Both ‘Green’ and ‘No-Green’
Table 15: 16-pin SOIC (0.150") Package Dimensions
Dimensions
Inches
Millimeters
Min.
Max.
Min.
Max.
A
0.061
0.068
1.55
1.73
A1 0.004
0.0098
0.102 0.249
A2 0.055
0.061
1.40
1.55
B
0.013
0.019
0.33
0.49
C
0.0075 0.0098
0.191 0.249
D
0.386
0.393
9.80
9.98
E
0.150
0.157
3.81
3.99
e
0.050 BSC
1.27 BSC
H
0.230
0.244
5.84
6.20
h
0.010
0.016
0.25
0.41
L
0.016
0.035
0.41
0.89
0°
8°
0°
8°
Θ
Rev. 4 | Page 20 of 24 | www.onsemi.com
FS6377
Table 16: 16-pin SOIC (0.150") Package Characteristics
Parameter
Symbol
Conditions/Description
Thermal impedance, junction to freeAir flow = 0m/s
ΘJA
air16-pin 0.150” SOIC
Corner lead
Lead inductance, self
L11
Center lead
Lead inductance, mutual
L12
Any lead to any adjacent lead
Lead capacitance, bulk
C11
Any lead to VSS
Typ.
Units
110
°C/W
4.0
3.0
0.4
0.5
nH
pF
nH
9.0 Ordering Information
Part Number
FS6377-01G-XTD
FS6377-01G-XTP
FS6377-01iG-XTD
FS6377-01iG-XTP
Package
16-pin (0.150”) SOIC
(small outline package)
‘Green’ or lead-free packaging
16-pin (0.150”) SOIC
(small outline package)
‘Green’ or lead-free packaging
16-pin (0.150”) SOIC
(small outline package)
‘Green’ or lead-free packaging
16-pin (0.150”) SOIC
(small outline package)
‘Green’ or lead-free packaging
Shipping Configuration
Temperature Range
Tube/Tray
0°C to 70°C (commercial)
Tape & Reel
0°C to 70°C (commercial)
Tube/Tray
-40°C to 85°C (industrial)
Tape & Reel
-40°C to 85°C (industrial)
10.0 Demonstration Software
Windows XP- (and earlier) based software is available from ON Semiconductor that illustrates the capabilities of the FS6377 and aids in
application development.
Contact your local sales representative for more information.
10.1 Software Requirements
• PC running MS Windows 95/98, 98 SE, ME, NT4, 2000, XP Home Edition, or XP Professional Edition
• 1.8MB available space on hard drive C
• Internet access to operate program found at www.amis.com/products/clocks/FS6377.html
10.2 Demo Program Operation
Launch the demo program from the website. Note that the parallel port cannot be accessed if your machine is not connected to the
demo board. A warning message will appear as shown in Figure 13.
Clicking “Ignore” starts the program for calculation only.
The FS6377 demo hardware is available on a limited basis for demonstration by an ON SEMICONDUCTOR field applications engineer,
but is no longer available for purchase.
The opening screen is shown in Figure 14.
Rev. 4 | Page 21 of 24 | www.onsemi.com
FS6377
Figure 13: Warning Message- Click”Ignore”
Figure 14: Opening Screen
10.2.1. Example Programming
Type a value for the crystal resonator frequency in MHz in the reference crystal box. This frequency provides the basis for all of the PLL
calculations that follow.
Next, click on the PLL A box. A pop-up screen similar to Figure 15 should appear. Type in a desired output clock frequency in MHz, set
the operating voltage (3.3V or 5V) and the desired maximum output frequency error. Pressing Calculate Solutions generates several
possible divider and VCO-speed combinations.
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Figure 15: PLL Screen
For a 100MHz output, the VCO should ideally operate at a higher frequency, and the reference and feedback dividers should be as
small as possible. In this example, highlight Solution #7. Notice the VCO operates at 200MHz with a post divider of two to obtain an
optimal 50 percent duty cycle.
Now choose which mux and post divider to use (that is, choose an output pin for the 100MHz output). Selecting A places the PostDiv
value in Solution #7 into post divider A and switches mux A to take the output of PLL A.
The PLL screen should disappear, and now the value in the PLL A box is the new VCO frequency chosen in Solution #7. Also note that
mux A has been switched to PLL A and the post divider A has the chosen 100MHz output displayed.
Repeat the steps for PLL B.
PLL C supports two different output frequencies depending on the setting of the SEL_CD pin. Both mux C and mux D are also affected
by the logic level on the SEL_CD pin, as are the post dividers C and D.
Figure 16: Post Divider Menu
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Click on PLL C1 to open the PLL screen. Set a desired frequency, however, now choose the post divider B as the output divider. Notice
the post divider box has split in two (as shown in Figure 16). The post divider B box now shows that the divider is dependent on the
setting of the SEL_CD pin for as long as mux B is the PLL C output.
Clicking on post divider A reveals a pull-down menu provided to permit adjustment of the post divider value independently of the PLL
screen. A typical menu is shown in Figure 16. The range of possible post divider values is also given in Table 7.
The register settings are shown to the left in the screen shown in Figure 14. Clicking on a register location displays a screen shown in
Figure 17. Individual bits can be poked, or the entire register value can be changed.
Figure 17: Register Screen
11.0 Revision History
Revision
1
2
3
4
Date
2004
2004
October 2007
May 2008
Modification
Initial doc
Update content to new AMIS template
Update to ON Semiconductor template
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