FSB50825B/FSB50825BS
Motion SPM) 5 Series
Description
The FSB50825B / FSB50825BS is an advanced Motion SPM 5 module
providing a fully−featured, high−performance inverter output for AC
Induction, BLDC and PMSM motors such as refrigerators, fans and pumps.
These modules integrate optimized gate drive of the built−in MOSFETs
(FRFET technology) to minimize EMI and losses, while also providing
multiple on−module protection features including under−voltage lockouts
and thermal monitoring. The built−in high−speed HVIC requires only a single
supply voltage and translates the incoming logic−level gate inputs to the
high−voltage, high−current drive signals required to properly drive the
module’s internal MOSFETs. Separate open−source MOSFET terminals are
available for each phase to support the widest variety of control algorithms.
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SPM5E−023 / 23LD, PDD STD
CASE MODEJ
Features
• UL Certified No. E209204 (UL1557)
• Optimized for Over 10 kHz Switching Frequency
• 250 V RDS(ON) = 0.55 (Max) FRFET MOSFET 3−Phase Inverter
•
•
•
•
•
•
•
•
with Gate Drivers and Protection
Built−In Bootstrap Diodes Simplify PCB Layout
Separate Open−Source Pins from Low−Side MOSFETs for
Three−Phase Current−Sensing
Active−HIGH Interface, Works with 3.3 / 5 V Logic, Schmitt−trigger
Input
Optimized for Low Electromagnetic Interference
HVIC for Gate Driving and Under−Voltage Protection
Isolation Rating: 1500 Vrms / min
RoHS Compliant
Moisture Sensitive Level (MSL) 3 for SMD PKG
SPM5H−023 / 23LD, PDD STD,
SPM23−BD
CASE MODEM
MARKING DIAGRAM
$Y&Z&K&E&E&E&3
FSB50825X
Applications
• 3−Phase Inverter Driver for Small Power AC Motor Drives
$Y
&Z
&3
&K
FSB50825X
= ON Semiconductor Logo
= Assembly Plant Code
= Data Code (Year & Week)
= Lot
= Specific Device Code
X = B or BS
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
this data sheet.
© Semiconductor Components Industries, LLC, 2018
January, 2019 − Rev. 0
1
Publication Order Number:
FSB50825B/D
FSB50825B/FSB50825BS
ABSOLUTE MAXIMUM RATINGS (TC = 25°C, Unless otherwise noted)
Symbol
Conditions
Parameter
Rating
Unit
250
V
250
V
40
A
VPN
DC Link Input Voltage,
Drain−Source Voltage of Each MOSFET
BVDSS
Drain−Source Voltage
IPN
Zero−Bias Static Leakage Current
ID 25 (Note 2)
Each MOSFET Drain Current, Continuous
TC = 25°C
3.6
A
ID 80 (Note 2)
Each MOSFET Drain Current, Continuous
TC = 80°C
2.7
A
IDP (Note 2)
Each MOSFET Drain Current, Peak
TC = 25°C, PW < 100 s
9.0
A
IDRMS (Note 2) Each FRFET Drain Current, Rms
TC = 80°C, FPWM < 20 kHz
1.9
Arms
PD (Note 2)
TC = 25°C, For Each MOSFET
14.2
W
Conditions
Rating
Unit
VIN = 0V, ID = 250 A
VPN= 200V, VIN = 0V,
VDD= VBS= 0V,
TC= TJ = 25°C for all phase
Maximum Power Dissipation
CONTROL PART (Each HVIC Unless Otherwise Specified)
Symbol
Parameter
VDD
Control Supply Voltage
Applied Between VDD and COM
20
V
VBS
High−side Bias Voltage
Applied Between VB and VS
20
V
VIN
Input Signal Voltage
Applied Between IN and COM
−0.3 ~ VDD+0.3
V
BOOTSTRAP DIODE PART (Each Bootstrap Diode Unless Otherwise Specified)
Symbol
Conditions
Parameter
Rating
Unit
250
V
VRRMB
Maximum Repetitive Reverse Voltage
IFB (Note 2)
Forward Current
TC = 25°C
0.5
A
IFPB (Note 2)
Forward Current (Peak)
TC = 25°C, Under 1ms Pulse Width
1.5
A
THERMAL RESISTANCE
Symbol
Conditions
Parameter
Inverter MOSFET part, (Per Module)
Rating
Unit
1.7
_C/W
Rating
Unit
TOTAL SYSTEM
Symbol
Conditions
Parameter
TJ
Operating Junction Temperature
−40 ~ 150
_C
TSTG
Storage Temperature
−40 ~ 125
_C
VISO
Isolation Voltage
1500
Vrms
60 Hz, Sinusoidal, 1 minute, Connection Pins to Heatsink
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. For the Measurement Point of Case Temperature TC, Please refer to Figure 5.
2. Calculation Value or Design Factor.
3. Using continuously under heavy loads or excessive assembly conditions (e.g. the application of high temperature/ current/ voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e.
operating temperature/ current/ voltage, etc.) are within the absolute maximum ratings and the operating ranges.
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2
FSB50825B/FSB50825BS
PACKAGE MARKING AND ORDERING INFORMATION
Device
Device Marking
Package
Packing Type
Reel Size
Quantity
FSB50825B
FSB50825B
SPM5P−023
Rail
N/A
15
FSB50825BS
FSB50825BS
SPM5Q−023
Tape & Reel
330 mm
450
PIN DESCRIPTION
Pin No.
Pin Name
1
COM
IC Common Supply Ground
Pin Description
2
VB(U)
Bias Voltage for U Phase High Side FRFET Driving
3
VDD(U)
Bias Voltage for U Phase IC and Low Side FRFET Driving
4
IN(UH)
Signal Input for U Phase High−side
5
IN(UL)
Signal Input for U Phase Low−side
6
N.C
N.C
7
VB(V)
Bias Voltage for V Phase High Side FRFET Driving
8
VDD(V)
Bias Voltage for V Phase IC and Low Side FRFET Driving
9
IN(VH)
Signal Input for V Phase High−side
10
IN(VL)
Signal Input for V Phase Low−side
11
VTS
12
VB(W)
Bias Voltage for W Phase High Side FRFET Driving
13
VDD(W)
Bias Voltage for W Phase IC and Low Side FRFET Driving
14
IN(WH)
Signal Input for W Phase High−side
15
IN(WL)
Signal Input for W Phase Low−side
16
N.C
17
P
18
U, VS(U)
19
NU
Negative DC–Link Input for U Phase
20
NV
Negative DC–Link Input for V Phase
21
V, VS(V)
22
NW
23
W, VS(W)
Output for HVIC Temperature Sensing
N.C
Positive DC–Link Input
Output for U Phase & Bias Voltage Ground for High Side FRFET Driving
Output for V Phase & Bias Voltage Ground for High Side FRFET Driving
Negative DC–Link Input for W Phase
Output for W Phase & Bias Voltage Ground for High Side FRFET Driving
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3
FSB50825B/FSB50825BS
(1) COM
(2) VB(U)
(17) P
(3) VCC(U)
VCC
VB
(4) IN (UH)
HIN
HO
(5) IN (UL)
LIN
VS
COM
LO
(18) U, V S(U)
(6) N.C
(19) N U
(7) VB(V)
(8) VCC(V)
VCC
VB
(9) IN (VH)
HIN
HO
LIN
VS
COM
LO
(10) IN (VL)
(11) V TS
(20) N V
(21) V, V S(V)
V TS
(12) V B(W)
(13) V CC(W)
VCC
VB
(14) IN (WH)
HIN
HO
LIN
VS
COM
LO
(15) IN (WL)
(22) N W
(23) W, V S(W)
(16) N.C
Figure 1. Pin Configuration and Internal Block Diagram (Bottom View)
NOTE:
4. Source Terminal of Each Low−Side MOSFET is Not Connected to Supply Ground or Bias Voltage Ground
Inside Motion SPM 5 product. External Connections Should be Made as Indicated in Figure 4
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4
FSB50825B/FSB50825BS
ELECTRICAL CHARACTERISTICS (TJ = 25°C, VDD = VBS = 15 V Unless Otherwise Specified)
Test Conditions
Min.
Typ.
Max.
Unit
Drain−Source Breakdown Voltage
VIN= 0 V, ID = 1 mA (Note 5)
250
−
−
V
Zero Gate Voltage Drain Current
VIN= 0 V, VDS = 250 V
−
−
1
mA
RDS(on)
Static Drain−Source On−Resistance
VDD = VBS = 15 V, VIN = 5 V, ID = 2 A
−
0.37
0.55
VSD
Drain−Source Diode Forward Voltage
VDD = VBS = 15 V, VIN = 0 V, ID = −2 A
−
−
1.1
V
−
330
−
ns
−
530
−
ns
Switching Times
VPN = 150 V, VDD = VBS = 15 V, ID = 2
A ON / OFF RG = 800 / 200
VIN = 0 V ↔ 5 V,
Inductive Load L= 3 mH
High and Low−Side MOSFET Switching (Note 6)
−
100
−
ns
−
40
−
J
−
15
−
J
Symbol
Parameter
INVERTER PART (Each MOSFET Unless Otherwise Specified)
BVDSS
IDSS
tON
tOFF
trr
EON
EOFF
RBSOA
Reverse−Bias Safe Operating Area
VPN = 200 V, VDD = VBS = 15 V, ID = IDP,
VDS=BVDSS, TJ = 150_C
High− and Low−Side MOSFET
Switching (Note 7)
Full Square
CONTROL PART (Each HVIC Unless Otherwise Specified)
IQDD
Quiescent VDD Current
VDD = 15 V,
VIN = 0 V
Applied Between
VDD and COM
−
−
200
A
IQBS
Quiescent VBS Current
VBS = 15 V,
VIN = 0 V
Applied Between
VB(U)−U, VB(V)−V,
−
−
100
A
VB(W)−W
IPDD
Operating VDD Supply Current
VDD − COM
VDD = 15 V, fPWM
= 20 kHz, duty
= 50%, Applied
to One PWM
Signal Input for
Low−Side
900
A
IPBS
Operating VBS Supply Current
VB(U) − VS(U),
VB(V) − VS(V),
VB(W) − VS(W)
VDD = VBS = 15
V, fPWM = 20
kHz,
Duty = 50%, Applied to One
PWM Signal Input for High−Side
800
A
UVDDD
UVDDR
UVBSD
UVBSR
VTS
Low−Side Undervoltage Protection
(Figure 8)
High−Side Undervoltage Protection
(Figure 9)
HVIC Temperature sensing voltage
output
VDD Undervoltage Protection Detection Level
7.4
8.0
9.4
V
VDD Undervoltage Protection Reset
Level
8.0
8.9
9.8
V
VBS Undervoltage Protection Detection
Level
7.4
8.0
9.4
V
VBS Undervoltage Protection Reset
Level
8.0
8.9
9.8
V
VDD=15 V, THVIC= 25_C (Note 8)
600
790
980
mV
−
−
2.9
V
0.8
−
−
V
VIH
ON Threshold Voltage
Logic High Level
VIL
OFF Threshold Voltage
Logic Low Level
Applied between
IN and COM
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5
FSB50825B/FSB50825BS
ELECTRICAL CHARACTERISTICS (TJ = 25°C, VDD = VBS = 15 V Unless Otherwise Specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
BOOTSTRAP DIODE PART (Each Bootstrap Diode Unless Otherwise Specified)
VFB
Forward Voltage
IF = 0.1 A, TC = 25_C (Note 9)
−
2.5
−
V
trrB
Reverse Recovery Time
IF = 0.1 A, TC = 25_C
−
80
−
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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6
FSB50825B/FSB50825BS
RECOMMENDED OPERATING CONDITION
Value
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
−
150
200
V
VPN
Supply Voltage
Applied Between P and N
VDD
Control Supply Voltage
Applied Between VDD and COM
13.5
15
16.5
V
VBS
High−Side Bias Voltage
Applied Between VB and VS
13.5
15
16.5
V
VIN(ON)
Input ON Threshold Voltage
Applied Between IN and COM
3.0
−
VDD
V
VIN(OFF)
Input OFF Threshold Voltage
0
−
0.6
V
1.0
−
−
S
−
15
−
kHz
tdead
Blanking Time for Preventing Arm−Short VDD = VBS = 13.5 ∼ 16.5 V, TJ ≤ 150°C
fPWM
PWM Switching Frequency
TJ ≤ 150°C
Built in Bootstrap Diode VF −IF Characteristic
1.0
0.9
0.8
0.7
IF [A]
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
1
2
3
456
7
8
9
VF [V]
10
11
12
13
14
15
Tc=255C
Figure 2. Built in Bootstrap Diode Characteristics (Typ.)
NOTE:
5. BVDSS is the Absolute Maximum Voltage Rating Between Drain and Source Terminal of Each MOSFET Inside Motion SPM
5 product. VPN Should be Sufficiently Less Than This Value Considering the Effect of the Stray Inductance so that VDS Should
Not Exceed BVDSS in Any Case.
6. tON and tOFF Include the Propagation Delay Time of the Internal Drive IC. Listed Values are Measured at the Laboratory
Test Condition, and They Can be Different According to the Field Applications Due to the Effect of Different Printed Circuit
Boards and Wirings. Please see Figure 7 for the Switching Time Definition with the Switching Test Circuit of Figure 7.
7. The peak current and voltage of each MOSFET during the switching operation should be included in the Safe Operating
Area (SOA). Please see Figure 6 for the RBSOA test circuit that is same as the switching test circuit.
8. VTS is only for sensing temperature of module and cannot shutdown MOSFETs automatically.
9. Built in bootstrap diode includes around 15 resistance characteristic. Please refer to Figure 2.
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7
FSB50825B/FSB50825BS
These values depend on PWM control algorithm
C1
+15 V
* Example Circuit : V phase
VDC
P
MCU
R5
C5
VDD
VB
HIN
HO
LIN
VS
COM
LO
V
VTS
10 F
C2
C4
HIN
LIN
Output
Note
Inverter
Output
0
0
Z
Both FRFET Off
0
1
0
Low side FRFET On
C3
1
0
VDC
High side FRFET On
1
1
Forbidden
Shoot through
Open
Open
Z
Same as (0,0)
N
R3
®
One Leg Diagram of Motion SPM 5 Product
* Example of Bootstrap Paramters
:
C1 = C2 = 1 F Ceramic Capacitor
Figure 3. Recommended MCU Interface and Bootstrap Circuit with Parameters
NOTE:
10. Parameters for bootstrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical
example of parameters is shown above.
11. RC−coupling (R5 and C5) and C4 at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be
used to prevent improper signal due to surge−noise.
12. Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the
reduction of surge−voltage. Bypass capacitors such as C1, C2 and C3 should have good high−frequency characteristics to
absorb high−frequency ripple−current.
Figure 4. Case Temperature Measurement
NOTE:
13. Attach the thermocouple on top of the heat−sink of SPM 5 package (between SPM 5 package and heatsink if applied) to
get the correct temperature measurement.
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8
FSB50825B/FSB50825BS
3.5
3.0
VTS [V]
2.5
2.0
1.5
1.0
0.5
20
40
60
80
100
120
140
160
o
THVIC [ C]
Figure 5. Temperature Profile of VTS (Typical)
VIN
VDS
VIN
Irr
120% of ID
100% of ID
ID
ID
10% of ID
VDS
tON
trr
tOFF
(b) Turn−off
(a) Turn-on
Figure 6. Switching Time Definitions
C BS
ID
VDD
VDD
VB
HIN
HO
LIN
VS
COM
LO
L
VDC
+
V DS
−
VTS
One Leg Diagram of Motion SPM
®
5 Product
Figure 7. Switching and RBSOA (Single−Pulse) Test Circuit (Low−side)
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9
FSB50825B/FSB50825BS
Input Signal
UV Protection
Status
Low-side Supply, VDD
RESET
RESET
SET
UVDDR
UVDDD
MOSFET Current
Figure 8. Under−Voltage Protection (Low−Side)
Input Signal
UV Protection
Status
High-side Supply, VBS
RESET
SET
RESET
UVBSR
UVBSD
MOSFET Current
Figure 9. Under−Voltage Protection (High−Side)
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10
FSB50825B/FSB50825BS
C1
(1 ) COM
( 17 )P
(2 )VB(U)
(3 )VDD(U)
R5
(4 ) IN( UH)
(5 ) IN( UL)
C5
C2
(6 )N.C
VDD
VB
HIN
HO
LIN
VS
COM
LO
(18 )U ,VS(U)
C3
(19 )NU
(7 )VB(V)
(8 )VDD(V)
(9 ) IN( VH)
(10 ) IN(VL)
Micom
VDC
(11 ) VTS
(12 ) VB(W)
(13 ) VDD(W)
(14 ) IN( WH)
(15 ) IN( WL)
(16 ) N.C
VDD
VB
HIN
HO
LIN
VS
COM
LO
(20 )NV
(21 )V ,VS(V)
M
VTS
VDD
VB
HIN
HO
LIN
VS
COM
LO
( 22 )NW
(23 ) W V
, S(W)
C4
For current-sensing and protection
15 V
Supply
C6
R4
R3
Figure 10. Example of Application Circuit
NOTE:
14. About pin position, refer to Figure 1.
15. RC−coupling (R5 and C5, R4 and C6) and C4 at each input of Motion SPM 5 product and MCU are useful to prevent
improper input signal caused by surge−noise.
16. The voltage−drop across R3 affects the low−side switching performance and the bootstrap characteristics since it is placed
between COM and the source terminal of the low−side MOSFET. For this reason, the voltage−drop across R3 should be less
than 1 V in the steady−state.
17. Ground−wires and output terminals, should be thick and short in order to avoid surge−voltage and malfunction of HVIC.
18. All the filter capacitors should be connected close to Motion SPM 5 product, and they should have good characteristics for
rejecting high−frequency ripple current.
SPM is a registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other
countries.
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11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SPM5E−023 / 23LD, PDD STD, FULL PACK, DIP TYPE
CASE MODEJ
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON13543G
DATE 31 JAN 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SPM5E−023 / 23LD, PDD STD, FULL PACK, DIP TYPE
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SPM5H−023 / 23LD, PDD STD, SPM23−BD (Ver1.5) SMD TYPE
CASE MODEM
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON13546G
DATE 31 JAN 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SPM5H−023 / 23LD, PDD STD, SPM23−BD (Ver1.5) SMD TYPE
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
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, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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