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FSSD06 — SD/SDIO and MMC Two-Port Multiplexer
Features
Description
On Resistance Typically 4Ω, VDDH=2.7V
ftoggle: > 120MHz
Low On Capacitance: 9pF Typical
Low Power Consumption: 1µA Maximum
Conforms to Secure Digital (SD), Secure Digital I/O
The FSSD06 is a two-port multiplexer that allows Secure
Digital (SD), Secure Digital I/O (SDIO), and Multimedia
Card (MMC) host controllers to be expanded out to
multiple cards or peripherals. This configuration enables
the CMD, CLK, and D[3:0] signals to be multiplexed to
dual-card peripherals. It is optimized for 1-bit / 4-bit SD /
MMC applications.
(SDIO), and Multimedia Card (MMC) Specifications
Supports 1-Bit / 4-Bit Host Controllers (VDDH=1.65V to
3.6V) Communicating with High-Voltage (2.7-3.6V)
and Dual-Voltage Cards (1.65-1.95V, 2.7-3.6V)
-
VDDH=1.65 to 3.6V, VDDC1/C2=VDDH to 3.6V
The architecture includes the necessary bi-directional
data and command transfer capability for single highvoltage cards or dual-voltage supply cards. The clock
path for the FSSD06 is a uni-directional buffer with an
integrated pull-up for high-impedance mode.
Typical applications involve switching in portables and
consumer applications: cell phones, digital cameras,
home theater monitors, portable GPS units, and printers.
24-Lead MLP (3.5 x 4.5mm) and UMLP Packages
Applications
Cell Phone, PDA, Digital Camera, Portable GPS
LCD Monitor, Home Theater PC/TV, All-in-One Printer
Analog Symbol Diagram
VDDC1
/OE
S
Control
VDDC2
VDDH
5
DAT[0:3], CMD
5
CLK
1DAT[0:3], 1CMD
5
V DDC1
V DD C2
RPU
RPU
2DAT[0:3], 2CMD
1CLK
2CLK
GND
Figure 1.
Analog Symbol Diagram
Ordering Information
Part Number
Operating
Temperature Range
FSSD06BQX
-40°C to +85°C
24-Lead Molded Leadless Package (MLP), JEDEC MO220, 3.5 x 4.5mm
Tape & Reel
FSSD06UMX
-40°C to +85°C
24-Lead Ultrathin Molded Leadless Package (UMLP)
Tape & Reel
© 2007 Fairchild Semiconductor Corporation
FSSD06 • Rev. 1.0.5
Package Description
Packing
Method
www.fairchildsemi.com
FSSD06 — SD/SDIO and MMC Two-Port Multiplexer
March 2012
DAT[2]
3
22
VDDC1
DAT[3]
4
21
1CLK
CMD
5
20
1DAT[0]
VDDH
6
19
GND
7
CLK
1DAT[3]
1CMD
VDDC1
23
1DAT[2]
1DAT[3]
1CMD
24
/OE
1DAT[2]
1
DAT[2]
/OE
2
24
23
22
21
20
19
DAT[3]
1
18
1CLK
CMD
2
17
1DAT[0]
1DAT[1]
VDDH
3
16
1DAT[1]
18
2DAT[2]
GND
4
15
2DAT[2]
8
17
2DAT[3]
CLK
5
14
2DAT[3]
DAT[0]
9
16
2CMD
DAT[0]
6
13
2CMD
DAT[1]
10
15
VDDC2
2DAT[0]
2CLK
Figure 3.
9
10
11
12
VDDC2
2DAT[1]
MLP Pin Assignments
8
2CLK
S
Figure 2.
7
2DAT[0]
14
2DAT[1]
13
S
12
DAT[1]
11
UMLP Pin Assignments
FSSD06 — SD/SDIO and MMC Two-Port Multiplexer
Pin Configuration
Pin Definitions
Name
Description
VDDH
Power Supply (Host ASIC)
VDDC1, VDDC2
Power Supply (SDIO Peripheral Card Ports)
/OE
Output Enable (Active Low)
S
Select Pin
1DAT[3:0], 2DAT[3:0], 1CMD, 2CMD
SDIO Card Ports
DAT[3:0], CMD
SDIO Common Ports
CLK, 1CLK, 2CLK
Clock Path Ports
Truth Table
/OE
S
Function
LOW
LOW
CMD, CLK, DAT[3:0] connected to 1CMD, 1CLK, 1DAT[3:0]; 2CLK pulled HIGH via RPU
LOW
HIGH
CMD, CLK, DAT[3:0] connected to 2CMD, 2CLK, 2DAT[3:0]; 1CLK pulled HIGH via RPU
HIGH
X
All Ports High Impedance; 1CLK, 2CLK pulled HIGH via RPU
© 2007 Fairchild Semiconductor Corporation
FSSD06 • Rev. 1.0.5
www.fairchildsemi.com
2
VDDH
1.65 – 3.60V
VDDC1
FSSD06
VDD H to 3.6V
RT
GND
CMD, DAT[3:0]
1CMD, 1DAT[3:0]
5
5
Processor
1CLK
Secure Data /
Multimedia Card
2:1 Peripheral
Expander
CLK
WiFi,
Bluetooth,
MMC or SD
Module
VDDC2
VDD H to 3.6V
RT
Note: External resistors (R T) are
recommended if card supplies are
allowed to float in the application.
The resistors should be >500K to
minimize power consumption.
GND
2CMD, 2DAT[3:0]
5
2CLK
/OE
S
GND
Figure 4.
WiFi,,
Bluetooth,
MMC or SD
Module
Typical Application Diagram
Functional Description
The FSSD06 enables sharing the ASIC/baseband
processor SDIO port(s) to two peripheral cards,
providing bi-directional support for dual-voltage
SD/SDIO or MMC cards available in the marketplace.
Each SDIO port of the FSSD06 has its own supply rail,
allowing peripheral cards with different supplies to be
interfaced to the host. The peripheral card supplies must
be equal or greater than the host to minimize power
consumption. The independent VDDH, VDDC1, and VDDC2
are defined by the supplies connected from the
application Power Management ICs (PMICs) to the
FSSD06. The clock path is a uni-directional buffered
path rather than a bi-directional switch port.
CLK Bus
The 1CLK and 2CLK outputs are bi-state buffer
architectures, rather than a switch I/O, to ensure 52MHz
incident wave switching. When there is no
communication on the bus (IDLE), the FSSD06 can be
disabled with the /OE pin. When this pin is pulled HIGH,
the nCLK outputs are also pulled HIGH. Along with
nCMD, nDAT[3:0] goes high-impedance to ensure that
the CLK path between the FSSD06 and the peripheral
does not float.
IDLE State CMD/DAT Bus “Parking”
The SD and MMC card specifications were written for a
direct point-to-point communication between host
controller and card. The introduction of the FSSD06 in
that path, as an expander, requires that the functional
operation and system latency not be impacted by the
FSSD06 switch characteristics. Since there are various
card formats, protocols, and configurable controllers, a
/OE pin is available to facilitate a fast IDLE transition for
the nCMD/nDAT[3:0] outputs. Some controllers, rather
than simply placing CMD/DAT into high-impedance
mode, may pull their outputs HIGH for a clock cycle prior
to going into high-impedance mode (referred to as
“parking” the output). Some legacy controllers pull their
outputs HIGH versus high impedance.
CMD, DAT Bus Pull-ups
The 1CMD, 2CMD, 1DAT[3:0], and 2DAT[3:0] ports do
not have, internally, the system pull-up resistors as
defined in the MMC or SD card system bus
specifications. The system bus pull-up must be added
external to the FSSD06. The value, within the specific
specification limits, is a function of the individual
application and type of card or peripheral connected. For
SD card applications, the RCMD and RDAT pull-ups should
be between 10kΩ and 100kΩ. For MMC applications,
the RCMD pull-ups should be between 4.7kΩ and 100kΩ
and the RDAT pull-ups between 50kΩ and 100kΩ. The
card-side 1CMD, 2CMD, 1DAT[3:0], and 2DAT[3:0]
outputs have a circuit that facilitates incident wave
switching, so the external pull-up resistors ensure
retention of the output high level.
If the /OE pin is left LOW and the controller places the
CMD/DAT[3:0] outputs into high impedance, the
nCMD/nDAT[3:0] output rise time is a function of the RC
time constant through the switch path. It is
recommended that the host controller pull CMD and
DAT[3:0] HIGH for one cycle before pulling /OE HIGH.
This facilitates parking all nCMD/nDAT[3:0] outputs
HIGH before putting the switch I/Os in high impedance.
The /OE pin can be used to place the 1CMD, 2CMD,
1DAT[3:0] and 2DAT[3:0] into high-impedance mode
when the system enters IDLE state (see IDLE State
CMD/DAT Bus “Parking”).
© 2007 Fairchild Semiconductor Corporation
FSSD06 • Rev. 1.0.5
FSSD06 — SD/SDIO and MMC Two-Port Multiplexer
Typical Application Diagram
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Conditions
Min.
Max.
Unit
4.6
V
4.6
V
VDDH
Supply Voltage
-0.5
VDDC1,VDDC2
Supply Voltage
-0.5
VSW
(1)
VCNTRL(1)
VCLKI(1)
VCLKO(1)
(2)
VDDx +
1DAT[3:0], 2DAT[3:0], 1CMD,
2CMD Pins
-0.5
0.3V
(4.6V maximum)
V
DAT[3:0], CMD Pins
-0.5
(2)
VDDx + 0.3V
(4.6V maximum)
V
Control Input Voltage
S, /OE
-0.5
4.6
V
CLK Input Voltage
CLK
-0.5
4.6
V
Switch I/O Voltage
CLK Output Voltage
1CLK, 2CLK
-0.5
(2)
VDDx +
0.3V
(4.6V maximum)
V
-50
mA
IINDC
Input Clamp Diode Current
ISW
Switch I/O Current
SDIO Continuous
50
mA
Peak Switch Current
SDIO Pulsed at 1ms Duration,
