FSUSB242GEVB

FSUSB242 Type-C USB Port Protection Switch Features • • • • • • • • • • Fully USB Data Port Protection VDD 0 V− 5.5 V (12 V DC tolerant) −18 V to +20 V DC Tolerance on HSD± Port ±25 V IEC 61000−4−5 Surge Protection w/o External TVS VDD Operating Range, 2.7 V−5.5 V HSD RON: 5 W Typical CON = 5 pF Typical Wide −3 dB Bandwidth: > 720 MHz Low Power Operation: ICC < 10 mA (Typical) Over Voltage Protection: 3.6 V & 4.5 V www.onsemi.com WLCSP9 1.20 y 1.20 CASE 567UL MARKING DIAGRAM MT&K XYZ Typical Applications • Smartphones • Tablets • Laptops A1 MT &K X Y Z Safety Mechanisms Highlight • 3.6 V & 4.5 V OVP Trip Point • ±25 V Surge Protection without Need for External TVS PIN CONNECTION USB Type−C Connector VSYS SEL AP/MCU 1 2 3 A VDD HSD− HSD+ B GND SEL HSD1+ C HSD2− HSD2+ HSD1− FSUSB242 OVP Control & Logic HSD1+ HSD+ HSD1− HSD2+ PMIC = Specific Device Code = 2 Digit Lot Run Code = Year = 2 Week Data Code = Plant Code USB HSD Switch HSD2− HSD− GND Figure 1. Application Schematic TOP Through View ORDERING INFORMATION See detailed ordering and shipping information on page 11 of this data sheet. © Semiconductor Components Industries, LLC, 2017 May, 2020 − Rev. 4 1 Publication Order Number: FSUSB242/D FSUSB242 VDD SEL Control & Logic OVP HSD1+ HSD+ HSD2+ HSD1− HSD− HSD2− GND Figure 2. Simplified Block Diagram Table 1. PIN FUNCTION DESCRIPTION CSP Bump Name Type Description A1 VDD Power Supply Power B1 GND Ground Ground A3 HSD+ Data Common High Speed Data Bus A2 HSD− Data Common High Speed Data Bus B3 HSD1+ Data Multiplexed High Speed Data Port 1 C3 HSD1− Data Multiplexed High Speed Data Port 1 C2 HSD2+ Data Multiplexed High Speed Data Port 2 C1 HSD2− Data Multiplexed High Speed Data Port 2 B2 SEL I/O Tri−Input HSD Switch Select & /OE Table 2. SWITCH TRUTH TABLE CONFIGURATION VDD SEL Switch Configuration UVLO X Switch off High impedance Valid 0 HSD+ = HSD1+, HSD− = HSD1− Valid 1 HSD+ = HSD2+, HSD− = HSD2− Valid Float/High−Z Switch Disable High impedance www.onsemi.com 2 FSUSB242 APPLICATION INFORMATION Over Voltage Protection larger then 2.5 MW the switch will recognize the High−Z state and disable the switch. If the system does not have GPIO that supports High−Z state, the user can utilize 2 MOSFETs or a Logic Device to achieve the same result. Over voltage protection turns the switch off if the inputs HSD+/HSD− rise above the over voltage trip threshold. Under Voltage Lockout For GPIO The SEL pin function below: • If the input is pulled up with less than 50 kW it will be considered as Logic High • If the input is pulled down with less than 50 kW it will be consider as Logic Low • If the input is pulled up or down with more 2.5 MW it will be consider as float/High−Z The under−voltage lockout on VDD pin turns the switch off if the VDD voltage drops below the lockout threshold. With the SELpin active, the input voltage rising above the UVLO threshold releases the lockout and enables the switch. Tri−State Input Control Pin (SEL) The SEL pin can be tri−stated to disable the switch to save power, there are a few ways to achieve this. If the SEL pin is controlled by GPIO in the system, if the GPIO pin has a High−Z state where the impedance of the High−Z state is System Timing Diagram SEL = H SEL SEL = L 4V HSD± = HSD2± HSD2± HSD1± 3V HSD± = HSD1± TOFF TON HSD± = HSD2± HSD± = HSD1± HSD± TBBM VDD UVLO Figure 3. System Timing Plot www.onsemi.com 3 TON TOFF FSUSB242 System Block Diagrams 2.7 ~ 5.5 V VDD USB HS 1 USB HS 2 Processor D+ HSD 1+ D− HSD 1− D+ HSD 2+ D− HSD 2− GPIO SEL HSD+ D+ HSD− D− FSUSB 242 GND Type −C connector Figure 4. Application of 2x USB HS interface 2.7 ~ 5.5 V VDD USB HS UART Processor D+ HSD 1+ D− HSD 1− RxD HSD 2+ TxD HSD 2− GPIO HSD+ D+ HSD− D− FSUSB 242 SEL GND Type−C connector Figure 5. Application of UART and USB HS interface 2.7 ~ 5.5 V VDD UART 1 UART 2 Processor RxD HSD 1+ TxD HSD 1− RxD HSD 2+ TxD HSD 2− GPIO SEL FSUSB 242 HSD+ 100 D+ HSD − 100 D− 1nF GND 1nF Type−C connector Figure 6. Application of 2x UART interface When 2x UART signals are switched over FSUSB242, both 100 ohm series resistor and 1 nF bypass capacitors are recommended in the common switch path as above. If FSUSB242 is used to switch USB and UART signals, connect UART signals to HSD1. www.onsemi.com 4 FSUSB242 USB High Speed Eye Diagram VDD = 5.5 V HSD to HSD1 Path Figure 7. HS USB Eye @ VDD = 5 V VDD = 2.7 V HSD to HSD2 Path Figure 8. HS USB Eye @ VDD = 2.7 V www.onsemi.com 5 FSUSB242 Table 3. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Unit VDD Supply Voltage from VDD −0.5 12.0 V VSW DC Input voltage tolerance for HSD±, to GND −18 20 V DC Input voltage tolerance for HSD1±, HSD2± to GND −1.2 6 V VCONTROL DC Input Voltage (SEL) −0.5 ISW DC HSD Switch Current IIK DC Input Diode Current −50 Storage Temperature Range −65 TSTORAGE 6 V 100 mA mA +150 °C TJ Maximum Junction Temperature +150 °C TL Lead Temperature (Soldering, 10 seconds) +260 °C ESD IEC 61000−4−2 System ESD (Note 1) Connector Pins (HSD±) Human Body Model, JEDEC JESD22−A114 Air Gap 15 Contact 8 kV kV Power to GND 2 Internal Pin to GND (HSD1±, HSD2±) 2 External Pin to GND (HSD±) 14 Charged Device Model, JEDEC LESD22−C101 All Pins 1 IEC 61000−4−5 Surge Protection HSD±, to GND ±25 V VDD to GND +12 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. System level test that depends on end system for actual performance. These tests results are with external TVS protection. These specs are listed as general guidelines for expected performance in actual system and do not guarantee listed performance. Table 4. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Typ Max Unit 4.2 5.5 V V VDD Supply Voltage 2.7 VSW1 HSD1 Switch I/O Signal Swing Voltage (Note 2) −0.5 3.6 VSW2 HSD2 Switch I/O Signal Swing Voltage (Note 2) −0.5 4.5 V ICCSW Maximum HSD Switch Continuous Current 75 mA VCNTRL TA Control Input Voltage (SEL) −0.5 VDD V Operating Temperature −40 +85 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 2. The switch swing voltage is based on the OVP trip level, and when OVP triggers the switch will be disabled to protect the host and no longer in the standard operating condition, once over voltage is removed the device will automatically recover back to normal condition. Table 5. DC ELECTRICAL CHARACTERISTICS (Unless otherwise specified: Recommended TA and TJ temperature ranges. All typical values are at TA = 25°C and VDD = 4.2 V unless otherwise specified.) TA = −40 to +855C TJ = −40 to +1255C Symbol Characteristic VDD (V) Conditions 2.7 to 5.5 WLCSP: /OE = H & L, IOUT = 0 Min Typ Max Unit BASIC OPERATION DEVICE ICC Quiescent Supply Current IOFF Power−Off Leakage Current 0 VSWHSD1 = 0 V to 3.6 V, VSWHSD2 = 0 V to 4.5 V www.onsemi.com 6 10 −3 mA 3 mA FSUSB242 Table 5. DC ELECTRICAL CHARACTERISTICS (continued) (Unless otherwise specified: Recommended TA and TJ temperature ranges. All typical values are at TA = 25°C and VDD = 4.2 V unless otherwise specified.) TA = −40 to +855C TJ = −40 to +1255C Symbol Characteristic VDD (V) Conditions Min Typ Max Unit BASIC OPERATION DEVICE IIN Control Input Leakage 2.7 to 5.5 VCNTRL = 0 V to VDD −2 4 mA IOZ Off State Leakage 2.7 to 5.5 HSD± ≥ 0 V, HSD1±, HSD2± ≤ 3.6 V −3 5 mA HSD Path On Resistance 2.7 to 5.5 IOUT = 8 mA, VSW = 0 V to 0.4 V 5 W HSD Path Delta RON 2.7 to 5.5 IOUT = 8 mA, VSW = 0 V to 0.4 V 0.15 W VIH SEL Input Voltage High 2.7 to 5.5 1.3 VIM SEL Input Voltage Middle (Note 3) 2.7 to 5.5 0.8 VIL SEL Input Voltage Low 2.7 to 5.5 Impedance to VDD or GND detected as a Float including VDD = 0 2.7 to 5.5 Input OVP Lockout for HSD1 (FSUSB242UCX) 2.7 to 5.5 BASIC OPERATION HSD SWITCH RON DRON Zfloat VOV_TRIP1 Input OVP Lockout for HSD1 (FSUSB242UCXF45) VOV_TRIP2 VOV_TRIP3_F45 (Note 4) Input OVP Lockout for HSD2 Input OVP Lockout for both HSD1 and HSD2 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 VOV_HYS Input OVP Hysteresis 2.7 to 5.5 VNV_TRIP Input Negative Voltage Lockout 2.7 to 5.5 VNV_HYS VCL VUVLO TSD Input OVP Hysteresis 2.7 to 5.5 Clamping Voltage 2.7 to 5.5 Under−Voltage Lockout Thermal Shutdown (Note 3) V 1.0 V 0.5 V 2.5 MW VHSD± Rising, SEL = 0 3.6 3.8 VHSD± Falling, SEL = 0 3.3 3.5 VHSD± Rising, SEL = 0 4.5 4.7 VHSD± Falling, SEL = 0 4.2 4.4 VHSD± Rising, SEL = 1 4.5 4.7 VHSD± Falling, SEL = 1 4.2 4.4 VHSD± Rising 4.5 4.7 VHSD± Falling 4.2 4.4 4.0 V 4.9 V 4.9 V 4.9 V 0.3 V VHSD± Falling −1.0 V VHSD± Rising −0.7 0.3 V VHSD± ≥ VOV_TRIP 4.5 V VDD Rising 2.4 VDD Falling 2.3 Shutdown Threshold 150 Return from Shutdown 130 Hysteresis 20 2.7 V °C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Guaranteed by characterization or Design, not production tested. www.onsemi.com 7 FSUSB242 4. FSUSB242F45UCX OVP threshold. Table 6. AC ELECTRICAL CHARACTERISTICS (Unless otherwise specified: Recommended TA and TJ temperature ranges. All typical values are at TA = 25°C and VDD = 4.2 V unless otherwise specified.) TA = −40 to +855C TJ = −40 to +1255C Symbol Characteristic VDD (V) Conditions Min Typ Max Unit HSD SWITCH TIMING PARAMETER tOVP OVP Response Time (Note 53) 2.7 to 5.5 IOUT = 8 mA, CL = 5 pF, RL = 50 W, VHSD± = 3.3 V to 4.9 V 0.35 ms tON Turn−On Time, SEL to Output 2.7 to 5.5 RL = 50 W, CL = 5 pF 0.1 ms tOFF Turn−Off Time, SEL to Output 2.7 to 5.5 RL = 50 W, CL = 5 pF, VSW = 0.8 V 0.2 ms tPD Propagation Delay (Note 5) 2.7 to 5.5 RL = 50 W, CL = 5 pF, VSW = 0.8 V 1.3 ns tBBM Break−Before−Make (Note 5) 2.7 to 5.5 RL = 50 W, CL = 5 pF, VSW1 = VSW2 = 0.8 V 50 ms tSK(P) Skew of Opposite Transitions of the Same Output (Note 5) 2.7 to 5.5 VSW = 0.2 VdiffPP, RL = 50 W, CL = 5 pF 35 ps Total Jitter (Note 5) 2.7 to 5.5 VSW = 0.2 VdiffPP, RL = 50 W, CL = 5 pF, tR = tF = 500 ps (10−90%) @ 480 Mbps (PRBS = 215 – 1) 250 ps 1.5 pF tJ HSD+ SWITCH CAPACITANCE CIN Control Pin Input Capacitance (Note 5) 0 CON HSD± On Capacitance (Note 5) 2.7 to 5.5 SEL = L/H, f = 240 MHz 4 COFF HSD± Off Capacitance (Note 5) 2.7 to 5.5 SEL = Float, f = 240 MHz 3 2.7 to 5.5 RL = 50 W, CL = 0 pF 1000 MHz RL = 50 W, CL = 5 pF 550 MHz HSD SWITCH BANDWIDTH BW −3dB SDD21 Bandwidth (Note 5) HSD SWITCH AC PARAMETER OIRR Off Isolation (Note 5) 2.7 to 5.5 RL = 50 W, f = 240 MHz −35 dB Xtalk Non−Adjacent Channel Crosstalk (Note 5) 2.7 to 5.5 RL = 50 W, f = 240 MHz −40 dB Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Guaranteed by characterization or Design, not production tested. www.onsemi.com 8 FSUSB242 TEST DIAGRAMS VON I Dn(OFF) NC HSDn A VSW Dn VSW Select GND I ON Select R ON = VON / ION V Sel = V Sel = GND Figure 10. Off Leakage tRISE = 2.5ns Dn VSW GND RS 0 orV Vcc **Each switch port is tested separately 0 orVcc Figure 9. On Resistance HSDn GND CL RL VCC V OUT 90% Input–– V V/OE ,VSel GND V Sel VOH RL , RS , and C L are functions of the application environment (see AC Tables for specific values) CL includes test fixture and stray capacitance. VOL Figure 11. AC Test Circuit Load VCC /2 10% 90% Output− VOUT GND 90% VCC /2 10% GND tFALL = 2.5ns tON 90% tOFF Figure 12. Turn−On / Turn−Off Waveforms tRISE = 500ps +400mV −400mV 10% 90% 0V tFALL = 500ps 90% 10% Output t PHL Figure 13. Propagation Delay (tRtF − 500 ps) t PLH Figure 14. Intra-Pair Skew Test tSK(P) www.onsemi.com 9 FSUSB242 TEST DIAGRAMS (Continued) tRISE= 2.5ns Vcc HSDn Dn VSW1 GND CL VSW2 RL 0V VOUT 10% V OUT GND GND 90% Vcc/2 Input−−V Sel 0.9*Vout 0.9*Vout RS tBBM V Sel RL , RS , and C L are functions of the application environment (see AC Tables for specific values) CL includes test fixture and stray capacitance. GND Figure 15. Break−Before−Make Interval Timing Network Analyzer Network Analyzer RS GND RS V IN VS VSel GND RT GND GND RS and RT are functions of the application environment (see AC Tables for specific values). RT VSel VOUT GND V OUT GND RS and RT are functions of the application environment (see AC Tables for specific values). RT GND Off isolation = 20 Log (VOUT / V IN) Figure 16. Bandwidth Figure 17. Channel Off Isolation Network Analyzer NC RS GND V IN VS VSel GND VS GND GND GND GND V IN GND RT GND GND RS and RT are functions of the application environment (see AC Tables for specific values). RT V OUT GND Crosstalk = 20 Log (VOUT / V IN) Figure 18. Non-Adjacent Channel-to-Channel Crosstalk www.onsemi.com 10 FSUSB242 TEST DIAGRAMS (Continued) Capacitance Meter Capacitance Meter HSDn HSDn S=LOW or HIGH S=LOW or HIGH OE=HIGH OE=LOW Dn Dn Figure 19. Channel Off Capacitance Figure 20. Channel On Capacitance ORDERING INFORMATION Table 7. AVAILABLE PART NUMBERS Part Number Device Code Operating Temperature Range Package Packing Method† FSUSB242UCX MT −40 to 85°C 9−Ball WLCSP (1.20 x 1.20 mm) Tape and Reel FSUSB242F45UCX MU −40 to 85°C 9−Ball WLCSP (1.20 x 1.20 mm) Tape and Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. www.onsemi.com 11 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WLCSP9, 1.2x1.2x0.48 CASE 567UL ISSUE A SCALE 4:1 A D PIN A1 REFERENCE ÈÈ ÈÈ NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 2009. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO THE SPHERICAL CROWNS OF THE SOLDER BALLS. B E DIM A A1 A2 b D E e TOP VIEW A2 A 0.05 C A1 NOTE 3 9X C SIDE VIEW 0.03 C SEATING PLANE MILLIMETERS MIN NOM MAX 0.488 0.526 0.450 0.176 0.196 0.216 0.274 0.292 0.310 0.24 0.26 0.28 1.14 1.20 1.26 1.14 1.20 1.26 0.40 BSC RECOMMENDED SOLDERING FOOTPRINT* (NSMD PAD TYPE) e b 0.05 C A B DATE 07 JUL 2017 e C B A DIMENSIONS: MILLIMETERS 1 2 3 BOTTOM VIEW DOCUMENT NUMBER: DESCRIPTION: 98AON64604G WLCSP9, 1.2x1.2x0.48 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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