FT8010MPX

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Two delays can be selected by hard-wiring the DSR pin: 7.5 ±20% seconds or 11.25 ±20% seconds. Long Delay Configurable to 7.5 or 11.25 Seconds Primary and Secondary Input Reset Pins Push-Pull and Open-Drain Output Pins 1.8 V to 5.0 V Operation (TA=-40°C to +85°C) 1.7 V to 5.0 V Operation (TA=-25°C to +85°C) 1.65 V to 5.0 V Operation (TA=0°C to +85°C) Packaged in 10-Lead UMLP (1.4 mm x 1.8 mm) and 8-Lead MLP (2.0 mm x 2.0 mm) Packages The FT8010 has two identical inputs for single or dual switch resetting capability. The device has two outputs: a push-pull output with 0.5 mA drive and an open-drain output with 0.5 mA pull-down drive. FT8010 draws minimal ICC current when inactive and functions over a wide 1.65 V to 5.0 V power supply range. Ordering Information Part Number Operating Temperature Range FT8010UMX -40°C to +85°C 10-Lead, Ultrathin MLP, 1.4 x 1.8 x 0.55 mm Package, 0.40 mm Pitch 5000 Units Tape and Reel FT8010MPX -40°C to +85°C 8-Lead, MLP 2.0 x 2.0 x 0.8 mm Package, 0.5 mm Pitch 3000 Units Tape and Reel © 2009 Fairchild Semiconductor Corporation FT8010 • Rev. 1.0.8 Package Packing Method www.fairchildsemi.com FT8010 — Reset Timer with Configurable Delay Time April 2013 FT8010 — Reset Timer with Configurable Delay Time Block Diagram Figure 1. © 2009 Fairchild Semiconductor Corporation FT8010 • Rev. 1.0.8 Block Diagram www.fairchildsemi.com 2 Figure 2. MLP Pin Configuration(1) (Top Through View) Figure 3. UMLP Pin Configuration(2) (Top Through View) Note: 1. The DAP may be a no connect or it may be tied to ground. 2. NC = No connect FT8010 — Reset Timer with Configurable Delay Time Pin Configuration Pin Definitions MLP Pin # UMLP Pin # Name 1 10 RST2 Push-Pull Output, Active HIGH 2 1 GND Ground 3 2 /SR1 Secondary Reset Input, Active LOW 4 3 /RST1 5 5 DSR Delay Selection Input (Must be tied directly to GND or VCC; do not use pull-up or pull-down resistors.) 6 6 TRIG Test Pin, Tied to GND in Normal Use 7 7 /SR0 Primary Reset Input, Active LOW 8 8 VCC Power Supply 4, 9, NC No Connect © 2009 Fairchild Semiconductor Corporation FT8010 • Rev. 1.0.8 Description Open-Drain Output, Active LOW www.fairchildsemi.com 3 The /RST1 output is an open-drain driver. When the count time exceeds time N, the /RST1 output drives LOW. The RST2 output is a push-pull driver. When the count time exceeds time N, the RST2 output drives HIGH. The FT8010 reset timer uses an internal oscillator and a two-stage, 21-bit counter to determine when the output pins switch. Time N is set by the hard-wired logic level of the DSR pin. N is either 7.5 ±20% seconds for DSR=LOW or 11.25 ±20% seconds for DSR=HIGH. Table 1. The TRIG pin should be tied GND or LOW during normal operation. The TRIG pin is a test mode pin used for SCAN testing. FT8010 Truth Table DSR Reset Timer ( +-20% ) 0 7.50s 1 11.25s Application Note IMPORTANT: The DSR pin must be tied to VCC or GND to provide a HIGH or LOW voltage level. The voltage level on the DSR pin determines the length of the configurable delay. It is important that the voltage level on the DSR pin not change during normal operation. The DSR pin must be tied directly to VCC or GND before SR0 or SR1 buttons go LOW. Do not use pull-up or pulldown resistors on the DSR pin. The two input pins, /SR0 and /SR1, drive voltage comparators that compare the voltage on the input with the voltage set by the reference block. A low input signal on both /SR0 and /SR1 starts the oscillator. The oscillator sends data pulses to the digital core, which includes the counter. There are two scenarios for counting, as described below: short duration and long duration. In the short-duration scenario, outputs /RST1 and RST2 are not affected. In the long duration scenario, the outputs change state after time N. The outputs return to their original states when a HIGH input signal occurs on either /SR0 or /SR1. /SR0 /SR1 L L Short Duration (tW < N) In this case, both input /SR0 and /SR1 are LOW for a duration tW which is shorter than time N. When an input goes LOW, the internal timer starts counting. The input goes HIGH before time N. The timer stops counting and resets and no changes occur on the outputs (see Figure 4). /RST1 /RST2 H L H L Description The timer starts counting when both inputs go LOW. The timer stops counting and resets when either input goes HIGH. No changes occur on the outputs, Both /SR0 and /SR1 need to be LOW to activate (start) the timer. Figure 4. © 2009 Fairchild Semiconductor Corporation FT8010 • Rev. 1.0.8 FT8010 — Reset Timer with Configurable Delay Time Functional Description Short Duration Waveform www.fairchildsemi.com 4 seconds. When the input goes HIGH, the timer resets and the outputs switch back to their original state after a propagation delay (see Figure 5). In this case, inputs /SR0 and /SR1 are LOW for a duration, tW, which is longer than time N. When an input goes LOW, the internal timer starts counting. After time N, the outputs switch and the timer stops counting. The input goes HIGH sometime after N /SR0 /SR1 /RST1 L L RST2 Description The timer starts counting when both inputs go LOW. After time N, the outputs switch. When either input goes HIGH, the timer resets and the outputs switch back to their original state. Both /SR0 and /SR1 need to be LOW to activate (start) the timer. Figure 5. FT8010 — Reset Timer with Configurable Delay Time Long Duration (tW > N) Long Duration Waveform Note: 3. Waveforms not drawn to scale (tpHL1, tpLH1 >> tpHL2, tpLH2). © 2009 Fairchild Semiconductor Corporation FT8010 • Rev. 1.0.8 www.fairchildsemi.com 5 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter VCC Supply Voltage VIN DC Input Voltage VOUT Output Voltage (4) IIK DC Input Diode Current IOK DC Output Diode Current IOH/IOL ICC TSTG Condition Min. Max. Unit -0.5 7 V /SR0, /SR1, TRIG, DSR -0.5 7 V /RST1 HIGH or LOW -0.5 7 RST2 HIGH or LOW -0.5 Vcc+0.5 /RST1, RST2, VCC=0 -0.5 7 VIN < 0 V -50 VOUT < 0 V -50 VOUT > VCC +50 DC Output Source/Sink Current -50 DC VCC or Ground Current per Supply Pin Storage Temperature Range -65 V mA mA +50 mA ±100 mA +150 °C °C TJ Junction Temperature under Bias +150 TL Junction Lead Temperature, Soldering 10 Seconds +260 °C PD Power Dissipation 5 mW ESD Electrostatic Discharge Capability Human Body Model, JESD22-A114 4 Charged Device Model, JESD22-C101 2 FT8010 — Reset Timer with Configurable Delay Time Absolute Maximum Ratings kV Note: 4. IO absolute maximum rating must be observed. © 2009 Fairchild Semiconductor Corporation FT8010 • Rev. 1.0.8 www.fairchildsemi.com 6 The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC Parameter Supply Voltage Condition Min. Max. -40C° to +85C° 1.8 5.0 -25C° to +85C° 1.7 5.0 0C° to +85C° 1.65 5.00 tRFC VCC Recovery Time After Power Down VCC=0 V After Power Down, Rising to 0.5 V 5 VIN Input Voltage /SR0, /SR1 0 5 /RST1 HIGH or LOW 0 5 RST2 HIGH or LOW 0 VCC /RST1, RST2, VCC=0 V 0 5 VOUT Output Voltage IOH DC Output Source Current IOL DC Output Sink Current TA Free Air Operating Temperature ΘJA Thermal Resistance Unit V ms RST2, 1.8 V ≤ VCC ≤ 3.0 V -0.1 RST2, 3.0 V ≤ VCC ≤ 5.0 V /RST1, RST2, VCC=1.8 V to 5.0 V -0.5 V V mA +0.5 -40 °C +85 MLP-8 245 UMLP-10 200 FT8010 — Reset Timer with Configurable Delay Time Recommended Operating Conditions °C/W Note: 5. All unused inputs must be held at VCC or GND. DC Electrical Characteristics Unless otherwise specified, conditions of TA=-40 to 80C with VCC=1.8 - 5.0V OR TA=-25 to 85C with VCC=1.7 – 5V OR TA=0 to 85C with VCC=1.65 – 5V produce the performance characteristics below. Symbol Parameter VIH Input High Voltage VIL Input Low Voltage VOH High Level Output Voltage VOL Low Level Output Voltage IIN ICC Condition /SR0, /SR1 DSR Min. Max. 1.2 V 0.65 x VCC /SR0, /SR1 0.32 DSR 0.25 x VCC RST2, IOH=-100 µA 0.8 x VCC RST2, IOH=-500 µA VCC=3.0 to 5.0 V 0.8 x VCC V V RST2, IOL=500 µA 0.3 /RST1, IOL=500 µA 0.3 Input Leakage Current 0 V ≤ VIN ≤ 5.0 V ±1.0 Quiescent Supply Current (Timer Inactive) /SR0 or /SR1=VCC 20 Dynamic Supply Current (Timer Active) /SR0=/SR1=0 V 100 © 2009 Fairchild Semiconductor Corporation FT8010 • Rev. 1.0.8 Unit V µA µA www.fairchildsemi.com 7 Unless otherwise specified, conditions of TA=-40 to 80C with VCC=1.8 - 5.0V OR TA=-25 to 85C with VCC=1.7 – 5V OR TA=0 to 85C with VCC=1.65 – 5V produce the performance characteristics below. Symbol tPHL1 tPLH2 tPLH1 tPHL2 Parameter Conditions Min. Typ. Max. Unit Timer Delay, /SRn to /RST1, CL=5 pF, RL=5 kΩ (DSR=0) See Figure 6 6.0 7.5 9.0 s Timer Delay, /SRn to /RST1, CL=5 pF, RL=5 kΩ (DSR=1) See Figure 6 9.00 11.25 13.50 s 220 310 ns Propagation Delay, /SRn to /RST1, (DSR=0 or 1) CL=5 pF, RL=5 kΩ See Figure 6 Timer Delay, /SRn to RST2, (DSR=0) CL=5 pF,RL=10 kΩ See Figure 7 6.0 7.5 9.0 s Timer Delay, /SRn to RST2, (DSR=1) CL=5 pF, RL=10 kΩ See Figure 7 9.00 11.25 13.50 s Propagation Delay, /SRn to RST2,(DSR=0 or 1) CL=5 pF, RL=10 kΩ See Figure 7 210 300 ns Capacitance Specifications FT8010 — Reset Timer with Configurable Delay Time AC Electrical Characteristics TA=+25°C. Symbol CIN COUT Parameter Conditions Typical Unit Input Capacitance VCC=GND 4.0 pF Output Capacitance VCC=5.0 V 5.0 pF © 2009 Fairchild Semiconductor Corporation FT8010 • Rev. 1.0.8 www.fairchildsemi.com 8 FT8010 — Reset Timer with Configurable Delay Time AC Test Circuit and Waveforms Figure 6. © 2009 Fairchild Semiconductor Corporation FT8010 • Rev. 1.0.8 /RST1 Output www.fairchildsemi.com 9 FT8010 — Reset Timer with Configurable Delay Time AC Test Circuit and Waveforms (Continued) Figure 7. © 2009 Fairchild Semiconductor Corporation FT8010 • Rev. 1.0.8 RST2 Output www.fairchildsemi.com 10 1.40 0.10 C A B 2X (9X) 1.70 0.563 0.663 1.80 1 PIN#1 IDENT 2.10 0.10 C TOP VIEW 0.40 2X (10X) 0.225 0.55 MAX. 0.10 C 0.08 C RECOMMENDED LAND PATTERN (0.15) SEATING C PLANE 0.05 0.00 0.55 SIDE VIEW 1.85 (10X) 0.225 6 OPTIONAL MINIMIAL TOE LAND PATTERN 0.40 1 NOTES: PIN#1 IDENT A. PACKAGE DOES NOT CONFORM TO ANY JEDEC STANDARD. B. DIMENSIONS ARE IN MILLIMETERS. 0.15 (10X) 0.25 10 BOTTOM VIEW 0.10 C A B 0.05 C C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. D. LAND PATTERN RECOMMENDATION IS BASED ON FSC DESIGN ONLY. 0.55 0.45 0.25 0.15 9X 0.45 0.40 0.35 (9X) 0.45 3 DETAIL A 1.45 FT8010 — Reset Timer with Configurable Delay Time Physical Dimensions PACKAGE EDGE 45° DETAIL A SCALE : 2X Figure 8. E. DRAWING FILENAME: MKT-UMLP10Arev5. F. FAIRCHILD SEMICONDUCTOR. LEAD OPTION 2 LEAD OPTION 1 SCALE : 2X SCALE : 2X 10-Lead, Ultrathin MLP, 1.4 x 1.8 x 0.55 mm Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FT8010 • Rev. 1.0.8 www.fairchildsemi.com 11 TOP LAYER CU KEEP OUT AREA 0.10 C 2.00 2X A 0.90 1.80 B E (0.90) 8X PIN1 IDENT (0.25) 8X 0.50 2.00 OPTION #1: NO CENTER PAD 0.10 C 2X (1.35) TOP VIEW 0.10 C (0.35) 0.90 0.80 MAX 1.80 (0.20) (0.90) 8X 0.08 C 0.05 0.00 C SEATING PLANE 0.50 SIDE VIEW 1 (0.25) 8X FT8010 — Reset Timer with Configurable Delay Time Physical Dimensions (Continued) OPTION #2: WITH CENTER PAD RECOMMENDED LAND PATTERN (NSMD PAD TYPE) A 0.25 0.15 8X 0.65 8X 4 0.45 NOTES: A. PACKAGE CONFORMS TO JEDEC MO-229, VARIATION W2020D EXCEPT WHERE NOTED. 0.40 MAX PIN 1 IDENT B. DIMENSIONS ARE IN MILLIMETERS. 0.50 8 0.10 0.05 5 C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. C A B C D. LAND PATTERN RECOMMENDATION BASED ON PCB MATRIX CALCULATOR V2009. 1.35 MAX E. IF CENTER PAD IS NOT SOLDERED TO, NO EXPOSED METAL IS ALLOWED IN THE TOP LAYER OF THE BOARD IN THE AREA SHOWN. BOTTOM VIEW F. DRAWING FILENAME: MKT-MLP08Rrev2. Figure 9. 8-Lead, Molded Leadless Package (MLP), 2.0 x 2.0 x 0.8 mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FT8010 • Rev. 1.0.8 www.fairchildsemi.com 12 FT8010 — Reset Timer with Configurable Delay Time © 2009 Fairchild Semiconductor Corporation FT8010 • Rev. 1.0.8 www.fairchildsemi.com 13 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. 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