HCPL3700VM

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This literature is subject to all applicable copyright laws and is not for resale in any manner. HCPL3700M AC/DC to Logic Interface Optocoupler Features Description • • • • The HCPL3700M voltage/current threshold detection optocoupler consists of an AlGaAs LED connected to a threshold sensing input buffer IC which are optically coupled to a high gain darlington output. The input buffer chip is capable of controlling threshold levels over a wide range of input voltages with a single resistor. The output is TTL and CMOS compatible. AC or DC Input Programmable Sense Voltage Logic Level Compatibility Threshold Guaranteed Over Temperature (0°C to 70°C) • Safety and Regulatory Approvals – UL1577, 5,000 VACRMS for 1 Minute – DIN EN/IEC60747-5-5 Applications • • • • • • Low Voltage Detection 5 V to 240 V AC/DC Voltage Sensing Relay Contact Monitor Current Sensing Microprocessor Interface Industrial Controls Schematics Package Outlines AC 1 8 VCC DC+ 2 7 NC 8 1 DC- 3 6 VO AC 4 5 GND 8 8 1 1 Figure 2. Package Outlines AC/DC POWER RX HCPL3700M GND 1 GND 2 Figure 1. Schematic ©2015 Fairchild Semiconductor Corporation HCPL3700M Rev. 1.1 LOGIC TRUTH TABLE (Positive Logic) Input Output H L L H A 0.1μF bypass capacitor must be connected between pins 8 and 5. www.fairchildsemi.com HCPL3700M — AC/DC to Logic Interface Optocoupler February 2016 As per DIN EN/IEC 60747-5-5, this optocoupler is suitable for “safe electrical insulation” only within the safety limit data. Compliance with the safety ratings shall be ensured by means of protective circuits. Parameter Characteristics Installation Classifications per DIN VDE 0110/1.89 Table 1, For Rated Mains Voltage < 150 VRMS I–IV < 300 VRMS I–IV < 450 VRMS I–III < 600 VRMS I–III < 1000 VRMS (Option TV) I–III Climatic Classification 40/85/21 Pollution Degree (DIN VDE 0110/1.89) 2 Comparative Tracking Index Symbol 175 Value Unit Input-to-Output Test Voltage, Method A, VIORM x 1.6 = VPR, Type and Sample Test with tm = 10 s, Partial Discharge < 5 pC 2,262 Vpeak Input-to-Output Test Voltage, Method B, VIORM x 1.875 = VPR, 100% Production Test with tm = 1 s, Partial Discharge < 5 pC 2,651 Vpeak VIORM Maximum Working Insulation Voltage 1,414 Vpeak VIOTM Highest Allowable Over-Voltage 6,000 Vpeak External Creepage ≥8 mm External Clearance ≥ 7.4 mm ≥ 10.16 mm ≥ 0.5 mm VPR Parameter External Clearance (for Option TV, 0.4" Lead Spacing) DTI TS IS,INPUT PS,OUTPUT RIO Distance Through Insulation (Insulation Thickness) Case Temperature(1) 150 °C 25 mA 250 mW Input Current(1) Output Power (Duty Factor ≤ 2.7%)(1) Insulation Resistance at TS, VIO = 500 V(1) > 109 Ω Note: 1. Safety limit value - maximum values allowed in the event of a failure. ©2015 Fairchild Semiconductor Corporation HCPL3700M Rev. 1.1 www.fairchildsemi.com 2 HCPL3700M — AC/DC to Logic Interface Optocoupler Safety and Insulation Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = 25°C unless otherwise specified. Symbol Parameter Value Unit TSTG Storage Temperature -40 to +125 °C TOPR Operating Temperature -40 to +85 °C TJ TSOL PT Junction Temperature Lead Solder Temperature Total Package Power Dissipation(2) -40 to +125 °C 260 for 10 sec °C 305 mW EMITTER IIN VIN PIN Input Current Average 50 Surge, 3 ms, 120 Hz Pulse Rate 140 Transient, 10 μs, 120 Hz Pulse Rate 500 Input Voltage (Pins 2-3) Input Power Dissipation(3) mA -0.5 V 230 mW 30 mA V DETECTOR IO Output Current (Average)(4) VCC Supply Voltage (Pins 8-5) -0.5 to 20 VO Output Voltage (Pins 6-5) -0.5 to 20 V PO Output Power Dissipation(5) 210 mW Notes: 2. Derate linearly above 70°C free-air temperature at a rate of 2.5 mW/°C. 3. Derate linearly above 70°C free-air temperature at a rate of 1.8 mW/°C. 4. Derate linearly above 70°C free-air temperature at a rate of 0.6 mA/°C. 5. Derate linearly above 70°C free-air temperature at a rate of 1.9 mW/°C. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC TA f Parameter Min. Max. Unit Supply Voltage 2 18 V Ambient Operating Temperature 0 70 °C Operating Frequency 0 4 kHz ©2015 Fairchild Semiconductor Corporation HCPL3700M Rev. 1.1 www.fairchildsemi.com 3 HCPL3700M — AC/DC to Logic Interface Optocoupler Absolute Maximum Ratings Symbol ITH+ ITH- Parameter Test Conditions 2.40 3.11 VO = 0.4 V, IO ≥ 4.2 mA 1.00 1.20 1.62 VIN = V2 - V3 (Pins 1 & 4 Open) VCC = 4.5 V, VO = 0.4 V(6) IO ≥ 4.2 mA 3.35 3.80 4.05 V 2.01 2.50 2.86 V 4.23 5.00 5.50 V 2.87 3.70 4.20 V lVIN = V1 - V4l (Pins 2 & 3 Open) VCC = 4.5 V, VO = 0.4 V(6) IO ≥ 4.2 mA AC (Pins 1, 4) lVIN = lV1 - V4l (Pins 2 & 3 Open) VCC = 4.5 V, VO = 2.4 V(6) IO ≤ 100 µA VTHIHYS 1.96 DC (Pins 2, 3) VIN = V2 - V3 (Pins 1 & 4 Open) VCC = 4.5 V, VO = 2.4 V(6) IO ≥ 100 µA VTH+ VHYS Max. (6) VTH+ Input Threshold Voltage Typ. VIN = VTH+, VCC = 4.5 V Input Threshold Current VTH- Min. Hysteresis Unit mA IHYS = ITH+ - ITH- 1.2 mA VHYS = VTH+ - VTH- 1.3 V VIHC1 VIHC1 = V2 - V3, V3 = GND, IIN = 10 mA, Pins 1 & 4 connected to Pin 3 5.4 6.3 6.6 V VIHC2 VIHC2 = lV1 - V4l, lIINl = 10 mA (Pins 2 & 3 Open) 6.1 7.0 7.3 V 13.4 V Input Clamp Voltage VIHC3 VIHC3 = V2 - V3, V3 = GND, IIN = 15 mA (Pins 1 & 4 Open) 12.5 VILC VILC = V2 - V3, V3 = GND, IIN = -10 mA -0.75 IIN VD1,2 VD3,4 VOL Input Current Bridge Diode Forward Voltage Logic LOW Output Voltage VIN = V2 - V3 = 5.0 V (Pins 1 & 4 Open) 3.0 IIN = 3 mA IIN = 3 mA VCC = 4.5 V, IOL = 4.2 mA(6) 3.7 V 4.4 mA 0.65 V 0.65 V 0.04 V(6) 0.40 V 100 µA Logic HIGH Output Current VOH = VCC = 18 ICCL Logic LOW Supply Current V2 - V3 = 5.0 V, VO = Open, VCC = 5 V 1.0 4 mA ICCH Logic HIGH Supply Current VCC = 18 V, VO = Open 0.01 4 µA CIN Input Capacitance f = 1 MHz, VIN = 0 V (Pins 2 & 3, Pins 1 & 4 Open) IOH 50 pF Note: 6. Logic LOW output level at pin 6 occurs when VIN ≥ VTH+ and when VIN > VTH- once VIN exceeds VTH+. Logic HIGH output level at pin 6 occurs when VIN ≤ VTH- and when VIN < VTH+ once decreases below VTH-. ©2015 Fairchild Semiconductor Corporation HCPL3700M Rev. 1.1 www.fairchildsemi.com 4 HCPL3700M — AC/DC to Logic Interface Optocoupler Electrical Characteristics (TA = 0°C to 70°C Unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Unit tPHL Propagation Delay Time (to Output Low Level) RL = 4.7 kΩ, CL = 30 pF(7) 6.0 15 µs tPLH Propagation Delay Time (to Output High Level) RL = 4.7 kΩ, CL = 30 pF(7) 25.0 40 µs tR Output Rise Time (10–90%) RL = 4.7 kΩ, CL = 30 pF 45 µs tF Output Fall Time (90–10%) RL = 4.7 kΩ, CL = 30 pF 0.5 µs |CMH| Common Mode Transient Immunity (at Output High Level) IIN = 0 mA, RL = 4.7 kΩ, VO min = 2.0 V, VCM = 1400 V(8)(9) 4000 V/µs |CML| Common Mode Transient Immunity (at Output Low Level) IIN = 3.11 mA, RL = 4.7 kΩ, VO max = 0.8 V, VCM = 1400 V(8)(9) 600 V/µs Isolation Characteristics (TA = 25°C unless otherwise specified.) Symbol Parameter Test Conditions VISO Withstand Isolation Voltage RH ≤ 50%, II-O ≤ 10 µA t = 1 minute, f = 50 Hz(10)(11) RI-O Resistance (Input to Output) VIO = 500 VDC(10) CI-O Capacitance (Input to Output) f = 1 MHz, VIO = 0 VDC Min. Typ. 5000 Max. Unit VACRMS 1012 Ω 0.6 pF Notes: 7. TPHL propagation delay is measured from the 2.5 V level of the leading edge of a 5.0 V input pulse (1 μs rise time) to the 1.5 V level on the leading edge of the output pulse. TPLH propagation delay is measured on the trailing edges of the input and output pulse. (Refer to Fig. 11) 8. Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the leading edge of the common mode pulse signal VCM, to assure that the output will remain in a logic high state (i.e., VO > 2.0 V). Common mode transient immunity in logic low level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a logic low state (i.e., VO < 0.8 V). Refer to Fig. 12. 9. In applications where dVcm/dt may exceed 50,000 V/μs (Such as static discharge), a series resistor, RCC, should be included to protect the detector chip from destructive surge currents. The recommended value for RCC is 240 V per volt of allowable drop in VCC (between pin 8 and VCC) with a minimum value of 240 Ω. 10. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together. 11. The 5000 VACRMS/1 min. capability is validated by a 6000 VACRMS/1 sec. dielectric voltage withstand test. ©2015 Fairchild Semiconductor Corporation HCPL3700M Rev. 1.1 www.fairchildsemi.com 5 HCPL3700M — AC/DC to Logic Interface Optocoupler Switching Characteristics (TA = 25°C, VCC = 5 V unless otherwise specified) 50 DC (Pins 1,2 shorted together 3.5 IIN - INPUT CURRENT (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4 6 8 10 12 14 16 18 pins 3,4 shorted together) 40 30 DC (Pins 1 & 4 Open) 20 10 0 AC (Pins 2 & 3 Open) -10 20 0 2 VCC - OPERATING SUPPLY VOLTAGE (V) 120 4.0 110 3.8 100 3.6 90 80 VIN = 5.0 V 3.2 70 (PINS 2 and 3) 3.0 60 2.8 50 2.6 40 2.4 VOL 30 2.2 VCC = 5.0 V 20 IOL = 4.2 mA 2.0 1.8 -40 -20 0 20 40 60 10 80 10 12 14 0 100 3.2 4.0 3.0 VTH+ 3.8 2.8 3.6 2.6 3.4 2.4 ITH+ 3.2 2.2 3.0 2.0 2.8 1.8 VTH- 2.6 1.6 2.4 1.4 2.2 1.8 -40 1.2 ITH- 2.0 -20 0 o 20 1.0 40 60 80 0.8 100 o TA - TEMPERATURE ( C) TA - TEMPERATURE ( C) Figure 5. Input Current/Low Level Output Voltage vs. Temperature Figure 6. Current Threshold/Voltage Threshold vs. Temperature 30 100 0.5 25 80 20 15 tPLH 10 tF 60 0.3 50 40 0.2 tR 30 -20 0 20 0.1 10 tPHL 40 60 80 0 -40 100 o -20 0 20 40 60 80 0.0 100 o TA - TEMPERATURE ( C) TA - TEMPERATURE ( C) Figure 7. Propagation Delay vs. Temperature Figure 8. Rise and Fall Time vs. Temperature ©2015 Fairchild Semiconductor Corporation HCPL3700M Rev. 1.1 70 20 5 0 -40 0.4 tF - FALL TIME (μs) 90 tR - RISE TIME (μs) tP - PROPAGATION DELAY (μs) 8 4.2 VTH(DC) - VOLTAGE THRESHOLD (V) 4.2 IIN 6 Figure 4. Input Current vs. Input Voltage VOL - LOW LEVEL OUTPUT VOLTAGE (mV) IIN - INPUT CURRENT (mA) Figure 3. Logic Low Supply Current vs. Operating Supply Voltage 3.4 4 VIN - INPUT VOLTAGE (V) ITH(DC) - CURRENT THRESHOLD (mA) ICCL - LOGIC LOW SUPPLY CURRENT (mA) 4.0 www.fairchildsemi.com 6 HCPL3700M — AC/DC to Logic Interface Optocoupler Typical Performance Curves V+ / V- - EXTERNAL THRESHOLD VOLTAGE (V) ICCH - LOGIC HIGH SUPPLY CURRENT (nA) 100 VCC = 18 V VO = Open IIN = 0 A 10 1 0.1 -40 -20 0 20 40 60 80 100 o TA - TEMPERATURE ( C) Figure 9. Logic High Supply Current vs. Temperature 250 V+ (AC) 200 V+ (DC) V- (AC) 150 V- (DC) 100 50 0 0 40 80 120 160 200 240 RX - EXTERNAL SERIES RESISTOR (kΩ) Figure 10. External Threshold Characteristics V+/Vvs. Rx ©2015 Fairchild Semiconductor Corporation HCPL3700M Rev. 1.1 300 www.fairchildsemi.com 7 HCPL3700M — AC/DC to Logic Interface Optocoupler Typical Performance Curves (Continued) HCPL3700M — AC/DC to Logic Interface Optocoupler Test Circuits +5 V 5V 1 AC Pulse Generator tr = 5 ns Z O= 50 Ω VCC 8 2 DC+ 3 DC- 7 VO 0.1 μF bypass 0V t PHL Output 6 CL 4 AC 2.5 V Input (VIN) RL t PLH (VO ) VO Output (VO ) GND 5 90% 10% 90% 1.5 V 10% VOL tR tF VIN Pulse Amplitude = 50 V Pulse Width = 1 ms f = 100 Hz Tr = Tf = 1.0 μs (10%–90%) Fig. 11. Switching Test Circuit 1400 V I IN RCC* 1 AC A B VFF 7 2 DC+ 3 DC4 AC +5 V VCC 8 VO 0.1 μF bypass RL VCM (VO ) GND 5 VO CL** + 0V Output 6 VOH Switching Pos. (A) I IN = 0 mA VO (Min) VCM * SEE NOTE 8 Pulse Gen VO (Max) ** CL IS 30 pF, WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE VO Switching Pos. (B) I IN = 3.11 mA VOL Fig. 12. Test Circuit for Common Mode Transient Immunity and Typical Waveforms ©2015 Fairchild Semiconductor Corporation HCPL3700M Rev. 1.1 www.fairchildsemi.com 8 HCPL3700M — AC/DC to Logic Interface Optocoupler Reflow Profile Temperature (°C) TP 260 240 TL 220 200 180 160 140 120 100 80 60 40 20 0 Max. Ramp-up Rate = 3°C/S Max. Ramp-down Rate = 6°C/S tP Tsmax tL Preheat Area Tsmin ts 120 240 360 Time 25°C to Peak Time (seconds) Profile Freature Pb-Free Assembly Profile Temperature Min. (Tsmin) 150°C Temperature Max. (Tsmax) 200°C Time (tS) from (Tsmin to Tsmax) 60–120 seconds Ramp-up Rate (tL to tP) 3°C/second max. Liquidous Temperature (TL) 217°C Time (tL) Maintained Above (TL) 60–150 seconds Peak Body Package Temperature 260°C +0°C / –5°C Time (tP) within 5°C of 260°C 30 seconds Ramp-down Rate (TP to TL) 6°C/second max. Time 25°C to Peak Temperature 8 minutes max. Figure 13. Reflow Profile ©2015 Fairchild Semiconductor Corporation HCPL3700M Rev. 1.1 www.fairchildsemi.com 9 Part Number Package Packing Method HCPL3700M DIP 8-Pin Tube (50 units) HCPL3700SM SMT 8-Pin (Lead Bend) Tube (50 units) HCPL3700SDM SMT 8-Pin (Lead Bend) Tape and Reel (1,000 units) HCPL3700VM DIP 8-Pin, DIN EN/IEC60747-5-5 option Tube (50 units) HCPL3700SVM SMT 8-Pin (Lead Bend), DIN EN/IEC 60747-5-5 option Tube (50 units) HCPL3700SDVM SMT 8-Pin (Lead Bend), DIN EN/IEC 60747-5-5 option Tape and Reel (1,000 units) HCPL3700TVM DIP 8-Pin, 0.4” Lead Spacing, DIN EN/IEC 60747-5-5 option Tube (50 units) Marking Information 1 3700 XX YY B V 3 2 6 5 4 Figure 14. Top Mark Definitions 1 Fairchild Logo 2 Device Number 3 DIN EN/IEC60747-5-5 Option (only appears on component ordered with this option) 4 Two Digit Year Code, e.g., ‘15’ 5 Two Digit Work Week Ranging from ‘01’ to ‘53’ 6 Assembly Package Code ©2015 Fairchild Semiconductor Corporation HCPL3700M Rev. 1.1 www.fairchildsemi.com 10 HCPL3700M — AC/DC to Logic Interface Optocoupler Ordering Information ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. 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