NCV4254CPDSTR2G

NCV4254C Low Dropout Voltage Tracking Regulator The NCV4254C is a monolithic integrated low dropout tracking voltage regulator designed to provide an adjustable buffered output voltage that closely tracks the reference input voltage. The output delivers up to 70 mA while being able to be configured higher, lower or equal to the reference voltages. The part can be used in automotive applications with remote sensors or any situation where it is necessary to isolate the output of the other regulator. The NCV4254C also enables the user to bestow a quick upgrade to their module when added current is needed and the existing regulator cannot provide. www.onsemi.com MARKING DIAGRAMS 8 Features • • • • • • • • SOIC8 D SUFFIX CASE 751 8 1 Up to 70 mA Source Capability Low Output Tracking Tolerance Low Dropout (typ. 220 mV @ 70 mA) Low Disable Current in Stand−by Mode Wide Input Voltage Operating Range Protection Features: ♦ Current Limitation ♦ Thermal Shutdown ♦ Reverse Input Voltage and Reverse Bias Voltage NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Grade 1 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant 4254Cx ALYWW G 1 8 SOIC8 EP PD SUFFIX CASE 751AC 8 1 4254Cx ALYWW G 1 = A for Adjust version = S for Status version = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Device x A L Y WW G (Note: Microdot may be in either location) PIN CONNECTIONS Typical Applications VOUT GND GND ADJ or ST • Off the module loads (e.g. sensors power supply) VIN GND GND VEN/REF SOIC−8 (Top View) VOUT NC NC ADJ or ST VIN NC GND VEN/REF SOIC−8 EP (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. © Semiconductor Components Industries, LLC, 2016 November, 2018 − Rev. 0 1 Publication Order Number: NCV4254C/D NCV4254C Vin Vout VEN /REF BIAS CURRENT LIMIT SATURATION PROTECTION THERMAL SHUTDOWN − ADJ + GND EN/REF Figure 1. Block Diagram for Adjust Version NCV4254C Vin Vout VEN /REF BIAS CURRENT LIMIT SATURATION PROTECTION STATUS GENERATOR THERMAL SHUTDOWN ST − + GND EN/REF Figure 2. Block Diagram for Status Output for NCV4254C www.onsemi.com 2 NCV4254C Table 1. PIN FUNCTION DESCRIPTION Pin No. SOIC−8 Pin No. SOIC−8 EP Pin Name 1 1 Vout Tracker Output Voltage. Connect 2.2 µF capacitor with ESR < 5 W to ground be connected directly or by a voltage divider for lower output voltages. 2, 3, 6, 7 6 GND Power Supply Ground. − 2, 3, 7 NC Not Connected. Connect to GND 4 4 ADJ Voltage Adjust Input. The adjust input can be connected directly to output pin for Vout = VEN/REF or by a voltage divider for higher/lower output voltages. The adjust pin can be also connected to ground in case of using this device as a High−Side Driver. 4 4 ST 5 5 EN/REF 8 8 Vin − PAD PAD Description Tracking Regulator Status Output. Open collector output. Connect via a pull−up resistor to a positive voltage rail. A low signal indicates fault conditions at the regulator’s output. Enable / Reference. Connect the reference to this pin. A low signal disables the IC; a high signal switches it on. The reference voltage can be connected directly or by a voltage divider for lower output voltages. Positive Power Supply Input. Connect 0.1 µF capacitor to ground. Exposed Pad. Connect to GND Table 2. MAXIMUM RATINGS Rating Input Voltage DC (Note 1) Symbol Min Max Unit Vin −20 45 V 45 V DC Peak Transient Voltage (Load Dump) (Note 2) Vin Output Voltage Vout −5 40 V Enable / Reference Input Voltage DC VEN/REF −20 40 V Adjust Voltage (Adjust Version) DC VADJ −20 40 V Status output Voltage (Status Output Version) DC VST −0.3 7 V TJ(max) −40 150 °C TSTG −55 150 °C Maximum Junction Temperature Storage Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in production. Passed Class B according to ISO16750−1. Table 3. ESD CAPABILITY (Note 3) Rating ESD Capability, Human Body Model Symbol Min Max Unit ESDHBM −4 4 kV 3. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (JS−001−2010) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115) Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes = 2.5 V, Cin = 0.1 µF, Cout = 2.2 µF, for typical values TJ = 25°C, for min/max values TJ = −40°C to 150°C; unless otherwise noted. (Note 6) Parameter Test Conditions Symbol Min Typ Max Unit Output Voltage Tracking Accuracy Vin = 5.7 V to 26 V, Iout = 0.1 mA to 60 mA 2.5 V ≤ VEN/REF ≤ (VIN − 600 mV) DVout −3 − 3 mV Output Voltage Tracking Accuracy Vin = 5.5 V to 26 V, Iout = 0.1 mA to 60 mA VEN/REF = 5 V DVout −10 − 10 mV Output Voltage Tracking Accuracy Vin = 5.5 V to 32 V, Iout = 0.1 mA to 30 mA VEN/REF = 5 V DVout −10 − 10 mV Line Regulation Vin = 5.5 V to 32 V, Iout = 5 mA, VEN/REF = 5V Regline −5 − 5 mV Load Regulation Iout = 0.1 mA to 70 mA, VEN/REF = 5 V Regload −5 − 5 mV Dropout Voltage (Note 7) Iout = 70 mA, VEN/REF = 5 V VDO − 220 400 mV Disable Current, Stand−by Mode VEN/REF ≤ 0.4 V, TJ ≤ 125°C IDIS − 0.01 5 mA Quiescent Current, Iq = Iin − Iout Iout ≤ 0.1 mA, VEN/REF = 5 V Iout ≤ 70 mA, VEN/REF = 5 V Iq − − 65 1 80 2 mA mA ILIM 71 110 150 mA REGULATOR OUTPUT DISABLE AND QUIESCENT CURRENTS CURRENT LIMIT PROTECTION Current Limit Vout = (VEN/REF – 0.1 V), VEN/REF = 5 V REVERSE CURRENT PROTECTION Reverse Current Vin = 0 V, Vout = 32 V, VEN/REF = 5 V Iout_rev −15 −10 − mA Reverse Current at Negative Input Voltage Vin = −16 V, Vout = 0 V, VEN/REF = 5 V Iin_rev −1 −0.2 − mA f = 100 Hz, 1 Vp−p PSRR − 60 − dB − 2 − − 0.4 − PSRR Power Supply Ripple Rejection (Note 8) ENABLE / REFERENCE Enable / Reference Input Threshold Voltage Logic Low Logic High Vth(EN/R Vout = 0 V, Iout ≤ 5 mA, Tj ≤ 125°C |Vout − VEN/REF| < 10 mV EF) V 6. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA ≈ TJ. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 7. Measured when output voltage falls 100 mV below the regulated voltage at Vin = 13.5 V. 8. Values based on design and/or characterization. www.onsemi.com 4 NCV4254C Table 7. ELECTRICAL CHARACTERISTICS Vin = 13.5 V, VEN/REF >= 2.5 V, Cin = 0.1 µF, Cout = 2.2 µF, for typical values TJ = 25°C, for min/max values TJ = −40°C to 150°C; unless otherwise noted. (Note 6) Parameter Test Conditions Symbol Min Typ Max Unit ENABLE / REFERENCE Enable / Reference Input Current VEN/REF = 5 V IEN/REF − 2 3 mA Enable / Reference Input Current if Input tied to GND Vin = 0 V, VEN/REF = 5 V IEN/REF − 0.003 0.6 mA REN/REF 1.7 2.2 3.3 MW IADJ − 0.03 0.5 mA Enable / Reference Internal Pull−Down Resistor ADJUST (only Adjust Version) Adjust Input Biasing Current VADJ = 5 V STATUS OUTPUT (only Status Version) Status Switching Threshold, Undervoltage Vout decreasing Vout_UV VEN/REF VEN/REF VEN/REF −120 −77 −50 mV Status Switching Threshold, Overvoltage Vout increasing Vout_OV VEN/REF VEN/REF VEN/REF +50 +77 +120 mV tST 10 23 33 ms Status Output Low Voltage IST = 1 mA, Vin ≥ 4 V VST_low − − 0.4 V Status Output Sink Current Limitation VST = 0.8 V IST_max 1 − − mA Status Output Leakage Current Vout = VEN/REF, VST = 5 V IST_leak − − 2 mA TSD 151 175 200 °C Status reaction Time THERMAL SHUTDOWN Thermal Shutdown Temperature (Note 8) 6. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA ≈ TJ. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 7. Measured when output voltage falls 100 mV below the regulated voltage at Vin = 13.5 V. 8. Values based on design and/or characterization. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 5 NCV4254C TYPICAL CHARACTERISTICS 100 Unstable Region Vin = 13.5 V VREF = 5 V 2 10 1 Iout = 0.1 mA 0 ESR (W) Vout, TRACKING ACCURACY (mV) 3 Iout = 70 mA 1 Stable Region −1 Cout = 2.2 mF Vin = 13.5 V VREF = 5 V TJ = 25°C 0.1 −2 −3 −40 −20 0 20 40 60 100 80 120 0.01 140 0 50 40 60 Figure 3. Tracking Accuracy DVout vs. Junction Temperature Tj Figure 4. Output Capacitor Series Resistor ESR vs. Output Current Iout 70 6 Vout, OUTPUT VOLTAGE (V) 5 4 3 2 TJ = −40°C TJ = 25°C TJ = 150°C 1 0 160 1 2 3 4 5 4 3 2 1 0 1 2 3 4 5 6 7 8 VREF, REFERENCE VOLTAGE (V) Vin, INPUT VOLTAGE (V) Figure 5. Output Voltage Vout vs. Reference Voltage VEN/REF Figure 6. Output Voltage Vout vs. Input Voltage Vin VEN/REF = 5 V TJ = 150°C TJ = 25°C 140 120 TJ = −40°C 100 80 60 40 20 0 VREF = 5 V TJ = 25°C Iout = 70 mA 5 0 6 Iout_max, OUTPUT CURRENT LIMITATION (mA) Vout, OUTPUT VOLTAGE (V) Iout_max, OUTPUT CURRENT LIMITATION (mA) 30 Iout, OUTPUT CURRENT (mA) Vin = 13.5 V 0 20 TJ, JUNCTION TEMPERATURE (°C) 6 0 10 5 10 15 20 25 30 35 40 160 VEN/REF = 2 V TJ = 25°C 140 TJ = 150°C TJ = −40°C 120 100 80 60 40 20 0 0 5 10 15 20 25 30 35 40 Vin, INPUT VOLTAGE (V) Vin, INPUT VOLTAGE (V) Figure 7. Output Current Limitation Iout_max vs. Input Voltage Vin , V REF = 5 V Figure 8. Output Current Limitation Iout_max vs. Input Voltage Vin , V REF = 2 V www.onsemi.com 6 NCV4254C TYPICAL CHARACTERISTICS 350 TJ = 150°C 300 VDR, DROPOUT VOLTAGE (mV) VDR, DROPOUT VOLTAGE (mV) 350 250 TJ = 25°C 200 150 TJ = −40°C 100 VREF = 5 V 50 0 0 10 20 30 40 50 60 70 200 150 100 VREF = 5 V 50 0 20 40 60 80 100 120 140 Iout, OUTPUT CURRENT (mA) TJ, JUNCTION TEMPERATURE (°C) Figure 9. Dropout Voltage VDR vs. Output Current Iout Figure 10. Dropout Voltage VDR vs. Junction Temperature Tj −0.1 Iout, REVERSE CURRENT (mA) Iin, REVERSE CURRENT (mA) 250 0 TJ = −40°C −0.2 TJ = 150°C −0.3 −0.4 −0.5 VREF = 5 V −0.6 −32 −28 −24 −20 −16 −12 −8 −4 −2 −4 TJ = −40°C −6 −8 TJ = 150°C −10 Vin = 13.5 V VREF = 5 V −12 −14 0 0 4 8 12 16 20 24 28 Vin, INPUT VOLTAGE (V) Vout, OUTPUT VOLTAGE (V) Figure 11. Reverse Current Iin vs. Input Voltage Vin Figure 12. Reverse Current Iin vs. Output Voltage Vout 32 90 Vin = 13.5 V VREF = 5 V 1.2 Iq, QUIESCENT CURRENT (mA) 1.4 Iq, QUIESCENT CURRENT (mA) Iout = 70 mA 0 −40 −20 80 0 TJ = 150°C 1.0 0.8 TJ = −40°C 0.6 0.4 0.2 0 300 0 10 20 30 40 50 60 80 70 60 50 40 30 10 0 70 TJ = 25°C Iout = 1 mA VREF = 5 V 20 5 10 15 20 25 30 35 Iout, OUTPUT CURRENT (mA) Vin, INPUT VOLTAGE (V) Figure 13. Quiescent Current Iq vs. Output Current Iout Figure 14. Quiescent Current Iq vs. Input Voltage Vin www.onsemi.com 7 40 NCV4254C TYPICAL CHARACTERISTICS 2.5 2.0 1.5 1.0 Vin = 13.5 V VREF = 5 V 0.5 Iout (50 mA/div) 0 −40 −20 Vout (50 mV/div) IREF, REFERENCE CURRENT (mA) 60 0 20 40 60 80 100 120 VREF = 5 V TJ = 150°C 50 40 30 20 10 0 140 0 5 10 15 20 25 30 35 40 45 TJ, JUNCTION TEMPERATURE (°C) Vin, INPUT VOLTAGE (V) Figure 15. Enable / Reference Input Current IEN/REF vs. Junction Temperature T j Figure 16. Enable / Reference Input Current IEN/REF vs. Input Voltage Vin 70 mA 0.1 mA 35 TJ = 25°C Vin = 13.5 V Cout = 2.2 mF trise/fall = 1 ms (Iout) tST, STATUS REACTION TIME (ms) IREF, REFERENCE CURRENT (mA) 3.0 5.113 V 5V 4.910 V 30 25 20 15 Vin = 13.5 V VREF = 5 V 10 −40 −20 TIME (400 ms/div) 0 20 40 60 80 100 120 TJ, JUNCTION TEMPERATURE (°C) Figure 17. Load Transient Figure 18. Status Reaction Time tST vs. Junction Temperature TJ www.onsemi.com 8 140 NCV4254C APPLICATION INFORMATION temperature above 150°C is outside the maximum ratings and reduces the IC lifetime. The NCV4254C allows a negative supply voltage. However, several small currents are flowing into the IC. For details see electrical characteristics table and typical performance graphs. The thermal protection circuit is not operating during reverse polarity condition. The NCV4254C tracking regulator is self−protected with internal thermal shutdown and internal current limit. Typical characteristics are shown in Figure 3 to Figure 18. Input Decoupling (Cin) A ceramic or tantalum 0.1 mF capacitor is recommended and should be connected close to the NCV4254C package. Higher capacitance and lower ESR will improve the overall line and load transient response. If extremely fast input voltage transients are expected then appropriate input filter must be used in order to decrease rising and/or falling edges below 50 V/ms for proper operation. The filter can be composed of several capacitors in parallel. Thermal Considerations As power in the NCV4254C increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. When the NCV4254C has good thermal conductivity through the PCB, the junction temperature will be relatively low with high power applications. The maximum dissipation the NCV4254C can handle is given by: Output Decoupling (Cout) The output capacitor for the NCV4254C is required for stability. Without it, the regulator output will oscillate. Actual size and type may vary depending upon the application load and temperature range. Capacitor effective series resistance (ESR) is also a factor in the IC stability. Worst−case is determined at the minimum ambient temperature and maximum load expected. The output capacitor can be increased in size to any desired value above the minimum. One possible purpose of this would be to maintain the output voltage during brief conditions of negative input transients that might be characteristic of a particular system. The capacitor must also be rated at all ambient temperatures expected in the system. To maintain regulator stability down to −40_C, a capacitor rated at that temperature must be used. P D(MAX) + ƪTJ(MAX) * TAƫ (eq. 1) R qJA Since TJ is not recommended to exceed 150°C, then the NCV4254C (SOIC−8 EP) soldered on 645 mm2, 1 oz copper area, FR4 can dissipate up to 1.667 W when the ambient temperature (TA) is 25°C. See Figure 19 and 20 for RqJA versus PCB Cu area. The power dissipated by the NCV4254C can be calculated from the following equations: P D [ V inǒI q@I outǓ ) I out ǒV in * V outǓ (eq. 2) or Tracking Regulator V in(MAX) [ The output voltage Vout is controlled by comparing it to the voltage applied at pin EN/REF and driving a PNP pass transistor accordingly. The control loop stability depends on the output capacitor Cout, the load current, the chip temperature and the poles/zeros introduced by the integrated circuit. Protection circuitry prevents the IC as well as the application from destruction in case of catastrophic events. These safeguards contain output current limitation, reverse polarity protection as well as thermal shutdown in case of over temperature. In order to avoid excessive power dissipation that could never be handled by the pass element and the package, the maximum output current is decreased at high input voltages. The over temperature protection circuit prevents the IC from immediate destruction under fault conditions (e.g. Output continuously short−circuited) by reducing the output current. A thermal balance below 200°C junction temperature is established. Please note that a junction P D(MAX) ) ǒV out I outǓ I out ) I q (eq. 3) RqJA, THERMAL RESISTANCE (°C/W) 160 140 1 Layer 120 100 80 4 Layer 60 40 20 0 0 100 200 300 400 500 600 PCB Cu AREA (mm2) Figure 19. RqJA vs. PCB CU Area (SOIC−8 Package) www.onsemi.com 9 700 800 NCV4254C Hints RqJA, THERMAL RESISTANCE (°C/W) 140 Vin and GND printed circuit board traces should be as wide as possible. When the impedance of these traces is high, there is a chance to pick up noise or cause the regulator to malfunction. Place external components, especially the output capacitor, as close as possible to the NCV4254C and make traces as short as possible. The NCV4254C is not developed in compliance with ISO26262 standard. If application is safety critical then the below application diagram shown in Figure 21 or 22 can be used. 120 100 1 Layer 80 60 4 Layer 40 20 0 0 100 200 300 400 PCB Cu AREA 500 600 700 800 (mm2) Figure 20. RqJA vs. PCB CU Area (SOIC−8 EP Package) VBAT VIN VDD VOUT COUT1 1μF CIN1 100nF Main supply e.g. VCC RESET Voltage Supervisor NCV8772(C) I/O Microprocessor (e.g. NCV30X, NCV809) GND OFF ON EN I/O RO I/O GND VOUT VIN CIN2 100nF COUT2 2.2μF NCV4254C REF/EN GND VOUT ADJ Figure 21. Application Diagram for ADJ version www.onsemi.com 10 NCV4254C VBAT VIN VDD VOUT COUT1 1μF CIN1 100nF Main supply e.g. VCC RESET Voltage Supervisor NCV8772(C) I/O Microprocessor (e.g. NCV30X, NCV809) GND OFF ON EN I/O RO I/O GND CIN2 100nF VOUT VOUT VIN COUT2 2.2μF NCV4254C REF/EN GND ST RST 10kΩ Figure 22. Application Diagram for ST version www.onsemi.com 11 I/O NCV4254C CIRCUIT DESCRIPTION ENABLE Function Output Voltage By pulling the VREF/EN lead below 0.4 V typically, the IC is disabled and enters a Stand−by mode where the device draws less then 5 μA from supply. When the VREF/EN lead is greater then 1.75 V, VOUT tracks the VREF/EN lead normally. The output is capable of supplying 70 mA to the load while configured as a similar (Figure 26), lower (Figure 27) or higher (Figure 25) voltage as the reference lead. The Adj lead acts as the inverting terminal of the op amp and the VREF lead as the non−inverting. The device can also be configured as a high−side driver as displayed in Figure 28. STATUS Output The status output is used as the power on indicator to the microcontroller. This signal indicates when the output voltage is suitable for reliable operation of the sensor. It pulls low when the output is not considered to be ready. ST is pulled up to VREF (Figure 23) or Vout (Figure 24) by an external resistor, typically 10 kW. V IN V in C in 100 nF V REF C REF/EN C in 100nF V REF C in 100 nF V REF R 1 C REF/EN 10nF R ST 10kΩ C in 100 nF C REF/EN 10nF V out + V ADJ R1 V REF C REF/EN 10nF C out 2.2mF R2 R 1) 1 R2 ǒ R2 R1 ) R2 V out Ǔ C out 2.2mF NCV4254C REF/EN GND V out ADJ Figure 28. Adjust Version Application Circuit: High−Side Driver ADJ ǒ V in C in 100 nF V out V out REF/EN GND ADJ Figure 27. Adjust Version Application Circuit: Output Voltage Lower Than the Reference Voltage V IN NCV4254C V REF GND C REF/EN 10nF I/O ST V in C out 2.2mF NCV4254C V out + V REF C out 2.2mF V out V out REF/EN R2 Figure 24. Status Version Application Circuit: Status to Output Voltage V IN V in V out V out REF/EN GND V out + V REF V IN R ST 10 kW NCV4254C ADJ Figure 26. Adjust Version Application Circuit: Output Voltage Equal to the Reference Voltage Figure 23. Status Version Application Circuit: Status to Reference Voltage C in 100 nF REF/EN GND CREF/EN 10nF V REF V in Cout 2.2mF I/O ST 10 nF V IN Vout Vout NCV4254C VREF C out 2.2 mF NCV4254C GND Vin V out V out REF/EN VIN Ǔ Figure 25. Adjust Version Application Circuit: Output Voltage Higher Than the Reference Voltage www.onsemi.com 12 NCV4254C ORDERING INFORMATION Version Package Shipping† NCV4254CDAJR2G ADJ 2500 / Tape & Reel NCV4254CDSTR2G ST SOIC−8 (Pb−Free) NCV4254CPDAJR2G ADJ 2500 / Tape & Reel NCV4254CPDSTR2G ST SOIC−8 EP (Pb−Free) Device †For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 13 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 EP CASE 751AC ISSUE D 8 1 SCALE 1:1 DATE 02 APR 2019 GENERIC MARKING DIAGRAM* 8 XXXXX AYWWG G 1 DOCUMENT NUMBER: DESCRIPTION: XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package 98AON14029D SOIC−8 EP *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present and may be in either location. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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