NCV47710
LDO Regulator - Adjustable
Current Limit, 3.3 V Logic
5 V to 20 V
The NCV47710 is a 350 mA output current integrated low dropout
regulator designed for use in harsh automotive environments. It
includes wide operating temperature and input voltage ranges. The
device is offered with adjustable voltage versions available in 6%
output voltage accuracy. It has a high peak input voltage tolerance and
reverse input voltage protection. It also provides overcurrent
protection, overtemperature protection and enable for control of the
state of the output voltage. The integrated current sense feature
provides diagnosis and system protection functionality. The current
limit of the device is adjustable by resistor connected to CSO pin.
Voltage on CSO pin is proportional to output current.
Features
• Adjustable Voltage Version (from 5 V to 20 V) ± 6% Output Voltage
•
•
•
•
for ±3% Output Voltage Accuracy see NCV47711 Specification
Enable Input (3.3 V Logic Compatible Thresholds)
for 5 V Logic Compatible Thresholds see NCV47700 or
NCV47701 Specification
Adjustable Current Limit (from 10 mA to 350 mA) with 10%
accuracy
Protection Features:
♦ Current Limitation
♦ Thermal Shutdown
♦ Reverse Input Voltage
This is a Pb−Free Device
Typical Applications
•
•
•
•
Audio and Infotainment System
Instrument Cluster
Navigation
Satellite Radio
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MARKING
DIAGRAMS
8
SOIC−8
Exposed Pad
PD SUFFIX
CASE 751AC
8
1
47710
ALYW
G
1
8
SOIC−8
D SUFFIX
CASE 751
8
1
1
A
L
Y
W
G
47710
ALYW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
ADJ
1
8
Vout
GND
EN
NC
NC
CSO
Vin
SOIC−8 EP, SOIC−8
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
C in
V out
V in
Cb*
1 mF
NCV47710
EN
GND
R1
ADJ
CSO
C CSO
1 mF
C out
R2
22 mF
R CSO
*Required if usage of low ESR output capacitor Cout is demand, see
Regulator Stability Considerations section.
Figure 1. Application Schematic
© Semiconductor Components Industries, LLC, 2012
September, 2019 − Rev. 2
1
Publication Order Number:
NCV47710/D
NCV47710
Vin
Vout
VOLTAGE
REFERENCE
VREF1
VREF2
ENABLE
EN
SATURATION
PROTECTION
THERMAL
SHUTDOWN
PASS DEVICE
AND
CURRENT MIRROR
ICSO = Iout / 100
SP
TSD
+
-
SP
GND
+
VREF2
2.55 V
VREF1
1.275 V
ADJ
-
TSD
Figure 2. Simplified Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
SOIC−8 EP
Pin No.
SOIC−8
Pin Name
1
1
ADJ
Adjustable Voltage Setting Input. See Application Section for more details.
2
2
GND
Power Supply Ground.
3
3
EN
4
4
CSO
5
5
Vin
Positive Power Supply Input.
6
6
NC
Not Connected
7
7
NC
Not Connected
8
8
Vout
Regulated Output Voltage.
EPAD
−
EPAD
Description
Enable Input; low level disables the IC.
Current Sense Output, Current Limit setting and Output Current value information.
See Application Section for more details.
Connect to ground potential or leave unconnected.
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2
CSO
NCV47710
ABSOLUTE MAXIMUM RATINGS (Note 1)
Symbol
Rating
Min
Max
Unit
Input Voltage
Vin
−42
45
V
Enable Input Voltage
VEN
−0.3
7.0
V
Adjustable Input Voltage
VADJ
−0.3
10
V
CSO Voltage
VCSO
−0.3
7.0
V
Vout
−1
40
V
Junction Temperature
TJ
−40
150
°C
Storage Temperature
TSTG
−55
150
°C
Output Voltage
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
ESD CAPABILITY (Note 2)
Symbol
Min
Max
Unit
ESD Capability, Human Body Model
ESDHBM
−2
2
kV
ESD Capability, Machine Model
ESDMM
−200
200
V
Rating
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (JS−001−2010)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes < 50mm2 due to
the inability of a small package body to acquire and retain enough charge to meet the minimum CDM discharge current waveform
characteristic defined in JEDEC JS−002−2014.
LEAD SOLDERING TEMPERATURE AND MSL (Note 3)
Symbol
Rating
Moisture Sensitivity Level
SOIC−8 EP
SOIC−8
Min
MSL
Max
2
1
Unit
−
3. For more information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Thermal Characteristics, SOIC−8 EP (single layer PCB)
Thermal Resistance, Junction−to−Air (Note 4)
Thermal Reference, Junction−to−Lead (Note 4)
RθJA
RψJL
70
19
Thermal Characteristics, SOIC−8 EP (4 layers PCB)
Thermal Resistance, Junction−to−Air (Note 4)
Thermal Reference, Junction−to−Lead (Note 4)
RθJA
RψJL
29
12
Thermal Characteristics, SOIC−8 (single layer PCB)
Thermal Resistance, Junction−to−Air (Note 4)
Thermal Reference, Junction−to−Lead (Note 4)
RθJA
RψJL
121
42
Thermal Characteristics, SOIC−8 (4 layers PCB)
Thermal Resistance, Junction−to−Air (Note 4)
Thermal Reference, Junction−to−Lead (Note 4)
RθJA
RψJL
77
52
Unit
°C/W
°C/W
°C/W
°C/W
4. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate. Single layer − according to JEDEC51.3,
4 layers − according to JEDEC51.7.
RECOMMENDED OPERATING RANGES
Symbol
Min
Max
Unit
Input Voltage (Note 5)
Rating
Vin
5.5
40
V
Output Current Limit (Note 6)
ILIM
10
350
mA
TJ
−40
150
°C
Vout_nom
5.0
20
V
CCSO
1.0
4.7
mF
Junction Temperature
Nominal Output Voltage
Current Sense Output (CSO) Capacitor
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Minimum Vin = 5.5 V or (Vout_nom + 0.5 V), whichever is higher.
6. Corresponding RCSO is in range from 25 kW down to 728 W.
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3
NCV47710
ELECTRICAL CHARACTERISTICS Vin = 13.5 V, VEN = 3.3 V, RCSO = 0 W, CCSO = 1 mF, Cin = 1 mF, Cout = 22 mF, ESR = 1.5 W, Min
and Max values are valid for temperature range −40°C ≤ TJ ≤ 150°C unless otherwise noted and are guaranteed by test design or
statistical correlation. Typical values are referenced to TJ = 25°C.
Test Conditions
Symbol
Min
Typ
Max
Unit
Output Voltage (Accuracy %)
Vin = (Vout_nom + 1 V) to 40 V, Iout = 5 mA to 350 mA
Vout
−6
−
6
%
Line Regulation
Vin = (Vout_nom + 1 V) to (Vout_nom + 20V), Iout = 5mA
Regline
−
0.1
2.0
%
Load Regulation
Iout = 5 mA to 350 mA
Regload
−
0.14
2.8
%
Dropout Voltage (Note 7)
Iout = 150 mA, VDO = Vin − Vout
VDO
−
250
500
mV
IDIS
−
−
−
85
10
−
mA
nA
Parameter
REGULATOR OUTPUT
DISABLE AND QUIESCENT CURRENTS
Disable Current
VEN = 0 V
VEN = 0 V, TJ = 25°C
Quiescent Current, Iq = Iin − Iout
Iout = 1 mA, Vin = (Vout_nom + 8.5 V)
Iq
−
150
230
mA
Quiescent Current, Iq = Iin − Iout
Iout = 350 mA, Vin = (Vout_nom + 8.5 V)
Iq
−
23
50
mA
Vout = 0.9 x Vout_nom, Vin = (Vout_nom + 8.5 V)
ILIM
400
−
−
mA
Power Supply Ripple Rejection
f = 100 Hz, 0.5 Vp−p, Iout = 5 mA, Cin = none
PSRR
−
70
−
dB
Output Noise Voltage
f = 10 Hz to 100 kHz, Cb = 10 nF, Iout = 5 mA
Vn
−
100
−
mVrms
0.99
−
1.85
1.9
−
2.31
CURRENT LIMIT PROTECTION
Current Limit
PSRR & NOISE
ENABLE
Vth(EN)
V
Enable Input Threshold Voltage
Logic Low (OFF)
Logic High (ON)
Vout v 0.1 V
Vout w 0.9 x Vout_nom
Enable Input Current
VEN = 3.3 V
IEN
2.0
9.0
20
mA
Turn On Time from Enable ON to
90% of Vout_nom
Iout = 100 mA, Cb = 10 nF, R1 = 82 kW,
R2 = 27 kW
ton
−
1.6
−
ms
CSO Voltage Level at Current
Limit
Vout = 0.9 x Vout_nom, (Vout_nom = 5 V)
RCSO = 1 kW
VCSO_Ilim
2.346
(−8 %)
2.55
2.754
(+8 %)
V
CSO Transient Voltage Level
CCSO = 4.7 mF, RCSO = 1 kW, Iout pulse from 10 mA
to 350 mA, tr = 1 ms
VCSO
−
−
3.0
V
CSO Current to Output Current
Ratio (Note 8)
VCSO = 2 V, Iout = 10 mA to 350 mA,
(Vout_nom = 5V)
ICSO/Iout
−
(−10%)
(1/100)
−
(+10%)
−
CSO Current at No Load Current
VCSO = 0 V, Iout = 0 mA, (Vout_nom = 5 V)
ICSO_off
−
−
10
mA
Vin = 12 V, Vout = 14 V
Iout_rev
−40
−25
−
mA
TSD
150
−
195
°C
OUTPUT CURRENT SENSE
REVERSE CURRENT
Reverse Current (Note 9)
THERMAL SHUTDOWN
Thermal Shutdown Temperature
Iout = 5 mA
7. Measured when the output voltage Vout has dropped −2% from the nominal value obtained at Vin = Vout_nom + 8.5 V.
8. Not guaranteed in dropout.
9. Values based on design and/or characterization.
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4
NCV47710
TYPICAL CHARACTERISTICS
0.40
Vin = 13.5 V
Iout = 5 mA
1.31
1.30
1.29
1.28
1.27
1.26
1.25
1.24
−40 −20
0.35
Iq, QUIESCENT CURRENT (mA)
VREF1, REFERENCE VOLTAGE (V)
1.32
0.30
0.25
0.20
0.15
0.10
0.05
0
0
20 40 60 80 100 120 140 160
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Reference Voltage vs. Temperature
0
5
10
15
20
25
30
Vin, INPUT VOLTAGE (V)
35
40
Figure 4. Quiescent Current vs. Input Voltage
6
2
TJ = 25°C
Iout = 5 mA
Vout_nom = 5 V
5
TJ = 25°C
Rout = 4.7 kW
Vout_nom = 5 V
1
Iin, INPUT CURRENT (mA)
Vout, OUTPUT VOLTAGE (V)
TJ = 25°C
Iout = 5 mA
Vout_nom = 5 V
4
3
2
1
0
−1
−2
−3
−4
−5
−6
−7
0
0
1
2
3
5
7
4
6
Vin, INPUT VOLTAGE (V)
9
8
−8
−45 −40 −35 −30 −25 −20 −15 −10 −5
Vin, INPUT VOLTAGE (V)
10
ILIM, OUTPUT CURRENT LIMIT (mA)
VDO, DROPOUT VOLTAGE (mV)
800
Vin = 13.5 V
Vout_nom = 5 V
600
TJ = 150°C
500
400
TJ = 25°C
300
200
TJ = −40°C
100
0
0
50
100
150
200
250
Iout, OUTPUT CURRENT (mA)
300
5
10
40
45
Figure 6. Input Current vs. Input Voltage
(Reverse Input Voltage)
Figure 5. Output Voltage vs. Input Voltage
700
0
350
Figure 7. Dropout vs. Output Current
1400
Vout = 4.5 V
Vout_nom = 5 V
1300
TJ = −40°C
1200
1100
TJ = 25°C
1000
900
TJ = 150°C
800
700
600
0
5
10
15
20
25
30
35
Vin, INPUT VOLTAGE (V)
Figure 8. Output Current Limit vs. Input Voltage
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5
NCV47710
TYPICAL CHARACTERISTICS
3.0
Vout = 5 V to 20 V
TJ = 25°C
350
Vout = 5 V to 20 V
TJ = 25°C
ILIM = 10 mA to 350 mA
2.5
300
2.0
250
VCSO, (V)
ILIM, OUTPUT CURRENT LIMIT (mA)
400
200
150
1.5
1.0
100
0.5
50
0
2
0
4
6
0
8 10 12 14 16 18 20 22 24 26 28
RCSO, (kW)
0
Figure 9. Output Current Limit vs. RCSO
104
103
Iout/ICSO, OUTPUT CURRENT TO
CSO CURRENT RATIO
Iout/ICSO, OUTPUT CURRENT TO
CSO CURRENT RATIO
105
TJ = 25°C
Vin = 13.5 V
102
101
100
99
98
97
96
95
1
10
100
Iout, OUTPUT CURRENT (mA)
100
95
90
85
80
75
70
65
TJ = 25°C
Vin = 4.5 V
Vout_nom = 5 V
60
55
50
1
1000
Figure 11. Output Current to CSO Current Ratio
vs. Output Current
1000
10
100
Iout, OUTPUT CURRENT (mA)
Figure 12. Output Current to CSO Current Ratio
vs. Output Current in Dropout
25
5.0
TJ = 25°C
Vin = 13.5 V
20
Iq, QUIESCENT CURRENT (mA)
Iq, QUIESCENT CURRENT (mA)
125
Figure 10. Output Current (% of ILIM) vs. CSO
Voltage
105
15
10
5
0
25
50
75
100
Iout, OUTPUT CURRENT (% of ILIM)
0
50
100
150
200
250
Iout, OUTPUT CURRENT (mA)
300
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
350
Figure 13. Quiescent Current vs. Output Current
(High Load)
TJ = 25°C
Vin = 13.5 V
4.5
0
10
20
30 40 50 60 70
80
Iout, OUTPUT CURRENT (mA)
90
100
Figure 14. Quiescent Current vs. Output Current
(Low Load)
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NCV47710
TYPICAL CHARACTERISTICS
TJ = 25°C
Vin = 13.5 V
Vout_nom = 5 V
Iout = 5 mA
2500
80
75
PSRR (dB)
2000
90
85
Noise 10 Hz − 100 kHz
Vn = 100.6 mV
1500
1000
70
65
60
55
40
35
0
10
100
1000
FREQUENCY (Hz)
10000
100000
Iout = 5 mA
50
45
500
30
10
100
Unstable Region
10
100
1000
10000
FREQUENCY (Hz)
TJ = 25°C
Vin = Vout_nom + 8.5 V
Cout = 10−100 mF, Cb = none
Vout = 20 V
0.1
0.01
Unstable Region
0
50
100000 1000000
Figure 16. PSRR vs. Frequency
Vout = 5 V
1
Iout = 150 mA
TJ = 25°C
Vin = 13.5 V
Vout_nom = 5 V
Figure 15. Output Noise Density vs. Frequency
Cout, ESR STABILITY REGION (W)
OUTPUT NOISE DENSITY (nV/√Hz)
3000
100
150
200
250
Iout, OUTPUT CURRENT (mA)
300
350
Figure 17. Cout ESR Stability Region vs. Output
Current
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NCV47710
DEFINITIONS
General
reduces its internal bias and shuts off the output, this term is
called the disable current (IDIS).
All measurements are performed using short pulse low duty
cycle techniques to maintain junction temperature as close
as possible to ambient temperature.
Current Limit
Current Limit is value of output current by which output
voltage drops below 90% of its nominal value.
Output Voltage
The output voltage parameter is defined for specific
temperature, input voltage and output current values or
specified over Line, Load and Temperature ranges.
PSRR
Power Supply Rejection Ratio is defined as ratio of output
voltage and input voltage ripple. It is measured in decibels
(dB).
Line Regulation
The change in output voltage for a change in input voltage
measured for specific output current over operating ambient
temperature range.
Line Transient Response
Typical output voltage overshoot and undershoot response
when the input voltage is excited with a given slope.
Load Regulation
Load Transient Response
The change in output voltage for a change in output current
measured for specific input voltage over operating ambient
temperature range.
Typical output voltage overshoot and undershoot response
when the output current is excited with a given slope
between low−load and high−load conditions.
Dropout Voltage
Thermal Protection
The input to output differential at which the regulator output
no longer maintains regulation against further reductions in
input voltage. It is measured when the output voltage Vout
has dropped −2% from the nominal value obtained at Vin =
Vout_nom + 8.5 V. The junction temperature, load current,
and minimum input supply requirements affect the dropout
level.
Internal thermal shutdown circuitry is provided to protect
the integrated circuit in the event that the maximum junction
temperature is exceeded. When activated at typically 175°C,
the regulator turns off. This feature is provided to prevent
failures from accidental overheating.
Maximum Package Power Dissipation
The power dissipation level is maximum allowed power
dissipation for particular package or power dissipation at
which the junction temperature reaches its maximum
operating value, whichever is lower.
Quiescent and Disable Currents
Quiescent Current (Iq) is the difference between the input
current (measured through the LDO input pin) and the
output load current. If Enable pin is set to LOW the regulator
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NCV47710
APPLICATIONS INFORMATION
Circuit Description
Calculating Bypass Capacitor
The NCV47710 is an integrated low dropout regulator
that provides a regulated voltage at 350 mA to the output. It
is enabled with an input to the enable pin. The regulator
voltage is provided by a PNP pass transistor controlled by an
error amplifier with a bandgap reference, which gives it the
lowest possible dropout voltage. The output current
capability is 350 mA, and the base drive quiescent current is
controlled to prevent oversaturation when the input voltage
is low or when the output is overloaded. The integrated
current sense feature provides diagnosis and system
protection functionality. The current limit of the device is
adjustable by resistor connected to CSO pin. Voltage on
CSO pin is proportional to output current. The regulator is
protected by both current limit and thermal shutdown.
Thermal shutdown occurs above 150°C to protect the IC
during overloads and extreme ambient temperatures.
If usage of low ESR ceramic capacitors is demanded,
connect the bypass capacitor Cb between Adjustable Input
pin and Vout pin according to Applications circuit at
Figure 1. Parallel combination of bypass capacitor Cb with
the feedback resistor R1 contributes in the device transfer
function as an additional zero and affects the device loop
stability, therefore its value must be optimized. Attention to
the Output Capacitor value and its ESR must be paid. See
also Stability in High Speed Linear LDO Regulators
Application Note, AND8037/D for more information.
Optimal value of bypass capacitor is given by following
expression:
Cb +
1
2
p
fz
(eq. 1)
R1
where
R1 − the upper feedback resistor
fz − the frequency of the zero added into the device
transfer function by R1 and Cb external components.
Set the R1 resistor according to output voltage requirement.
Chose the fz with regard on the output capacitance Cout, refer
to the table below.
Regulator
The error amplifier compares the reference voltage to a
sample of the output voltage (Vout) and drives the base of a
PNP series pass transistor via a buffer. The reference is a
bandgap design to give it a temperature−stable output.
Saturation control of the PNP is a function of the load current
and input voltage. Oversaturation of the output power
device is prevented, and quiescent current in the ground pin
is minimized.
Cout (mF)
fZ range (kHz)
Regulator Stability Considerations
10
22
47
100
3.3−48.2
1.5−33
1.5−33
2.2−22
Ceramic capacitors and its part numbers listed bellow
have been used as low ESR output capacitors Cout from the
table above to define the frequency ranges of additional zero
required for stability:
The input capacitor (Cin) is necessary to stabilize the input
impedance to avoid voltage line influences. The output
capacitor (Cout) helps determine three main characteristics
of a linear regulator: startup delay, load transient response
and loop stability. The capacitor value and type should be
based on cost, availability, size and temperature constraints.
The aluminum electrolytic capacitor is the least expensive
solution, but, if the circuit operates at low temperatures
(−25°C to −40°C), both the value and ESR of the capacitor
will vary considerably. The capacitor manufacturer’s data
sheet usually provides this information. The value for the
output capacitor Cout, shown in Figure 1 should work for
most applications; see also Figure 17 for output stability at
various load and Output Capacitor ESR conditions. Stable
region of ESR in Figure 17 shows ESR values at which the
LDO output voltage does not have any permanent
oscillations at any dynamic changes of output load current.
Marginal ESR is the value at which the output voltage
waving is fully damped during four periods after the load
change and no oscillation is further observable.
ESR characteristics were measured with ceramic
capacitors and additional series resistors to emulate ESR.
Low duty cycle pulse load current technique has been used
to maintain junction temperature close to ambient
temperature.
GRM31CR71C106KAC7 (10 mF, 16 V, X7R, 1206)
GRM32ER71C226KE18 (22 mF, 16 V, X7R, 1210)
GRM32ER61C476ME15 (47 mF, 16 V, X5R, 1210)
GRM32ER60J107ME20 (100 mF, 6.3 V, X5R, 1210)
Enable Input
The enable pin is used to turn the regulator on or off. By
holding the pin down to a voltage less than 0.99 V, the output
of the regulator will be turned off. When the voltage on the
enable pin is greater than 2.31 V, the output of the regulator
will be enabled to power its output to the regulated output
voltage.
Setting the Output Voltage
The output voltage range can be set between 5 V and 20 V.
This is accomplished with an external resistor divider
feeding back the voltage to the IC back to the error amplifier
by the voltage adjust pin ADJ. The internal reference voltage
is set to a temperature stable reference (VREF1) of 1.275 V.
The output voltage is calculated from the following formula.
Ignoring the bias current into the ADJ pin:
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9
NCV47710
ǒ
V out + V REF1 1 )
Ǔ
R1
(eq. 2)
R2
P D(MAX) +
Use R2 < 50 kW to avoid significant voltage output errors
due to ADJ bias current.
Designers should consider the tolerance of R1 and R2 during
the design phase.
The output current limit can be set between 10 mA and
350 mA by external resistor RCSO (see Figure 1). Capacitor
CCSO of 1 mF in parallel with RCSO is required for stability
of current limit control circuitry (see Figure 1).
ǒ
100
I LIM +
1
R CSO +
100
1
Ǔ
1
100
2.55
R CSO
2.55
I LIM
(eq. 6)
R qJA
Since TJ is not recommended to exceed 150°C, then the
NCV47710 soldered on 645 mm2, 1 oz copper area, FR4
can dissipate up to 1.8 W (SOIC−8 EP) or 1 W (SOIC−8) and
up to 4.3 W (SOIC−8 EP) or 1.6 W (SOIC−8) for 4 layers
PCB (all layers are 1 oz) when the ambient temperature (TA)
is 25°C. See Figure 18 for RthJA versus PCB area. The power
dissipated by the NCV47710 can be calculated from the
following equations:
Setting the Output Current Limit
V CSO + I out R CSO
ƪTJ(MAX) * TAƫ
P D + V inǒI q@I outǓ ) I outǒV in * V outǓ
(eq. 7)
or
(eq. 3)
V in(MAX) [
(eq. 4)
P D(MAX) ) ǒV out
I outǓ
(eq. 8)
I out ) I q
Hints
(eq. 5)
Vin and GND printed circuit board traces should be as
wide as possible. When the impedance of these traces is
high, there is a chance to pick up noise or cause the regulator
to malfunction. Place external components, especially the
output capacitor, as close as possible to the NCV47710 and
make traces as short as possible.
Where
RCSO
− current limit setting resistor
VCSO
− voltage at CSO pin proportional to Iout
ILIM
− current limit value
Iout
− output current actual value
CSO pin provides information about output current actual
value. The CSO voltage is proportional to output current
according to Equation 3.
Once output current reaches its limit value (ILIM) set by
external resistor RCSO than voltage at CSO pin is typically
2.55 V. Calculations of ILIM or RCSO values can be done
using equations Equation 4 and Equation 5, respectively.
RqJA, THERMAL RESISTANCE (°C/W)
220
Thermal Considerations
As power in the NCV47710 increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient temperature
affect the rate of junction temperature rise for the part. When
the NCV47710 has good thermal conductivity through the
PCB, the junction temperature will be relatively low with
high power applications. The maximum dissipation the
NCV47710 can handle is given by:
200
180
160
1 oz
140
SO−8 single layer PCB
2 oz
120
100
80
2 oz
1 oz
1 oz
2 oz
SO−8 EP single layer PCB
60 SO−8 4 layers PCB
1 oz 2 oz
40 SO−8 EP 4 layers PCB
20
0
100
200
300
400
500
600
700
COPPER HEAT SPREADER AREA (mm2)
Figure 18. Thermal Resistance vs. PCB Copper Area
ORDERING INFORMATION
Device
Output Voltage
Marking
Package
Shipping†
NCV47710PDAJR2G
Adjustable
47710
SOIC−8 EP
(Pb−Free)
2500 / Tape & Reel
NCV47710DAJR2G
Adjustable
47710
SOIC−8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 EP
CASE 751AC
ISSUE D
8
1
SCALE 1:1
DATE 02 APR 2019
GENERIC
MARKING DIAGRAM*
8
XXXXX
AYWWG
G
1
DOCUMENT NUMBER:
DESCRIPTION:
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
98AON14029D
SOIC−8 EP
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”, may
or may not be present and may be in either
location. Some products may not follow the
Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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