NDS332P

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Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. June 1997 NDS332P P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package. -1 A, -20 V, RDS(ON) = 0.41 Ω @ VGS= -2.7 V RDS(ON) = 0.3 Ω @ VGS = -4.5 V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.0V. Proprietary package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. Compact industry standard SOT-23 surface Mount package. ________________________________________________________________________________ D G AEsolute Maximum Ratings T A = 25°C unless otherwise noted Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage - Continuous ID Drain Current - Continuous PD Maximum Power Dissipation (Note 1a) - Pulsed NDS332P Units -20 V ±8 V -1 A -10 (Note 1a) (Note 1b) TJ,TSTG S Operating and Storage Temperature Range 0.5 W 0.46 -55 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) RθJC Thermal Resistance, Junction-to-Case (Note 1) © 1997 Fairchild Semiconductor Corporation 250 °C/W 75 °C/W NDS332P Rev. E Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min -20 Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA IDSS Zero Gate Voltage Drain Current VDS = -16 V, VGS = 0 V V TJ = 55°C -1 µA -10 µA IGSS Gate - Body Leakage Current VGS = 8 V, VDS= 0 V 100 nA IGSS Gate - Body Leakage Current VGS = -8 V, VDS= 0 V -100 nA V ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA TJ =125°C RDS(ON) Static Drain-Source On-Resistance -0.4 -0.6 -1 -0.3 -0.45 -0.8 0.35 0.41 0.5 0.74 0.26 0.3 VGS = -2.7 V, ID = -1 A TJ =125°C VGS = -4.5 V, ID = -1.1 A ID(ON) gFS On-State Drain Current Forward Transconductance VGS = -2.7 V, VDS = -5 V -1.5 VGS = -4.5 V, VDS = -5 V -2.5 Ω A VDS = -5 V, ID= -1 A 2.2 S VDS = -10 V, VGS = 0 V, f = 1.0 MHz 195 pF 105 pF 40 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) tf Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = -6 V, ID = -1 A, VGS = -4.5 V, RGEN = 6 Ω 8 15 ns 30 45 ns Turn - Off Delay Time 25 45 ns Turn - Off Fall Time 27 45 ns 3.7 5 nC VDS = -5 V, ID = -1 A, VGS = -4.5 V 0.5 nC 0.9 nC NDS332P Rev. E Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units -0.42 A -1.2 V DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Source Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -0.42 A (Note 2) -0.75 Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. PD (t) = T J −T A R θJA (t) = T J −T A R θJC +R θCA (t) = I 2D(t) × R DS(ON)@T J Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper. b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper. 1a 1b Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDS332P Rev. E Typical Electrical Characteristics -2.5 -3.5 -3.0 -2 -2.7 RDS(ON) , NORMALIZED I D , DRAIN-SOURCE CURRENT (A) VGS = -4.5V -2.0 -1.5 -1 -1.5 -0.5 0 DRAIN-SOURCE ON-RESISTANCE 1.8 -2.5 1.6 1.4 VGS =-2.0V 1.2 -2.5 1 -0.5 V DS -1 -1.5 -2 -2.5 , DRAIN-SOURCE VOLTAGE (V) -3.0 -3.5 0.8 -4.5 0.6 0.4 0 -3 0 -2.5 -3 1.8 R DS(on), NORMALIZED 1.6 1.4 1.2 1 0.8 0.6 0.4 -50 -25 0 25 50 75 100 T , JUNCTION TEMPERATURE (°C) 125 DRAIN-SOURCE ON-RESISTANCE I D = -1A V GS = -2.7 V GS = -2.7 V 1.4 1.2 25°C 1 -55°C 0.8 0.6 0 -0.5 25°C V DS = - 3V T = -55°C J 125°C -0.9 -0.6 -0.3 -1 V GS -1.25 -1.5 -1.75 , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. -2 GATE-SOURCE THRESHOLD VOLTAGE (V) -1.5 -0.75 -2.5 -3 Figure 4. On-Resistance Variation with Drain Current and Temperature. Figure 3. On-Resistance Variation with Temperature. 0 -0.5 -1 -1.5 -2 I , DRAIN CURRENT (A) D J -1.2 TJ = 125°C 1.6 0.4 150 Vth , NORMALIZED R DS(ON) , NORMALIZED -1 -1.5 -2 I , DRAIN CURRENT (A) Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.8 DRAIN-SOURCE ON-RESISTANCE -0.5 D Figure 1. On-Region Characteristics. I D , DRAIN CURRENT (A) -2.7 1.15 V DS = VGS 1.1 I D = -250µA 1.05 1 0.95 0.9 0.85 0.8 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 150 Figure 6. Gate Threshold Variation with Temperature. NDS332P Rev.E Typical Electrical Characteristics (continued) 1 VGS =0V -I , REVERSE DRAIN CURRENT (A) I D = -250µA 1.08 1.04 1 0.96 0.1 0.05 TJ = 125°C 0.01 0.92 -50 -25 0 T J 25 50 75 100 , JUNCTION TEMPERATURE (°C) 125 -55°C 0.001 0.0001 150 0 0.2 0.4 0.6 0.8 -V SD , BODY DIODE FORWARD VOLTAGE (V) 1 Figure 8. Body Diode ForwardVoltageVariation with Source Current and Temperature. Figure 7. Breakdown Voltage Variation with Temperature. 5 -V GS , GATE-SOURCE VOLTAGE (V) 500 300 CAPACITANCE (pF) 25°C S BV DSS , NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 1.12 VDS = -5V I D = -1A -10V 4 200 Ciss 100 Coss -15V 3 2 50 30 20 0.1 Crss f = 1 MHz VGS = 0V 0.2 -V DS 0.5 1 2 5 , DRAIN TO SOURCE VOLTAGE (V) 10 1 0 20 Figure 9. Capacitance Characteristics. 1 ton t d(on) t d(off) 90% V OUT VOUT 10% 10% DUT G 5 tf 90% D R GEN 4 t off tr RL VIN 2 3 Q g , GATE CHARGE (nC) Figure 10. Gate Charge Characteristics. VDD VGS 0 90% V IN 50% 50% S 10% PULSE WIDTH Figure 11. Switching Test Circuit. INVERTED Figure 12. Switching Waveforms. NDS332PRev. E 20 4 VDS =- 5V -I D , DRAIN CURRENT (A) 3 25°C 125°C 2 1m 10 TJ = -55°C 1 5 N) S(O RD 2 g 100 -0.5 -1 -1.5 -2 I D, DRAIN CURRENT (A) -2.5 10s DC V GS = -2.7V SINGLE PULSE RθJA = See Note 1b TA = 25°C 0.01 0.1 -3 ms 1s 0.1 0.2 0.5 1 2 5 10 -VDS , DRAIN-SOURCE VOLTAGE (V) 20 Figure 13. Transconductance Variation with Drain Current and Temperature. Figure 14. Maximum Safe Operating Area. 1 1.4 -ID , STEADY-STATE DRAIN CURRENT (A) STEADY-STATE POWER DISSIPATION (W) 0 0.8 0.6 1a 1b 0.4 0.2 0 4.5"x5" FR-4 Board TA = 25 oC Still Air 0 0.1 0.2 0.3 2oz COPPER MOUNTING PAD AREA (in 2) 0.4 s 10m s 1 0.03 0 IT LIM 0.5 FS , TRANSCONDUCTANCE (SIEMENS) Typical Electrical Characteristics (continued) 50 1.2 1 1b 1a 4.5"x5" FR-4 Board TA = 25 oC Still Air VGS = -2.7V 0.8 0.6 0 0.1 0.2 0.3 2 2oz COPPER MOUNTING PAD AREA (in ) 0.4 Figure 16. Maximum Steady-State Drain Current versus Copper Mounting Pad Area. Figue 15. SuperSOTTM _ 3 Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 0.5 0.2 D = 0.5 R θJA (t) = r(t) * R θJA R θJA = See Note 1b 0.2 0.1 0.1 0.05 0.05 0.02 0.01 0.005 P(pk) 0.02 t1 0.01 t2 TJ - TA = P * R θJA (t) Single Pulse Duty Cycle, D = t1 /t2 0.002 0.001 0.0001 0.001 0.01 0.1 t 1 , TIME (sec) 1 10 100 300 Figure 17. Transient Thermal Response Curve. Note : Characterization performed using the conditions described in note 1b. Transient thermal response will change depending on the circuit board design. NDS332PRev. E TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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