OKDx-T/50-W12-C
www.murata-ps.com
50A Digital PoL DC-DC Converter Series
Typical units
FEATURES
Small package: SMD/TH: 30.85 x 20.0 x 8.2 mm
(1.215 x 0.787 x 0.323 in); SIP: 33.0 x 7.6 x 18.1 mm
(1.30 x 0.30 x 0.713 in)
PRODUCT OVERVIEW
Synchonization & phase spreading
The OKDx-T/50-W12 series are high efficiency, digital point-of-Load (PoL) DC-DC
power converters capable of delivering
50A/165W. Available in three different package formats, through-hole, single-in-line,
and surface mount, these converters have a
typical efficiency of 97.2%. PMBus™ compatibility allows monitoring and configuration of
critical system-level performance require-
ments. Apart from standard PoL performance
and safety features like OVP, OCP, OTP, and
UVLO, these digital converters have advanced
features: digital current sharing (full power,
no derating), non-linear transient response,
optimized dead time control, synchronization,
and phase spreading. These converters are
ideal for use in telecommunications, networking, and distributed power applications.
Current sharing, voltage tracking & voltage
margining
Power Management via PMBus™
Applications
Voltage setting via pin-strap or PMBus™
Configurable soft-start/stop
Distributed power architectures
MTBF 14.2 Mh
Configurable output voltage (Vout) and voltage
margins (Margin low and Margin high)
Intermediate bus voltage applications
Configurable protection limits for OVP, input over
voltage, input under voltage, over current, on/off,
and temperature
Network equipment
0.6 V - 3.3 V output voltage range
High efficiency, typ. 97.2% at 5Vin, 3.3Vout half
load
Configuration and monitoring via PMBus™
Adaptive compensation of PWM control loop &
fast loop transient response
Non-Linear Response for reduction of decoupling capacitor
Remote control & power good
Output short-circuit, output over voltage, & over
temperature protection
Certified to UL/IEC 60950-1
Servers and storage applications
Status monitor Vout, Iout, Vin, Temp, Power
good, and On/Off
PART NUMBER STRUCTURE
OKD x - T / 50 - W12 E - xxx - C
Digital Non-isolated PoL
Y = Surface Mount
H = Horizontal Mount Through-Hole
X = SIP
Trimmable Output
Voltage Range
0.6 - 3.3Vdc
RoHS Hazardous
Substance Compliance
C = RoHS-6 (does not claim EU RoHS exemption
7b – lead in solder)
Software Configuration Digits
(001 is positive turn-on logic)
(002 is negative turn-on logic)*
E = Long pin length (5.5mm)
Blank = Standard length (4.0mm)
Maximum Rated Output
Current in Amps
Input Voltage Range
4.5-14Vdc
*Special quantity order is required;
contact Murata Power Solutions for
MOQ and lead times.
PM
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MDC_OKDx-T/50-W12-C.A06 Page 1 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
ORDERING GUIDE
Model Number
OKDY-T/50-W12-001-C
OKDH-T/50-W12-001-C
OKDX-T/50-W12-001-C
OKDX-T/50-W12E-001-C
OKDH-T/50-W12-002-C
OKDX-T/50-W12-002-C
Output
0.6-3.3 V, 50 A/ 165 W
Absolute Maximum Ratings
Characteristics
TP2
Operating temperature (see Thermal Consideration section)
TS
Storage temperature
VI
Input voltage (See Operating Information Section for input and output voltage relations)
Logic I/O voltage
CTRL, SA0, SA1, SALERT, SCL, SDA, VSET, SYNC, GCB, PG
Ground voltage differential -S, PREF, GND
Analog pin voltage
VO, +S, VTRK
General and Safety
Safety
Calculated MTBF
Min
-40
-40
-0.3
-0.3
-0.3
-0.3
Conditions
Designed for UL/IEC/EN 60950 1
Telcordia SR-332, Issue 2 Method 1
Min
Typ
Typ
14.2
Max
125
125
16
6.5
0.3
6.5
Max
Unit
°C
°C
V
V
V
V
Unit
Mhrs
Stress in excess of Absolute Maximum Ratings may cause permanent
damage. Absolute Maximum Ratings, sometimes referred to as no
destruction limits, are normally tested with one parameter at a time
exceeding the limits in the Electrical Specification. If exposed to stress
above these limits, function and performance may degrade in an
unspecified manner.
default configuration file, unless otherwise specified. The default
configuration file is designed to fit most application needs with focus
on high efficiency. If different characteristics are required it is possible to change the configuration file to optimize certain performance
characteristics. Note that current sharing operation requires changed
configuration file.
Configuration File
This product is designed with a digital control circuit. The control
circuit uses a configuration file which determines the functionality
and performance of the product. The Electrical Specification table
shows parameter values of functionality and performance with the
In this Technical specification examples are included to show the
possibilities with digital control. See Operating Information section for
information about trade offs when optimizing certain key performance
characteristics.
C i=140 μF, C o =400 μF
VIN
VOUT
VIN
VOUT
Ci
Co
GND
GND
+Sense
-Sense
PGOOD
(SA1)
SALERT
CTRL
VSET
Controller and digital interface
SYNC
SCL
SDA
SA0
GCB
VTRK
PREF
Fundamental Circuit Diagram
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MDC_OKDx-T/50-W12-C.A06 Page 2 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Electrical Specifications, OKDY-T/50-W12-C and OKDH-T/50-W12-C
TP1 = -30 to +95°C, VIN = 4.5 to 14 V, VIN > VOUT + 1.0 V
Typical values given at: TP1 = +25 °C, VIN = 12.0 V, max IOUT, unless otherwise specified under Conditions.
Default configuration file, 190 10-CDA 102 0206/001.
External CIN = 470 μF/10 mΩ, COUT = 470 μF/10 mΩ. See Operating Information section for selection of capacitor types.
Sense pins are connected to the output pins.
Characteristics
Input voltage rise time
VI
Conditions
monotonic
Output voltage without pin strap
Output voltage adjustment range
Output voltage adjustment including margining
Output voltage set-point resolution
VO
Load regulation; IO = 0 - 100%
VOac
Output ripple & noise
CO = 470 μF (minimum external capacitance). See Note 11
IO
Output current
IS
Static input current at max IO
Ilim
Current limit threshold
Isc
Short circuit current
50% of max IO
See Note 17
V
V
V
% FS
-1
1
%
-2
2
%
±0.025
47
2
2
2
3
2
2
2
2
20
25
30
35
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 3.3 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 3.3 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 3.3 V
See Note 18
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 3.3 V
Efficiency
max IO
Pd
Power dissipation at max IO
Pli
Input idling power
(no load)
Default configuration: Continues
Conduction Mode, CCM
Unit
V/ms
3.3
3.63
0.60
0.54
0.001
Ω
mV
mV
mVp-p
50
3.10
4.80
8.19
14.53
52
RMS, hiccup mode, See Note 3
Max
2.4
Internal resistance +S/-S to VOUT/GND
Line regulation
Typ
1.2
Including line, load, temp.
See Note 14
Current sharing operation
See Note 15
Output voltage accuracy
Min
A
65
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 3.3 V
11
9
7
6
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 3.3 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 3.3 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 3.3 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 3.3 V
85.6
90.4
93.7
95.7
80.5
86.9
91.6
94.6
7.25
7.54
8.28
9.36
0.90
0.90
1.10
1.67
A
A
A
%
%
W
W
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MDC_OKDx-T/50-W12-C.A06 Page 3 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Characteristics
Turned off with
CTRL-pin
PCTRL
Input standby power
Ci
Co
Internal input capacitance
Internal output capacitance
Total external output capacitance
ESR range of capacitors
(per single capacitor)
COUT
Vtr1
ttr1
fs
Load transient peak
voltage deviation
(L to H/H to L)
Load step 25-75-25%
of max IO
Load transient recovery
time, Note 5
(L to H/H to L)
Load step 25-75-25%
of max IO
Default configuration
di/dt = 2 A/μs
CO = 470 μF (minimum external
capacitance) see Note 12
Default configuration
di/dt = 2 A/μs
CO = 470 μF (minimum external
capacitance) see Note 12
Switching frequency
Switching frequency range
Switching frequency set-point accuracy
Control Circuit PWM Duty Cycle
Minimum Sync Pulse Width
Input Clock Frequency Drift Tolerance
Input Under Voltage Lockout,
UVLO
Input Over Voltage Protection,
IOVP
Power Good, PG,
See Note 2
Output voltage
Over/Under Voltage Protection,
OVP/UVP
Over Current Protection,
OCP
UVLO threshold
UVLO threshold range
Set point accuracy
UVLO hysteresis
UVLO hysteresis range
Delay
Fault response
IOVP threshold
IOVP threshold range
Set point accuracy
IOVP hysteresis
IOVP hysteresis range
Delay
Fault response
PG threshold
PG hysteresis
PG delay
PG delay range
UVP threshold
UVP threshold range
UVP hysteresis
OVP threshold
OVP threshold range
UVP/OVP response time
UVP/OVP
response time range
Fault response
OCP threshold
OCP threshold range
Protection delay,
Protection delay range
Fault response
Conditions
Default configuration:
Monitoring enabled,
Precise timing enabled
Min
Typ
Max
Unit
mW
170
140
400
See Note 9
470
30 000
μF
μF
μF
See Note 9
5
30
mΩ
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
79 / 256
127 / 298
144 / 324
VO = 3.3 V
210 / 327
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
60 / 100
100 / 100
100 / 100
VO = 3.3 V
100 / 100
PMBus configurable
320
200-640
External clock source
-5
5
150
-13
5
95
13
-150
150
0.35
0-10.15
2.5
Automatic restart, 70 ms
16
4.2-16
PMBus configurable
See Note 3
PMBus configurable
-150
See Note 3
See Note 19
PMBus configurable
PMBus configurable
PMBus configurable
PMBus configurable
See Note 3
PMBus configurable
See Note 4
PMBus configurable
See Note 3
μs
3.85
3.85-14
PMBus configurable
PMBus configurable
mV
150
1
0-11.8
2.5
Automatic restart, 70 ms
90
5
Direct after DLC
0-500
85
0-100
5
115
100-115
25
5-60
Automatic restart, 70 ms
62
0-62
32
1-32
Automatic restart, 70 ms
kHz
kHz
%
%
ns
%
V
V
mV
V
V
μs
V
V
mV
V
V
μs
% VO
% VO
s
% VO
% VO
% VO
% VO
% VO
μs
μs
A
A
Tsw
Tsw
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MDC_OKDx-T/50-W12-C.A06 Page 4 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Characteristics
Over Temperature Protection,
OTP at P2
See Note 8
VIL
VIH
IIL
VOL
VOH
IOL
IOH
tset
thold
tfree
Cp
Conditions
OTP threshold
OTP threshold range
OTP hysteresis
OTP hysteresis range
Fault response
Logic input low threshold
Logic input high threshold
Logic input low sink current
Logic output low signal level
Logic output high signal level
Logic output low sink current
Logic output high source current
Setup time, SMBus
Hold time, SMBus
Bus free time, SMBus
Internal capacitance on logic pins
Initialization time
Output Voltage
Delay Time
See Note 6
Output Voltage
Ramp Time
See Note 13
Delay duration
Delay duration range
Delay accuracy
turn-on
Delay accuracy
turn-off
Ramp duration
Ramp duration range
Ramp time accuracy
VTRK Input Bias Current
VTRK Tracking Ramp Accuracy (VO - VVTRK)
VTRK Regulation Accuracy (VO - VVTRK)
Current difference between products in a current sharing group
Min
PMBus configurable
PMBus configurable
See Note 3
SYNC, SA0, SA1, SCL, SDA, GCB, CTRL,
VSET
CTRL
SYNC, SCL, SDA, SALERT, GCB, PG
See Note 1
See Note 1
See Note 1
READ_IOUT vs IO
0.8
V
V
mA
V
V
mA
mA
ns
ns
ms
pF
2
0.6
0.4
2.25
4
2
10
See Note 10
See Note 16
PMBus configurable
Current sharing operation
VVTRK = 5.5 V
100% tracking, see Note 7
Current sharing operation
2 phases, 100% tracking
VO = 1.0 V, 10 ms ramp
100% Tracking
Current sharing operation
100% Tracking
Steady state operation
Ramp-up
IO = 0-50 A, TP1 = 0 to +95 °C
VI = 4.5-14 V, VO = 1.0 V
IO = 0-50 A, TP1 = 0 to +95 °C
VI = 4.5-14 V, VO = 0.6-3.3 V
Note 1: See section I2C/SMBus Setup and Hold Times – Definitions.
Note 2: Monitorable over PMBus Interface.
Note 3: Automatic restart ~70 or 240 ms after fault if the fault is no longer present. Continuous restart attempts if the
fault reappear after restart. See Operating Information for other fault response options.
Note 4: Tsw is the switching period.
Note 5: Within +/-3% of VO
Note 6: See section Soft-start Power Up.
Note 7: Tracking functionality is designed to follow a VTRK signal with slew rate < 2.4 V/ms. For faster VTRK signals
accuracy will depend on the regulator bandwidth.
Note 8: See section Over Temperature Protection (OTP).
Note 9: See section External Capacitors.
Note 10: See section Initialization Procedure.
40
10
5-500000
ms
-0.25/+4
ms
-0.25/+4
ms
ms
10
0-200
100
20
PMBus configurable
READ_VIN vs VI
READ_VOUT vs VO
READ_IOUT vs IO
Unit
°C
°C
°C
°C
300
250
2
Number of products in a current sharing group
Monitoring accuracy
Typ
Max
120
-40…+125
25
0-165
Automatic restart, 240 ms
110
-100
ms
μs
%
200
100
±100
μA
mV
mV
-1
1
%
-2
2
%
Max 2 x READ_IOUT monitoring accuracy
4
7
A
3
1
%
%
±3.0
A
±5.0
A
Note 11: See graph Output Ripple vs External Capacitance and Operating information section Output Ripple and Noise.
Note 12: See graph Load Transient vs. External Capacitance and Operating information section External Capacitors.
Note 13: Time for reaching 100% of nominal Vout.
Note 14: For Vout < 1.0 V accuracy is +/-10 mV. For further deviations see section Output Voltage Adjust using PMBus.
Note 15: Accuracy here means deviation from ideal output voltage level given by configured droop and actual load.
Includes line, load and temperature variations.
Note 16: For current sharing the Output Voltage Delay Time must be reconfigured to minimum 15 ms.
Note 17: For steady state operation above 1.05 x 3.3 V, please contact your local Murata sales representative.
Note 18: A minimum load current is not required if Low Power mode is used (monitoring disabled).
Note 19: See sections Dynamic Loop Compensation and Power Good.
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MDC_OKDx-T/50-W12-C.A06 Page 5 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Typical Characteristics
Efficiency and Power Dissipation
Efficiency vs. Output Current, VI = 5 V
Power Dissipation vs. Output Current, VI = 5 V
[%]
[W]
100
12
95
10
8
90
0.6 V
1.0 V
85
80
75
0
0
1
0
2
0
3
0
4
0.6 V
6
1.0 V
1.8 V
4
1.8 V
3.3 V
2
3.3 V
0
50 [A]
0
0
1
0
2
0
3
0
4
50 [A]
Efficiency vs. load current and output voltage:
TP1 = +25 °C, VI = 5 V, fsw = 320 kHz, CO = 470 μF/10 m.
Dissipated power vs. load current and output voltage:
TP1 = +25 °C, VI = 5 V, fsw = 320 kHz, CO = 470 μF/10 m.
Efficiency vs. Output Current, VI = 12 V
Power Dissipation vs. Output Current, VI = 12 V
[%]
[W]
100
12
10
95
8
90
0.6 V
1.0 V
85
80
0.6 V
6
1.0 V
1.8 V
4
1.8 V
3.3 V
2
3.3 V
75
0
0
0
1
0
2
0
3
0
4
50 [A]
0
0
1
0
2
0
3
0
4
50 [A]
Efficiency vs. load current and output voltage at
TP1 = +25 °C, VI = 12 V, fsw = 320 kHz, CO = 470 μF/10 m.
Dissipated power vs. load current and output voltage:
TP1 = +25 °C, VI = 12 V, fsw = 320 kHz, CO = 470 μF/10 m.
Efficiency vs. Output Current and
Switching Frequency
Power Dissipation vs. Output Current and
Switching frequency
[%]
[W]
95
12
10
90
200
kHz
85
200
kHz
8
320
kHz
6
320
kHz
80
480
kHz
4
480
kHz
75
640
kHz
2
640
kHz
70
0
0
10
0
2
0
3
0
4
Efficiency vs. load current and switch frequency at
TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 μF/10 m.
Default configuration except changed frequency
50 [A]
0
0
1
0
2
0
3
0
4
50 [A]
Dissipated power vs. load current and switch frequency at
TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 μF/10 m.
Default configuration except changed frequency
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MDC_OKDx-T/50-W12-C.A06 Page 6 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Typical Characteristics
Load Transient
Load Transient vs. External Capacitance, VO = 1.0 V
[mV]
500
Universal PID,
No NLR
Load Transient vs. External Capacitance, VO = 3.3 V
[mV]
500
Universal PID,
No NLR
400
DLC,
No NLR
400
300
Universal PID,
Default NLR
300
Universal PID,
Default NLR
200
DLC,
Default NLR
200
DLC,
Default NLR
100
Universal PID,
Opt. NLR
100
Universal PID,
Opt. NLR
DLC,
Opt. NLR
0
0
1
2
3
4
DLC,
Opt. NLR
0
0
5 [mF]
DLC,
No NLR
1
2
3
4
5 [mF]
Load transient peak voltage deviation vs. external capacitance.
Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 μF/10 m,
TP1 = +25 °C, VI = 12 V, VO = 1.0 V, fsw = 320 kHz, di/dt = 2 A/μs
Load transient peak voltage deviation vs. external capacitance.
Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 μF/10 m,
TP1 = +25 °C, VI = 12 V, VO = 3.3 V, fsw = 320 kHz, di/dt = 2 A/μs
Load transient vs. Switch Frequency
Output Load Transient Response, Default Configuration
[mV]
600
Universal PID,
No NLR
500
DLC,
No NLR
400
Universal PID,
Default NLR
300
DLC,
Default NLR
200
Universal PID,
Opt. NLR
100
DLC,
Opt. NLR
0
200
300
400
500
600 [kHz]
Load transient peak voltage deviation vs. frequency.
Step-change (12.5-37.5-12.5 A).
TP1 = +25 °C. VI = 12 V, VO = 1.0 V, CO = 470 μF/10 m
Output voltage response to load current
Step-change (12.5-37.5-12.5 A) at:
TP1 = +25 °C, VI = 12 V, VO = 1.0 V
di/dt = 2 A/μs, fsw = 320 kHz
CO = 470 μF/10 m
Top trace: output voltage (200
mV/div.).
Bottom trace: load current (10
A/div.).
Time scale: (0.1 ms/div.).
Note 1: For Universal PID, see section Dynamic Loop Compensation (DLC).
Note 2: In the load transient graphs, the worst-case scenario (load step 37.5-12.5 A) has been
considered.
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MDC_OKDx-T/50-W12-C.A06 Page 7 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Typical Characteristics
Output Current Characteristic
Output Current Derating, VO = 0.6 V
Output Current Derating, VO = 1.0 V
[A]
[A]
50
50
3.0 m/s
40
2.0 m/s
3.0 m/s
40
2.0 m/s
30
1.0 m/s
30
1.0 m/s
20
0.5 m/s
20
0.5 m/s
Nat. Conv.
10
0
Nat. Conv.
10
0
20
40
60
80
100
120 [°C]
20
40
60
80
100
120 [°C]
Available load current vs. ambient air temperature and airflow at
VO = 0.6 V, VI = 12 V. See Thermal Consideration section.
Available load current vs. ambient air temperature and airflow at
VO = 1.0 V, VI = 12 V. See Thermal Consideration section.
Output Current Derating, VO = 1.8 V
Output Current Derating, VO = 3.3 V
[A]
[A]
50
50
3.0 m/s
3.0 m/s
40
40
2.0 m/s
2.0 m/s
30
1.0 m/s
30
1.0 m/s
20
0.5 m/s
20
0.5 m/s
Nat. Conv.
10
10
Nat. Conv.
0
0
20
40
60
80
100
20
120 [°C]
40
60
80
100
120 [°C]
Available load current vs. ambient air temperature and airflow at
VO = 3.3 V, VI = 12 V. See Thermal Consideration section.
Available load current vs. ambient air temperature and airflow at
VO = 1.8 V, VI = 12 V. See Thermal Consideration section.
Current Limit Characteristics, VO = 1.0 V
Current Limit Characteristics, VO = 3.3 V
[V]
[V]
1.2
4.0
VI = 4.5, 5 .0V
VI = 5.0, 12 V
0.9
3.0
4.5 V
4.5 V
5.0 V
0.6
5.0 V
2.0
12 V
12 V
VI = 4.5,14 V
14 V
0.3
0.0
VI = 12, 14 V
14 V
1.0
0.0
50
55
60
65 [A]
50
55
60
65 [A]
Output voltage vs. load current at TP1 = +25 °C, VO = 1.0 V.
Output voltage vs. load current at TP1 = +25 °C, VO = 3.3 V.
Note: Output enters hiccup mode at current limit.
Note: Output enters hiccup mode at current limit.
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MDC_OKDx-T/50-W12-C.A06 Page 8 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Typical Characteristics
Output Voltage
Output Ripple & Noise, VO = 1.0 V
Output Ripple & Noise, VO = 3.3 V
Output voltage ripple at: TP1 = +25 °C, Trace: output voltage (10 mV/div.).
Time scale: (2 μs/div.).
VI = 12 V, CO = 470 μF/10 m
IO = 50 A
Output voltage ripple at: TP1 = +25 °C, Trace: output voltage (10 mV/div.).
VI = 12 V, CO = 470 μF/10 m
Time scale: (2 μs/div.).
IO = 50 A
Output Ripple vs. Input Voltage
Output Ripple vs. Frequency
[mVpk-pk]
[mVpk-pk]
40
70
60
30
50
0.6 V
1.0 V
40
1.0 V
1.8 V
30
3.3 V
20
0.6 V
20
10
1.8 V
3.3 V
10
0
5
7
9
11
0
[V]
13
200
300
400
500
600
[kHz]
Output voltage ripple Vpk-pk at: TP1 = +25 °C, CO = 470 μF/10 m, IO = 50 A
Output voltage ripple Vpk-pk at: TP1 = +25 °C, VI = 12 V, CO = 470 μF/10 m,
IO = 50 A. Default configuration except changed frequency.
Output Ripple vs. External Capacitance
Load regulation, VO = 1.0 V
[mV]
[V]
40
1.010
30
0.6 V
1.005
4.5 V
1.0 V
20
1.8 V
3.3 V
10
0
0
1
2
3
4
5 [mF]
Output voltage ripple Vpk-pk at: TP1 = +25 °C, VI = 12 V. IO = 50 A.
Parallel coupling of capacitors with 470 μF/10 m
5.0 V
1.000
12 V
14 V
0.995
0.990
0
5
10
15
20
25 [A]
Load regulation at VO = 1.0 V, TP1 = +25 °C, CO = 470 μF/10 m
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MDC_OKDx-T/50-W12-C.A06 Page 9 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Typical Characteristics
Start-up and shut-down
Start-up by input source
Start-up enabled by connecting VI at:
TP1 = +25 °C, VI = 12 V, VO = 1.0 V
CO = 470 μF/10 m, IO = 50 A
Shut-down by input source
Top trace: output voltage (0.5 V/div.).
Bottom trace: input voltage (5 V/div.).
Time scale: (20 ms/div.).
Start-up by CTRL signal
Start-up by enabling CTRL signal at:
TP1 = +25 °C, VI = 12 V, VO = 1.0 V
CO = 470 μF/10 m, IO = 50 A
Shut-down enabled by disconnecting
VI at:
TP1 = +25 °C, VI = 12 V, VO = 1.0 V
CO = 470 μF/10 m, IO = 50 A
Top trace: output voltage (0.5 V/div.).
Bottom trace: input voltage (5 V/div.).
Time scale: (2 ms/div.).
Shut-down by CTRL signal
Top trace: output voltage (0.5 V/div.).
Bottom trace: CTRL signal (2 V/div.).
Time scale: (20 ms/div.).
Shut-down enabled by disconnecting
VI at:
TP1 = +25 °C, VI = 12 V, VO = 1.0 V
CO = 470 μF/10 m, IO = 50 A
Top trace: output voltage (0.5 V/div).
Bottom trace: CTRL signal (2 V/div.).
Time scale: (2 ms/div.).
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MDC_OKDx-T/50-W12-C.A06 Page 10 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Electrical Specifications, OKDX-T/50-W12-C
TP1 = -30 to +95 °C, VI = 4.5 to 14 V, VI > VO + 1.0 V
Typical values given at: TP1 = +25 °C, VI = 12.0 V, max IO, unless otherwise specified under Conditions.
Default configuration file, 190 10-CDA 102 0259/001.
External CIN = 470 μF/10 mΩ, COUT = 470 μF/10 mΩ. See Operating Information section for selection of capacitor types.
Sense pins are connected to the output pins.
Characteristics
VI
Input voltage rise time
Conditions
monotonic
Output voltage without pin strap
Output voltage adjustment range
Output voltage adjustment including margining
Output voltage set-point resolution
VO
Load regulation; IO = 0 - 100%
VOac
Output ripple & noise
CO = 470 μF (minimum external capacitance). See Note 11
IO
Output current
IS
Static input current at max IO
Ilim
Current limit threshold
Isc
Short circuit current
RMS, hiccup mode, See Note 3
Efficiency
max IO
Pd
Power dissipation at max IO
Pli
Input idling power
(no load)
Default configuration: Continues
Conduction Mode, CCM
PCTRL
Input standby power
Turned off with
CTRL-pin
Ci
Internal input capacitance
Max
2.4
Unit
V/ms
3.3
3.63
V
V
V
% FS
1
%
2
%
±0.025
-1
-2
47
2
2
2
3
2
2
2
2
20
25
30
40
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 3.3 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 3.3 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 3.3 V
See Note 18
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 3.3 V
0.001
mV
mV
mVp-p
50
10
8
6
5
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 3.3 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 3.3 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 3.3 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 3.3 V
85.2
90.2
93.3
95.3
80.2
86.6
91.2
94.2
7.40
7.73
8.68
10.15
0.95
0.95
1.22
1.88
170
140
A
A
65
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 3.3 V
Default configuration:
Monitoring enabled,
Precise timing enabled
Ω
3.12
4.81
8.22
14.59
52
50% of max IO
See Note 17
0.60
0.54
Internal resistance +S/-S to VOUT/GND
Line regulation
Typ
1.2
Including line, load, temp.
See Note 14
Current sharing operation
See Note 15
Output voltage accuracy
Min
A
A
%
%
W
W
mW
μF
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MDC_OKDx-T/50-W12-C.A06 Page 11 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Characteristics
Co
Internal output capacitance
Total external output capacitance
COUT
ESR range of capacitors
(per single capacitor)
Vtr1
ttr1
fs
Load transient peak
voltage deviation
(L to H/H to L)
Load step 25-75-25%
of max IO
Default configuration
di/dt = 2 A/μs
CO = 470 μF (minimum external
capacitance) see Note 12
Load transient recovery
time, Note 5
(L to H/H to L)
Load step 25-75-25%
of max IO
Default configuration
di/dt = 2 A/μs
CO = 470 μF (minimum external
capacitance) see Note 12
Switching frequency
Switching frequency range
Switching frequency set-point accuracy
Control Circuit PWM Duty Cycle
Minimum Sync Pulse Width
Input Clock Frequency Drift Tolerance
Input Under Voltage Lockout,
UVLO
Input Over Voltage Protection,
IOVP
Power Good, PG,
See Note 2
Output voltage
Over/Under Voltage Protection,
OVP/UVP
Over Current Protection,
OCP
UVLO threshold
UVLO threshold range
Set point accuracy
UVLO hysteresis
UVLO hysteresis range
Delay
Fault response
IOVP threshold
IOVP threshold range
Set point accuracy
IOVP hysteresis
IOVP hysteresis range
Delay
Fault response
PG threshold
PG hysteresis
PG delay
PG delay range
UVP threshold
UVP threshold range
UVP hysteresis
OVP threshold
OVP threshold range
UVP/OVP response time
UVP/OVP
response time range
Fault response
OCP threshold
OCP threshold range
Protection delay,
Protection delay range
Fault response
Conditions
Min
Typ
400
See Note 9
470
30 000
Unit
μF
μF
See Note 9
5
30
mΩ
VO = 0.6 V
90 / 300
VO = 1.0 V
120 / 300
VO = 1.8 V
160 / 305
VO = 3.3 V
230 / 315
VO = 0.6 V
70 / 100
VO = 1.0 V
100 / 100
VO = 1.8 V
100 / 100
VO = 3.3 V
100 / 100
PMBus configurable
320
200-640
External clock source
mV
μs
-5
5
150
-13
5
95
13
3.85
3.85-14
PMBus configurable
-150
150
0.35
0-10.15
2.5
Automatic restart, 70 ms
16
4.2-16
PMBus configurable
See Note 3
PMBus configurable
-150
PMBus configurable
See Note 3
See Note 19
PMBus configurable
PMBus configurable
PMBus configurable
PMBus configurable
See Note 3
PMBus configurable
See Note 4
PMBus configurable
See Note 3
Max
150
kHz
kHz
%
%
ns
%
V
V
mV
V
V
μs
V
V
mV
V
V
μs
1
0-11.8
2.5
Automatic restart, 70 ms
90
5
Direct after DLC
0-500
85
0-100
5
115
100-115
25
% VO
% VO
ms
s
% VO
% VO
% VO
% VO
% VO
μs
5-60
μs
Automatic restart, 70 ms
60
0-60
32
1-32
Automatic restart, 70 ms
A
A
Tsw
Tsw
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MDC_OKDx-T/50-W12-C.A06 Page 12 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Characteristics
Over Temperature Protection,
OTP at P2
See Note 8
VIL
VIH
IIL
VOL
VOH
IOL
IOH
tset
thold
tfree
Cp
Conditions
OTP threshold
OTP threshold range
OTP hysteresis
OTP hysteresis range
Fault response
Logic input low threshold
Logic input high threshold
Logic input low sink current
Logic output low signal level
Logic output high signal level
Logic output low sink current
Logic output high source current
Setup time, SMBus
Hold time, SMBus
Bus free time, SMBus
Internal capacitance on logic pins
Initialization time
Output Voltage
Delay Time
See Note 6
Output Voltage
Ramp Time
See Note 13
Delay duration
Delay duration range
Delay accuracy
turn-on
Delay accuracy
turn-off
Ramp duration
Ramp duration range
Ramp time accuracy
VTRK Input Bias Current
VTRK Tracking Ramp Accuracy (VO - VVTRK)
VTRK Regulation Accuracy (VO - VVTRK)
Current difference between products in a current sharing group
Min
PMBus configurable
PMBus configurable
See Note 3
SYNC, SA0, SA1, SCL, SDA, GCB, CTRL,
VSET
CTRL
SYNC, SCL, SDA, SALERT, GCB, PG
See Note 1
See Note 1
See Note 1
READ_IOUT vs IO
0.8
V
V
mA
V
V
mA
mA
ns
ns
ms
pF
2
0.6
0.4
2.25
4
2
10
See Note 10
See Note 16
PMBus configurable
Current sharing operation
VVTRK = 5.5 V
100% tracking, see Note 7
Current sharing operation
2 phases, 100% tracking
VO = 1.0 V, 10 ms ramp
100% Tracking
Current sharing operation
100% Tracking
Steady state operation
Ramp-up
IO = 0-50 A, TP1 = 0 to +95 °C
VI = 4.5-14 V, VO = 1.0 V
IO = 0-50 A, TP1 = 0 to +95 °C
VI = 4.5-14 V, VO = 0.6-3.3 V
Note 1: See section I2C/SMBus Setup and Hold Times – Definitions.
Note 2: Monitorable over PMBus Interface.
Note 3: Automatic restart ~70 or 240 ms after fault if the fault is no longer present. Continuous restart attempts if the
fault reappear after restart. See Operating Information for other fault response options.
Note 4: Tsw is the switching period.
Note 5: Within +/-3% of VO
Note 6: See section Soft-start Power Up.
Note 7: Tracking functionality is designed to follow a VTRK signal with slew rate < 2.4 V/ms. For faster VTRK signals
accuracy will depend on the regulator bandwidth.
Note 8: See section Over Temperature Protection (OTP).
Note 9: See section External Capacitors.
Note 10: See section Initialization Procedure.
40
10
5-500000
ms
-0.25/+4
ms
-0.25/+4
ms
ms
10
0-200
100
20
PMBus configurable
READ_VIN vs VI
READ_VOUT vs VO
READ_IOUT vs IO
Unit
°C
°C
°C
°C
300
250
2
Number of products in a current sharing group
Monitoring accuracy
Typ
Max
120
-40…+125
25
0-165
Automatic restart, 240 ms
110
-100
ms
μs
%
200
100
±100
μA
mV
mV
-1
1
%
-2
2
%
Max 2 x READ_IOUT monitoring accuracy
4
7
A
3
1
%
%
±3.0
A
±5.0
A
Note 11: See graph Output Ripple vs External Capacitance and Operating information section Output Ripple and Noise.
Note 12: See graph Load Transient vs. External Capacitance and Operating information section External Capacitors.
Note 13: Time for reaching 100% of nominal Vout.
Note 14: For Vout < 1.0 V accuracy is +/-10 mV. For further deviations see section Output Voltage Adjust using PMBus.
Note 15: Accuracy here means deviation from ideal output voltage level given by configured droop and actual load.
Includes line, load and temperature variations.
Note 16: For current sharing the Output Voltage Delay Time must be reconfigured to minimum 15 ms.
Note 17: For steady state operation above 1.05 x 3.3 V, please contact your local Murata sales representative.
Note 18: A minimum load current is not required if Low Power mode is used (monitoring disabled).
Note 19: See sections Dynamic Loop Compensation and Power Good.
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MDC_OKDx-T/50-W12-C.A06 Page 13 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Typical Characteristics
Efficiency and Power Dissipation
Efficiency vs. Output Current, VI = 5 V
Power Dissipation vs. Output Current, VI = 5 V
[%]
[W]
100
12
10
95
8
90
0.6 V
1.0 V
85
80
75
0
10
20
30
40
0.6 V
6
1.0 V
1.8 V
4
1.8 V
3.3 V
2
3.3 V
0
50 [A]
0
10
20
30
40
50 [A]
Efficiency vs. load current and output voltage:
TP1 = +25 °C, VI = 5 V, fsw = 320 kHz, CO = 470 μF/10 m.
Dissipated power vs. load current and output voltage:
TP1 = +25 °C, VI = 5 V, fsw = 320 kHz, CO = 470 μF/10 m.
Efficiency vs. Output Current, VI = 12 V
Power Dissipation vs. Output Current, VI = 12 V
[%]
[W]
100
12
10
95
8
90
0.6 V
1.0 V
85
80
0.6 V
6
1.0 V
1.8 V
4
1.8 V
3.3 V
2
3.3 V
75
0
0
10
20
30
40
50 [A]
0
10
20
30
40
50 [A]
Efficiency vs. load current and output voltage at
TP1 = +25 °C, VI=12 V, fsw = 320 kHz, CO = 470 μF/10 m.
Dissipated power vs. load current and output voltage:
TP1 = +25 °C, VI=12 V, fsw = 320 kHz, CO = 470 μF/10 m.
Efficiency vs. Output Current and
Switching Frequency
Power Dissipation vs. Output Current and
Switching frequency
[%]
[W]
95
12
10
90
200
kHz
85
200
kHz
8
320
kHz
6
320
kHz
80
480
kHz
4
480
kHz
75
640
kHz
2
640
kHz
70
0
0
10
20
30
40
Efficiency vs. load current and switch frequency at
TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 μF/10 m.
Default configuration except changed frequency
50 [A]
0
10
20
30
40
50 [A]
Dissipated power vs. load current and switch frequency at
TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 μF/10 m.
Default configuration except changed frequency
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MDC_OKDx-T/50-W12-C.A06 Page 14 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Typical Characteristics
Load Transient
Load Transient vs. External Capacitance, VO = 1.0 V
[mV]
500
400
Universal PID,
No NLR
Load Transient vs. External Capacitance, VO = 3.3 V
[mV]
500
Universal PID,
No NLR
DLC,
No NLR
400
DLC,
No NLR
300
Universal PID,
Default NLR
300
Universal PID,
Default NLR
200
DLC,
Default NLR
200
DLC,
Default NLR
100
Universal PID,
Opt. NLR
100
Universal PID,
Opt. NLR
DLC,
Opt. NLR
0
0
1
2
3
4
5 [mF]
DLC,
Opt. NLR
0
0
1
2
3
4
5 [mF]
Load transient peak voltage deviation vs. external capacitance.
Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 μF/10 m,
TP1 = +25 °C. VI = 12 V, VO = 1.0 V, fsw = 320 kHz, di/dt = 2 A/μs
Load transient peak voltage deviation vs. external capacitance.
Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 μF/10 m,
TP1 = +25 °C. VI = 12 V, VO = 3.3 V, fsw = 320 kHz, di/dt = 2 A/μs
Load transient vs. Switch Frequency
Output Load Transient Response, Default Configuration
[mV]
600
Universal PID,
No NLR
500
DLC,
No NLR
400
Universal PID,
Default NLR
300
DLC,
Default NLR
200
Universal PID,
Opt. NLR
100
DLC,
Opt. NLR
0
200
300
400
500
600 [kHz]
Load transient peak voltage deviation vs. frequency.
Step-change (12.5-37.5-12.5 A).
TP1 = +25 °C. VI = 12 V, VO = 1.0 V, CO = 470 μF/10 m
Output voltage response to load
Step-change (12.5-37.5-12.5 A) at:
TP1 = +25 °C, VI = 12 V, VO = 1.0 V
di/dt = 2 A/μs, fsw = 320 kHz
CO = 470 μF/10 m
Top trace: output voltage (200 mV/div.).
Bottom trace: load current (10 A/div.).
Time scale: (0.1 ms/div.).
Note 1: For Universal PID, see section Dynamic Loop Compensation (DLC).
Note 2: In these graphs, the worst-case scenario (load step 37.5-12.5 A) has been considered.
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MDC_OKDx-T/50-W12-C.A06 Page 15 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Typical Characteristics
Output Current Characteristic
Output Current Derating, VO = 0.6 V
Output Current Derating, VO = 1.0 V
[A]
[A]
50
50
3.0 m/s
3.0 m/s
40
2.0 m/s
40
2.0 m/s
30
1.0 m/s
30
1.0 m/s
20
0.5 m/s
20
0.5 m/s
Nat. Conv.
10
0
Nat. Conv.
10
0
20
40
60
80
100
120 [°C]
20
40
60
80
100
120 [°C]
Available load current vs. ambient air temperature and airflow at
VO = 0.6 V, VI = 12 V. See Thermal Consideration section.
Available load current vs. ambient air temperature and airflow at
VO = 1.0 V, VI = 12 V. See Thermal Consideration section.
Output Current Derating, VO = 1.8 V
Output Current Derating, VO = 3.3 V
[A]
[A]
50
50
3.0 m/s
3.0 m/s
40
2.0 m/s
40
2.0 m/s
30
1.0 m/s
30
1.0 m/s
20
0.5 m/s
20
0.5 m/s
Nat. Conv.
10
0
Nat. Conv.
10
0
20
40
60
80
100
120 [°C]
20
Available load current vs. ambient air temperature and airflow at
VO = 1.8 V, VI = 12 V. See Thermal Consideration section.
40
60
80
100
120 [°C]
Available load current vs. ambient air temperature and airflow at
VO = 3.3 V, VI = 12 V. See Thermal Consideration section.
Current Limit Characteristics, VO = 1.0 V
Current Limit Characteristics, VO = 3.3 V
[V]
[V]
1,2
4,0
0,9
3,0
4.5 V
4.5 V
5.0 V
0,6
VI = 4.5, 5.0 V
VI = 12, 14 V
5.0 V
2,0
12 V
12 V
14 V
0,3
0,0
VI = 4.5, 14 V
VI = 5.0, 12 V
14 V
1,0
0,0
50
55
60
65 [A]
Output voltage vs. load current at TP1 = +25 °C, VO = 1.0 V.
Note: Output enters hiccup mode at current limit.
50
55
60
65 [A]
Output voltage vs. load current at TP1 = +25 °C, VO = 3.3 V.
Note: Output enters hiccup mode at current limit.
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MDC_OKDx-T/50-W12-C.A06 Page 16 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Typical Characteristics
Output Voltage
Output Ripple & Noise, VO = 1.0 V
Output Ripple & Noise, VO = 3.3 V
Output voltage ripple at: TP1 = +25 °C, Trace: output voltage (10 mV/div.).
Time scale: (2 μs/div.).
VI = 12 V, CO = 470 μF/10 m
IO = 50 A
Output voltage ripple at: TP1 = +25 °C, Trace: output voltage (10 mV/div.).
Time scale: (2 μs/div.).
VI = 12 V, CO = 470 μF/10 m
IO = 50 A
Output Ripple vs. Input Voltage
Output Ripple vs. Frequency
[mVpk-pk]
[mVpk-pk]
50
60
50
40
0.6 V
30
1.0 V
0.6 V
40
1.0 V
30
1.8 V
1.8 V
20
3.3 V
10
3.3 V
20
10
0
5
7
9
11
0
[V]
13
200
300
400
500
600
[kHz]
Output voltage ripple Vpk-pk at: TP1 = +25 °C, CO = 470 μF/10 m, IO = 50 A.
Output voltage ripple Vpk-pk at: TP1 = +25 °C, VI = 12 V, CO = 470 μF/10 m,
IO = 50 A. Default configuration except changed frequency.
Output Ripple vs. External Capacitance
Load regulation, VO = 1.0 V
[mV]
[V]
50
1,010
40
0.6 V
30
1,005
4.5 V
1.0 V
1.8 V
20
3.3 V
10
0
0
1
2
3
4
5 [mF]
Output voltage ripple Vpk-pk at: TP1 = +25 °C, VI = 12 V, IO = 50 A.
Parallel coupling of capacitors with 470 μF/10 m
5.0 V
1,000
12 V
14 V
0,995
0,990
0
5
10
15
20
25 [A]
Load regulation at VO = 1.0 V, TP1 = +25 °C, CO = 470 μF/10 m
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MDC_OKDx-T/50-W12-C.A06 Page 17 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Typical Characteristics
Start-up and shut-down
Start-up by input source
Start-up enabled by connecting VI at:
TP1 = +25 °C, VI = 12 V, VO = 1.0 V
CO = 470 μF/10 m, IO = 50 A
Shut-down by input source
Top trace: output voltage (0.5 V/div.).
Bottom trace: input voltage (5 V/div.).
Time scale: (20 ms/div.).
Start-up by CTRL signal
Start-up by enabling CTRL signal at:
TP1 = +25 °C, VI = 12 V, VO = 1.0 V
CO = 470 μF/10 m, IO = 50 A
Shut-down enabled by disconnecting
VI at:
TP1 = +25 °C, VI = 12 V, VO = 1.0 V
CO = 470 μF/10 m, IO = 50 A
Top trace: output voltage (0.5 V/div).
Bottom trace: input voltage (5 V/div.).
Time scale: (2 ms/div.).
Shut-down by CTRL signal
Top trace: output voltage (0.5 V/div.).
Bottom trace: CTRL signal (2 V/div.).
Time scale: (20 ms/div.).
Shut-down enabled by disconnecting
VI at:
TP1 = +25 °C, VI = 12 V, VO = 1.0 V
CO = 470 μF/10 m, IO = 50 A
Top trace: output voltage (0.5 V/div).
Bottom trace: CTRL signal (2 V/div.).
Time scale: (2 ms/div.).
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MDC_OKDx-T/50-W12-C.A06 Page 18 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Conducted EMI Input terminal value (typical for default configuration)
Output Ripple and Noise
Output ripple and noise is measured according to figure below.
A 50 mm conductor works as a small inductor forming together with the
two capacitors as a damped filter.
50 mm conductor
Vout
Tantalum
Capacitor
Output
10 μ F
Capacitor
470 μ F/10 m Ω
+S
–S
GND
Ceramic
Capacitor
0.1 μ F
Load
EMC Specification
Conducted EMI measured according to test set-up below. The fundamental switching frequency is 320 kHz at VI = 12 V, max IO.
50 mm conductor
BNC-contact to
oscilloscope
Output ripple and noise test set-up.
Operating information
EMI without filter
To spectrum
analyzer
RF Current probe
1kHz – 50MHz
Battery
supply
Resistive
load
C1
POL
50mm
C1 = 10uF / 600VDC
Feed- Thru RF capacitor
800mm
200mm
Conducted EMI test set-up
Layout Recommendations
The radiated EMI performance of the product will depend on the PWB
layout and ground layer design. It is also important to consider the standoff of the product. If a ground layer is used, it should be connected to the
output of the product and the equipment ground or chassis.
Power Management Overview
This product is equipped with a PMBus interface. The product incorporates a wide range of readable and configurable power management
features that are simple to implement with a minimum of external
components. Additionally, the product includes protection features
that continuously safeguard the load from damage due to unexpected
system faults. A fault is also shown as an alert on the SALERT pin.
The following product parameters can continuously be monitored by a
host: Input voltage, output voltage/current, and internal temperature. If
the monitoring is not needed it can be disabled and the product enters
a low power mode reducing the power consumption. The protection
features are not affected.
The product is delivered with a default configuration suitable
for a wide range operation in terms of input voltage, output voltage, and load. The configuration is stored in an internal Non-Volatile
Memory (NVM). All power management functions can be reconfigured
using the PMBus interface. Please contact your local Murata Power
Solutions representative for design support of custom configurations or appropriate SW tools for design and download of your own
configurations.
Input Voltage
The input voltage range, 4.5 - 14 V, makes the product easy to use in
intermediate bus applications when powered by a non-regulated bus
converter or a regulated bus converter. See Ordering Information for
input voltage range.
A ground layer will increase the stray capacitance in the PWB
and improve the high frequency EMC performance.
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MDC_OKDx-T/50-W12-C.A06 Page 19 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Input Under Voltage Lockout, UVLO
The product monitors the input voltage and will turn-on and turn-off at
configured levels. The default turn-on input voltage level setting is 4.20 V,
whereas the corresponding turn-off input voltage level is 3.85 V. Hence,
the default hysteresis between turn-on and turn-off input voltage is 0.35 V.
Once an input turn-off condition occurs, the device can respond in a
number of ways as follows:
1.
Continue operating without interruption. The unit will continue to
operate as long as the input voltage can be supported. If the input
voltage continues to fall, there will come a point where the unit will
cease to operate.
2.
Continue operating for a given delay period, followed by shutdown if
the fault still exists. The device will remain in shutdown until
instructed to restart.
I inputRMS = I load D (1–D),
where I load is the output load current and D is the duty cycle. The
maximum load ripple current becomes I load 2 . The ripple current is
divided into three parts, i.e., currents in the input source, external input
capacitor, and internal input capacitor. How the current is divided depends
on the impedance of the input source, ESR and capacitance values in the
capacitors. A minimum capacitance of 300 μF with low ESR is
recommended. The ripple current rating of the capacitors must follow
Eq. 1. For high-performance/transient applications or wherever the input
source performance is degraded, additional low ESR ceramic type
capacitors at the input is recommended. The additional input low ESR
capacitance above the minimum level insures an optimized performance.
Output capacitors:
When powering loads with significant dynamic current requirements, the
voltage regulation at the point of load can be improved by addition of
decoupling capacitors at the load.
The default response from a turn-off is an immediate shutdown of the
The most effective technique is to locate low ESR ceramic and electrolytic
device. The device will continuously check for the presence of the fault
capacitors as close to the load as possible, using several capacitors in
condition. If the fault condition is no longer present, the product will be reenabled. The turn-on and turn-off levels and response can be reconfigured parallel to lower the effective ESR. The ceramic capacitors will handle highfrequency dynamic load changes while the electrolytic capacitors are used
using the PMBus interface.
to handle low frequency dynamic load changes. Ceramic capacitors will
also reduce high frequency noise at the load.
Remote Control
It is equally important to use low resistance and low inductance PWB
The product is equipped with a remote layouts and cabling.
control function, i.e., the CTRL pin. The External decoupling capacitors are a part of the control loop of the product
Vext
remote control can be connected to
and may affect the stability margins.
either the primary negative input
Stable operation is guaranteed for the following total capacitance CO in
connection (GND) or an external
CTRL
the
output decoupling capacitor bank where
voltage (Vext), which is a 3 - 5 V
positive supply voltage in accordance
Eq. 2. CO >C min , Cmax @ >470, 30000@ μF.
GND
to the SMBus Specification version
The decoupling capacitor bank should consist of capacitors which has a
2.0.
capacitance value larger than C t C min and has an ESR range of
The CTRL function allows the product to be turned on/off by an external
device like a semiconductor or mechanical switch. By default the product
Eq. 3.
ESR >ESRmin , ESRmax @ >5, 30@ mΩ
will turn on when the CTRL pin is left open and turn off when the CTRL pin
is applied to GND. The CTRL pin has an internal pull-up resistor. When the
The control loop stability margins are limited by the minimum time constant
CTRL pin is left open, the voltage generated on the CTRL pin is max 5.5 V.
W min of the capacitors. Hence, the time constant of the capacitors should
If the device is to be synchronized to an external clock source, the clock
follow Eq. 4.
frequency must be stable prior to asserting the CTRL pin.
Eq. 4. W t W min C min ESRmin 2.35 P s
The product can also be configured using the PMBus interface to be
“Always on
” or turn on/off can be performed with PMBus commands.
This relation can be used if your preferred capacitors have parameters
outside the above stated ranges in Eq. 2 and Eq.3.
Input and Output Impedance
The impedance of both the input source and the load will interact with the
impedance of the product. It is important that the input source has low
characteristic impedance. The performance in some applications can be
enhanced by addition of external capacitance as described under External
x If the capacitors capacitance value is C C min one must use at least
Decoupling Capacitors. If the input voltage source contains significant
N capacitors where
inductance, the addition a capacitor with low ESR at the input of the
C
product will ensure stable operation.
ªC º
N t « min » and ESR t ESRmin min .
C
C
»
«
External Capacitors
x If the ESR value is ESR ! ESRmax one must use at least N capacitors
Input capacitors:
of that type where
The input ripple RMS current in a buck converter is equal to
3.
Initiate an immediate shutdown until the fault has been cleared. The
user can select a specific number of retry attempts.
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MDC_OKDx-T/50-W12-C.A06 Page 20 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
ª ESR º
C min
N t«
.
» and C t
ESR
N
max »
«
x If the ESR value is ESR ESR min the capacitance value should be
ESRmin
.
ESR
For a total capacitance outside the above stated range or capacitors that do
not follow the stated above requirements above a re-design of the control
loop parameters will be necessary for robust dynamic operation and
stability.
C t C min
Control Loop
The product uses a voltage-mode synchronous buck controller with a fixed
frequency PWM scheme. Although the product uses a digital control loop, it
operates much like a traditional analog PWM controller. As in the analog
controller case, the control loop compares the output voltage to the desired
voltage reference and compensation is added to keep the loop stable and
fast. The resulting error signal is used to drive the PWM logic. Instead of
using external resistors and capacitors required with traditional analog
control loops, the product uses a digital Proportional-Integral-Derivative
(PID) compensator in the control loop. The characteristics of the control
loop is configured by setting PID compensation parameters. These PID
settings can be reconfigured using the PMBus interface.
Dynamic Loop Compensation (DLC)
The DLC feature might in some documents be referred to as “Auto
Compensation” or “Auto Tuning” feature.
The DLC feature measures the characteristics of the power train and
calculates the proper compensator PID coefficients.
The default configuration is that once the output voltage ramp up has
completed, the DLC algorithm will begin and a new optimized
compensator solution (PID setting) will be found and implemented. The
DLC algorithm typically takes between 50 ms and 200 ms to complete.
By the PMBus command AUTO_COMP_CONFIG the user may select
between several different modes of operation:
x
x
x
x
Disable
Autocomp once, will run DLC algorithm each time the output is
enabled (default configuration)
Autocomp every second will initiate a new DLC algorithm each 1
second
Autocomp every minute will initiate a new DLC algorithm every
minute.
The DLC can also be configured to run once only after the first ramp up
(after input power have been applied) and to use that temporary stored PID
settings in all subsequent ramps. If input power is cycled a new DLC
algorithm will be performed after the first ramp up. The default setting is
however to run the DLC algorithm after every ramp up.
The DLC algorithm can also be initiated manually by sending the
AUTO_COMP_CONTROL command.
The DLC can also be configured with Auto Comp Gain Control. This scales
the DLC results to allow a trade-off between transient response and
steady-state duty cycle jitter. A setting of 100% will provide the fastest
transient response while a setting of 10% will produce the lowest jitter.
The default is 50%.
Changing DLC and PID Setting
Some caution must be considered while DLC is enabled and when it is
changed from enabled or disabled.
When operating, the controller IC uses the settings loaded in its (volatile)
RAM memory. When the input power is applied the RAM settings are
retrieved from the pin-strap resistors and the two non-volatile memories
(DEFAULT and USER). The sequence is described in the “Initialization
Procedure” section.
When DLC is enabled:
When DLC is enabled, the normal sequence (after input power has been
applied) that a value stored in the user non-volatile memory overwrites any
previously loaded value does not apply for the PID setting (stored in the
PID_TAPS register). The PID setting in the user non-volatile memory is
ignored and a non-configurable default PID setting is loaded to RAM to act
as a safe starting value for the DLC. Once the output has been enabled and
the DLC algorithm has found a new optimized PID setting, it will be loaded
in RAM and used by the control loop.
When saving changes to the user non-volatile memory, all changes made
to the content of RAM will be saved. This also includes the default PID
setting (loaded to RAM to act as a safe starting value) or the PID setting
changed by the DLC algorithm after enabling output. The result is that as
long as DLC is enabled the PID setting in the user non-volatile memory is
ignored, but it might accidentally get overwritten.
When changing DLC from disabled to enabled:
A non-configurable default PID setting is loaded to RAM to act as a safe
starting value for the DLC (same as above).
When changing DLC from enabled to disabled:
When changing DLC from enabled to disabled, the PID setting in the user
non-volatile memory will be loaded to RAM. Any new optimized PID setting
in RAM will be lost, if not first stored to the user non-volatile memory.
When DLC is disabled:
When DLC is disabled and input power has been applied, the PID setting in
the user non-volatile memory will be loaded to RAM and used in the control
loop.
The original PID setting in the user non-volatile memory is quite slow and
not recommended for optimal performance. If DLC is disabled it is
recommended to either:
1. Use the DLC to find optimized PID setting.
2. Use Ericsson Power Designer to find appropriate PID setting.
3. Use Universal PID as defined below.
The Universal PID setting (taps) is:
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MDC_OKDx-T/50-W12-C.A06 Page 21 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
A = 3289.56,
B = -6248.12,
C = 2964.06
Write 0x7CB941FDC3417CCD99 to PID_TAPS register and write
command STORE_USER_ALL
Note that if DLC is enabled, for best results VI must be stable before
DLC algorithm begins.
Load Transient Response Optimization
The product incorporates a Non-Linear transient Response, NLR, loop
that decreases the response time and the output voltage deviation
during a load transient. The NLR results in a higher equivalent loop
bandwidth than is possible using a traditional linear control loop. The
product is pre-configured with appropriate NLR settings for robust and
stable operation for a wide range of input voltage and a capacitive
load range as defined in the section External Decoupling Capacitors.
For an application with a specific input voltage, output voltage, and
capacitive load, the NLR configuration can be optimized for a robust
and stable operation and with an improved load transient response.
This will also reduce the amount of output decoupling capacitors and
yield a reduced cost. However, the NLR slightly reduces the efficiency. In order to obtain maximal energy efficiency the load transient
requirement has to be met by the standard control loop compensation
and the decoupling capacitors. The NLR settings can be reconfigured
using the PMBus interface.
Remote Sense
The product has remote sense that can be used to compensate for
voltage drops between the output and the point of load. The sense
traces should be located close to the PWB ground layer to reduce
noise susceptibility. Due to derating of internal output capacitance
the voltage drop should be kept below VDROPMAX = (5.5–VO)/2. A large
voltage drop will impact the electrical performance of the regulator. If
the remote sense is not needed, +S should be connected to VOUT and
−S should be connected to GND.
Output Voltage Adjust using Pin-strap Resistor
Using an external Pin-strap resistor, RSET, the output voltage can
be set in the range 0.6 V to 3.3
VSET
V at 28 different levels shown
R SET
in the table below. The resistor
PREF
should be applied between the
VSET pin and the PREF pin.
RSET also sets the maximum output voltage, see section “Output
Voltage Range Limitation.” The resistor is sensed only during product
start-up. Changing the resistor value during normal operation will
not change the output voltage. The input voltage must be at least 1
V larger than the output voltage in order to deliver the correct output
voltage. See Ordering Information for output voltage range.
VO [V]
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
RSET[kΩ]
10
11
12.1
13.3
14.7
16.2
17.8
19.6
21.5
23.7
26.1
28.7
31.6
1.25
1.30
1.40
34.8
38.3
42.2
VO [V]
1.50
1.60
1.70
1.80
1.90
2.00
2.10
2.20
2.30
2.50
3.00
3.30
RSET[kΩ]
46.4
51.1
56.2
61.9
68.1
75
82.5
90.9
100
110
121
133
The output voltage and the maximum output voltage can be pin
strapped to three fixed values by connecting the VSET pin according
to the table below.
VO [V]
0.60
1.2
2.5
VSET
Shorted to PREF
Open “high impedance”
Logic High, GND as reference
Output Voltage Adjust using PMBus
The output voltage set by pin-strap can be overridden by configuration
file or by using a PMBus command. See Electrical Specification for
adjustment range.
When setting the output voltage by configuration file or by a PMBus
command, the specified output voltage accuracy is valid only when
the set output voltage level falls within the same bin range as the
voltage level defined by the pin-strap resistor RSET. The applicable bin
ranges are defined in the table below. Valid accuracy for voltage levels
outside the applicable bin range is two times the specified.
Example:
Nominal VO is set to 1.10 V by RSET = 26.1 kΩ. 1.10 V falls within the
bin range 0.988-1.383 V, thus specified accuracy is valid when adjusting VO within 0.988-1.383V.
VO bin ranges [V]
0.600 – 0.988
0.988 – 1.383
1.383 – 1.975
1.975 – 2.398
2.398 – 2.963
2.963 – 3.753
Output Voltage Range Limitation
The output voltage range that is possible to set by configuration or
by the PMBus interface is limited by the pin-strap resistor RSET. The
maximum output voltage is set to 110% of the nominal output value
defined by RSET, VO,MAX = 1.1 x VO,RSET. This protects the load from an
over voltage due to an accidental wrong PMBus command.
The following table shows recommended resistor values for RSET.
Maximum 1% tolerance resistors are required.
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MDC_OKDx-T/50-W12-C.A06 Page 22 of 41
OKDx-T/50-W12-C
50A Digital PoL DC-DC Converter Series
Output Voltage Adjust Limitation using PMBus
In addition to the maximum output voltage limitation by the pin-strap
resistor RSET, there is also a limitation in how much the output voltage can be increased while the output is enabled. If output is disabled
then RSET resistor is the only limitation.
falls below 85% of the nominal voltage. These limits may be changed
via the PMBus interface. A PG delay period is defined as the time from
when all conditions within the product for asserting PG are met to
when the PG signal is actually asserted. The default PG delay is set to
10 ms. This value can be reconfigured using the PMBus interface.
Example:
If the output is enabled with output voltage set to 1.0 V, then it is only
possible to adjust/change the output voltage up to 1.7- V as long as
the output is enabled.
For products with DLC the PG signal is by default asserted directly
after the DLC operation have been completed. If DLC is disabled the
configured PG delay will be used. This can be reconfigured using the
PMBus interface.
VO setting
when enabled [V]
0.000 – 0.988
0.988 – 1.383
1.383 – 1.975
1.975 – 2.398
2.398 – 2.963
2.963 – 3.753
VO set range
while enabled [V]
~0.2 to >1.2
~0.2 to >1.7
~0.2 to >2.5
~0.2 to >2.97
~0.2 to >3.68
~0.2 to >4.65
Over Voltage Protection (OVP)
The product includes over voltage limiting circuitry for protection
of the load. The default OVP limit is 15% above the nominal output
voltage. If the output voltage exceeds the OVP limit, the product can
respond in different ways:
1. Initiate an immediate shutdown until the fault has been cleared.
The user can select a specific number of retry attempts.
2. Turn off the high-side MOSFET and turn on the low-side MOSFET.
The low-side MOSFET remains ON until the device attempts a
restart, i.e. the output voltage is pulled to ground level (crowbar
function).
The default response from an overvoltage fault is to immediately
shut down as in 2. The device will continuously check for the presence of the fault condition, and when the fault condition no longer
exists the device will be re-enabled. For continuous OVP when
operating from an external clock for synchronization, the only allowed
response is an immediate shutdown. The OVP limit and fault response
can be reconfigured using the PMBus interface.
Under Voltage Protection (UVP)
The product includes output under voltage limiting circuitry for
protection of the load. The default UVP limit is 15% below the nominal
output voltage. The UVP limit can be reconfigured using the PMBus
interface.
Power Good
The product provides a Power Good (PG) flag in the Status Word register that indicates the output voltage is within a specified tolerance
of its target level and no fault condition exists. If specified in section
Connections, the product also provides a PG signal output. The PG pin
is active high and by default open-drain but may also be configured
as push-pull via the PMBus interface.
By default, the PG signal will be asserted when the output reaches
above 90% of the nominal voltage, and de-asserted when the output
Switching Frequency
The fundamental switching frequency is 320 kHz, which yields
optimal power efficiency. The switching frequency can be set to any
value between 200 kHz and 640 kHz using the PMBus interface. The
switching frequency will change the efficiency/power dissipation,
load transient response and output ripple. For optimal control loop
performance in a product without DLC, the control loop must be reoptimized when changing the switching frequency.
Synchronization
Synchronization is a feature that allows multiple products to be synchronized to a common frequency. Synchronized products powered
from the same bus eliminate beat frequencies reflected back to the
input supply, and also reduces EMI filtering requirements. Eliminating
the slow beat frequencies (usually
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