OKDx-T/90-W12-xxx-C
90A Digital PoL DC-DC Converter Series
Typical units
FEATURES
PRODUCT OVERVIEW
The OKDx-T/90-W12 series are high efficiency, digital
Point-of-Load (PoL) DC-DC power converters capable
of delivering 90A/162W. Available in three different
package formats, Surface Mount, Through-Hole and
Single-Inline-Package, these converters have a
typical efficiency of 94.3%. PMBus™ compatibility
allows monitoring and configuration of critical
system-level performance requirements.
Apart from standard PoL performance and safety
features like OVP, OCP, OTP, and UVLO, these
digital converters have advanced features: digital
current sharing (full power, no derating), non-linear
transient response, optimized dead time control,
synchronization, and phase spreading. These
converters are ideal for use in telecommunications,
networking, and distributed power applications.
Power Management via PMBus™
Applications
Input voltage range of 7.5 to 14Vdc
0.6 V - 1.8 V output voltage range
High efficiency, typ. 94.3% at 12Vin,
1.8Vout half-load
TH package: 50.8 x 19.05 x 10.0 mm
(2.0 x 0.75 x 0.39 in) SIP: 50.8 x 9.51 x
19.05 mm (2.0 x 0.37 x 0.75 in)
Configuration & Monitoring via PMBus™
Synchronization & phase spreading
Current sharing, Voltage Tracking &
Voltage margining
MTBF 14.95 Mhrs
Non-Linear Response for reduction of
decoupling capacitor
Remote On/Off control & Power Good
Output short-circuit, output over
voltage, & over temperature protection
Certified to UL/IEC 60950-1
Configurable soft-start/stop
Configurable output voltage (Vout) and voltage
margins (Margin low and Margin high)
Configurable protection limits for OVP, input over
voltage, input under voltage, over current, on/off,
and temperature
Status monitor Vout, Iout, Vin, Temp, Power Good,
and On/Off
Distributed power architectures
Intermediate bus voltage applications
Servers and storage applications
Network equipment
PART NUMBER STRUCTURE
OKD x - T / 90 - W12 E - xxx - C
Digital Non-isolated PoL
Y = Surface Mount
H = Horizontal Mount Through-Hole
X = SIP
Trimmable Output
Voltage Range
0.6 - 1.8Vdc
Maximum Rated Output
Current in Amps
RoHS Hazardous
Substance Compliance
C = RoHS-6
(does not claim EU RoHS exemption 7b – lead in solder)
Software Configuration Digits
(001 is positive turn-on logic)
(002 is negative turn-on logic)*
SIP Version only
E = 5.5mm Pin Length*
Blank = 4.0mm Pin Length
Input Voltage Range
7.5-14Vdc
*Special quantity order is required;
contact Murata Power Solutions for
MOQ and lead times.
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MDC_OKDx-T/90-W12-xxx-C.A02 Page 1 of 71
OKDx-T/90-W12-xxx-C
90A Digital PoL DC-DC Converter Series
Ordering Guide
Model Number
OKDY-T/90-W12-001-C
OKDH-T/90-W12-001-C
OKDX-T/90-W12-001-C
Package Type
Surface Mount
Horizontal – Thru Hole
Single-Inline-Package
Output
Input Range
On/Off Logic
0.6-1.8V, 90A/162W
7.5V to 14V
Positive
Absolute Maximum Ratings
Characteristics
Min
TP1
TS
VI
Signal I/O voltage
Ground voltage
differential
Analog pin voltage
Operating temperature (see Thermal Consideration section)
Typ
Max
Unit
-40
150
°C
Storage temperature (Ambient)
Input voltage (See Operating Information Section for input
and output voltage relations)
CTRL, SA, SALERT, SCL, SDA, VSET, SYNC, PG, GCB, FAULT
-40
125
°C
-0.3
16
V
-0.3
6
V
-S, PREF, GND
-0.3
0.3
V
VO, +S, VTRK
-0.3
6.5
V
Max
Unit
General and Safety
Conditions
Safety
Designed for UL/IEC/EN 60950 1
Calculated MTBF
Telcordia SR-332, Issue 2 Method 1
Min
Typ
14.95
Mhrs
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those indicated in the Electrical Specification section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Configuration File
This product is designed with a digital control circuit. The control circuit uses a configuration file which determines the functionality and performance of
the product. The Electrical Specification table shows parameter values of functionality and performance with the Standard configuration, unless
otherwise specified. The Standard configuration is designed to fit most application needs. Changes in Standard configuration might be required to
optimize performance in specific application. Note that current sharing operation requires changed configuration.
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MDC_OKDx-T/90-W12-xxx-C.A02 Page 2 of 71
OKDx-T/90-W12-xxx-C
90A Digital PoL DC-DC Converter Series
Product Electrical Specifications
OKDY-T/90-W12-xxx-C, OKDH-T/90-W12-xxx-C and OKDX-T/90-W12-xxx-C
TP1 = -30 to +95 °C, VI = 7.5 to 14 V, unless otherwise specified under Conditions.
Typical values given at: TP1 = +25 °C, VI = 12.0 V, max IO, unless otherwise specified under Conditions.
VO defined by pin strap. Standard configuration.
Tested with external CIN = 1000 μF/12 mΩ + 24 x 10 μF, COUT = 10 x 470 μF/5 mΩ + 10 x 100 μF. See Operating Information section for design of input and output filters
for a specific application.
In the test set-up sense lines are connected directly to output pins on a converter and all the output voltage measurements are made on output pins.
Characteristics
VI
VO
Conditions
Input voltage
Input voltage slew rate
IO = max IO
Load regulation
IO = 0 - 100%
IO
Ilim
Output current
Current limit threshold
Isc
Short circuit current
Unit
14
6
V
V/ms
0.6
1.8
V
V
0.54
1.98
V
1.2
±0.025
Including line, load, temp
-1
-100
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
0
100
50% of max IO
η
Max
Monotonic
Line regulation
Output ripple & noise
(up to 20 MHz)
Typ
7.5
Output voltage without pin-strap
Output voltage adjustment range
Output voltage adjustment including PMBus
margining
Output voltage set-point resolution
Output voltage accuracy, Note 8
Internal resistance +S/-S to VOUT/GND
+S bias current
-S bias current
VOac
Min
Efficiency
IO = max IO
Pd
Power dissipation at max IO
Pli
Input idling power
PCTRL
CI
CO
Input standby power
Internal input capacitance
Internal output capacitance
IO = 0
1
47
20
20
2
2
2
2
2
2
2.5
3.5
5.0
114
RMS, hiccup mode,
VO = 1.0 V, 0.4 mΩ short
12
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
Turned off with CTRL-pin
VI = 0 V
VO = 0 V
87.6
91.4
94.3
83.7
88.7
92.5
10.5
11.5
13.1
1.29
1.35
1.82
0.44
257
700
100
% VO
% VO
Ω
µA
µA
mV
mV
mVp-p
90
125
A
A
A
%
%
W
W
W
μF
μF
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MDC_OKDx-T/90-W12-xxx-C.A02 Page 3 of 71
OKDx-T/90-W12-xxx-C
90A Digital PoL DC-DC Converter Series
Common Electrical Specifications
This section includes parameter specifications common to all product versions within the product series. Typically these are parameters defined by the digital controller of
the products. In the table below PMBus commands for configurable parameters are written in capital letters.
TP1 = -30 to +95 °C, VI = 7.5 to 14 V, unless otherwise specified under Conditions.
Typical values given at: TP1 = +25 °C, VI = 12.0 V, max IO, unless otherwise specified under Conditions.
VO defined by pin-strap. Standard configuration.
Characteristics
Conditions
Min
Switching Frequency
Switching Frequency Range, Note 1
fSW = 1/TSW
TINIT
TONdel_tot
TONdel
TOFFdel
TONrise /
TOFFfall
Switching Frequency Set-point Accuracy
External Sync Pulse Width
Input Clock Frequency Drift Tolerance
Initialization Time
Output voltage
Total On Delay Time
Output voltage
On Delay Time
Output voltage
Off Delay Time
Output voltage
On/Off
Ramp Time
(0-100%-0 of VO)
PMBus configurable
FREQUENCY_SWITCH
External sync
From VI > ~2.7 V to ready to be enabled
Enable by input voltage
Enable by CTRL pin
Turn on delay duration
Range PMBus configurable
TON_DELAY
Accuracy (actual delay vs set value)
Turn off delay duration, Note 2
Range PMBus configurable
TOFF_DELAY
Accuracy (actual delay vs set value), Note 3
Turn on ramp duration
Turn off ramp duration
Ramp duration range
PMBus configurable
TON_RISE/TOFF_FALL
Ramp time accuracy for standalone operation (actual
ramp time vs set value)
Characteristics
Conditions
PG threshold
Rising
Falling
PG thresholds range
PMBus configurable
POWER_GOOD_ON
VOUT_UV_FAULT_LIMIT
Power Good, PG
PG delay
PG delay range
Max
From VO reaching target to PG
assertion
PMBus configurable
POWER_GOOD_DELAY
IUVP threshold range
640
kHz
-5
150
-10
5
%
ns
%
Set point accuracy
IUVP response delay
Fault response
10
67
TINIT + TONdel
TONdel
5
3
ms
ms
250
-0/+2
0
4
250
0
100
±250
Min
Typ
Max
2
VIN_UV_FAULT_RESPONSE
0
Unit
% VO
ms
V
14
0.5
PMBus configurable
VIN_UV_WARN_LIMIT
ms
ms
5000
6.4
ms
ms
% VO
% VO
100
0
ms
µs
90
85
0
ms
ms
ms
-0/+2
5
Disabled in standard configuration. Turn off immediately
upon expiration of Turn off delay.
IUVP hysteresis
IUVP hysteresis range
kHz
6.4
PMBus configurable
VIN_UV_FAULT_LIMIT
Unit
200
IUVP threshold
Input Under Voltage
Protection,
IUVP
Typ
320
V
V
7.6
±280
100
Shutdown, automatic restart, 280 ms. Note 4
V
mV
μs
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MDC_OKDx-T/90-W12-xxx-C.A02 Page 4 of 71
OKDx-T/90-W12-xxx-C
90A Digital PoL DC-DC Converter Series
Characteristics
Conditions
Min
Typ
IOVP threshold
IOVP threshold range
Input Over Voltage
Protection,
IOVP
Set point accuracy
IOVP response delay
Fault response
UVP threshold
UVP threshold range
Output Voltage
Over/Under Voltage
Protection,
OVP/UVP
PMBus configurable
VIN_OV_FAULT_LIMIT
6.9
1
PMBus configurable
VIN_OV_WARN_LIMIT
VIN_OV_FAULT_RESPONSE
PMBus configurable
VOUT_UV_FAULT_LIMIT
0
±280
100
Shutdown, automatic restart, 280 ms. Note 4
85
OVP threshold
OVP threshold range
100
115
PMBus configurable
VOUT_OV_FAULT_LIMIT
100
Fault response
OCP threshold
Over Current Protection,
OCP
Note 5
Over Temperature
Protection,
OTP
Position P3
Note 7
Over Temperature
Protection,
OTP
Position P1 / P2
Note 7
OCP threshold range
Protection delay
Fault response
OTP threshold
OTP threshold range
OTP hysteresis
Fault response
OTP Threshold
OTP Threshold range
OTP Hysteresis
Fault response
10
VOUT_UV_FAULT_RESPONSE
VOUT_OV_FAULT_RESPONSE
PMBus configurable
OT_FAULT_LIMIT
PMBus configurable
OT_FAULT_RESPONSE
PMBus configurable
MFR_VMON_OV_FAULT_LIMIT
VMON_OV_FAULT_RESPONSE
% VO
% VO
% VO
μs
57
A
0-57
A
5
Shutdown, automatic restart, 280 ms. Note 4
125
TSW
IOUT_AVG_OC_FAULT_LIMIT
MFR_IOUT_OC_FAULT_RESPONSE
mV
μs
Shutdown, automatic restart, 280 ms. Note 4
Set value per phase
PMBus configurable
See Note 6
V
% VO
115
UVP/OVP response time
V
V
9.1
0
Unit
V
16
IOVP hysteresis
IOVP hysteresis range
Max
16
-40
+125
15
Shutdown, automatic restart, 280 ms. Note 4
150
-40
+150
25
Shutdown, automatic restart, 280 ms. Note 4
°C
°C
°C
°C
°C
°C
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MDC_OKDx-T/90-W12-xxx-C.A02 Page 5 of 71
OKDx-T/90-W12-xxx-C
90A Digital PoL DC-DC Converter Series
Characteristics
Conditions
Min
Input voltage
READ_VIN
Output voltage
READ_VOUT
Monitoring Accuracy
TP1 = 25 °C, VO = 1.0 V
TP1 = 0 - 95 °C, VO = 1.0 V
Output current
READ_IOUT
Duty cycle
READ_DUTY_CYCLE
Temperature
READ_TEMPERATURE_1
Position P3, TP3 = 0 - 95 °C
VTRK = 5 V
Tracking Input Voltage Range
VTRK pin
Tracking Rise-Time
VTRK pin
Tracking Accuracy
Regulation 100% tracking
VOL
Logic output high signal level
IOL
IOH
VIL
VIH
II_LEAK
CI_PIN
Logic output low sink current
Logic output high source current
Logic input low threshold
Logic input high threshold
Logic leakage current
Logic pin input capacitance
RI_PU
Logic pin internal pull-up resistance
fSMB
Supported SMBus Operating frequency
TBUF
SMBus Bus free time
tset
thold
SMBus SDA setup time from SCL
SMBus SDA hold time from SCL
SMBus START/STOP condition setup/hold time
from SCL
SCL low period
SCL high period
Tlow
Thigh
Unit
±280
mV
±1
% VO
±1
±3.5
A
A
-10
70
5
°C
200
µA
5
V
1
V/ms
2
% VO
0
Steady state operation
-2
Max 2 x READ_IOUT monitoring accuracy
4
Logic output low signal level
VOH
Max
No tolerance, Read value is the actual value applied by
PWM controller.
Tracking Input Bias Current
Current difference between products in a current sharing
group
Supported number of products in a current sharing group
Typ
0.5
SCL, SDA, SYNC, GCB, SALERT, PG
Sink / source current = 2 mA
SCL, SDA, CTRL, SYNC, GCB
SCL, SDA, SYNC, SALERT, PG
SCL, SDA, CTRL, SYNC, GCB
SCL, SDA, SALERT
CTRL to +5V
GCB to +5V
2.25
V
2
2
0.8
2
-100
100
12
No internal pull-up
10
47
100
STOP bit to START bit
See section SMBus – Timing
See section SMBus – Timing
See section SMBus – Timing
V
400
mA
mA
V
V
µA
pF
kΩ
kΩ
kHz
1.3
µs
100
300
ns
ns
600
ns
1.3
0.6
µs
µs
Note 1. There are configuration changes to consider when changing the switching frequency, see section Switching Frequency.
Note 2. A default value of 0 ms forces the device to Immediate Off behavior with TOFF_FALL ramp-down setting being ignored.
Note 3. The specified accuracy applies for off delay times larger than 4 ms. When setting 0 ms the actual delay will be 0 ms.
Note 4. Automatic restart ~280 ms after fault if the fault is no longer present. Continuous restart attempts if the fault reappear after restart. See Operating Information for other fault response options.
Note 5. The set OCP limit applies per phase. The total OCP limit will be twice the set value. Note that higher OCP threshold than specified may result in damage of the module at OC fault conditions.
Note 6. TSW is the switching period.
Note 7. See section Over Temperature Protection (OTP).
Note 8. For VO < 1.0 V accuracy is +/-10 mV. For further exceptions see section Output Voltage Adjust using PMBus.
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MDC_OKDx-T/90-W12-xxx-C.A02 Page 6 of 71
OKDx-T/90-W12-xxx-C
90A Digital PoL DC-DC Converter Series
Typical Output Characteristics, VO = 0.6 V
Standard configuration unless otherwise specified, TP1 = +25 °C
Efficiency
Power Dissipation
[%]
[W]
100
15
95
12
VI
VI
90
7.5 V
85
9.6 V
80
12 V
75
14 V
7.5 V
9
9.6 V
6
12 V
14 V
3
0
70
0
10
20
30
40
50
60
70
80
0
90 [A]
20
30
40
50
60
70
80
90 [A]
Efficiency vs. load current and input voltage.
Dissipated power vs. load current and input voltage.
Output Current Derating for SIP version
Output Current Derating for Horizontal versions
[A]
[A]
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
3.0 m/s
2.0 m/s
1.0 m/s
0.5 m/s
Nat. Conv.
0
10
20
40
60
80
100
120 [°C]
3.0 m/s
2.0 m/s
1.0 m/s
0.5 m/s
Nat. Conv.
0
20
40
60
80
100
120 [°C]
Available load current vs. ambient air temperature and airflow at
VI = 12 V. See section Thermal Consideration.
Available load current vs. ambient air temperature and airflow at
VI = 12 V. See section Thermal Consideration.
Output Ripple and Noise
Transient Response
Fundamental output voltage ripple at VI = 12 V, IO = max IO,
COUT = 10 x 470 µF/5 mΩ + 10 x 100 µF.
Scale: 5 mV/div, 2 µs/div, 20 MHz bandwidth.
See section Output Ripple and Noise.
Output voltage response to load current step change (22.5–67.5–22.5 A) at
VI = 12 V, COUT = 10 x 470 µF/5 mΩ + 10 x 100 µF, di/dt = 2 A/µs,
ASCR Gain = 550 and ASCR Residual = 90.
Scale from top: 50 mV/div, 20 A/div, 100 µs/div.
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MDC_OKDx-T/90-W12-xxx-C.A02 Page 7 of 71
OKDx-T/90-W12-xxx-C
90A Digital PoL DC-DC Converter Series
Typical Output Characteristics, VO = 1.0 V
Standard configuration unless otherwise specified, TP1 = +25 °C
Efficiency
Power Dissipation
[%]
[W]
100
15
95
12
VI
VI
90
7.5 V
85
9.6 V
80
12 V
75
14 V
7.5 V
9
9.6 V
6
12 V
14 V
3
0
70
0
10
20
30
40
50
60
70
80
0
90 [A]
20
30
40
50
60
70
80
90 [A]
Efficiency vs. load current and input voltage.
Dissipated power vs. load current and input voltage.
Output Current Derating for SIP version
Output Current Derating for Horizontal versions
[A]
[A]
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
3.0 m/s
2.0 m/s
1.0 m/s
0.5 m/s
Nat. Conv.
0
10
20
40
60
80
100
120 [°C]
3.0 m/s
2.0 m/s
1.0 m/s
0.5 m/s
Nat. Conv.
0
20
40
60
80
100
120 [°C]
Available load current vs. ambient air temperature and airflow at
VI = 12 V. See section Thermal Consideration.
Available load current vs. ambient air temperature and airflow at
VI = 12 V. See section Thermal Consideration.
Output Ripple and Noise
Transient Response
Fundamental output voltage ripple at VI = 12 V, IO = max IO,
COUT = 10 x 470 µF/5 mΩ + 10 x 100 µF.
Scale: 5 mV/div, 2 µs/div, 20 MHz bandwidth.
See section Output Ripple and Noise.
Output voltage response to load current step change (22.5–67.5–22.5 A) at
VI = 12 V, COUT = 10 x 470 µF/5 mΩ + 10 x 100 µF, di/dt = 2 A/µs,
ASCR Gain = 400 and ASCR Residual = 90.
Scale from top: 50 mV/div, 20 A/div, 100 µs/div.
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MDC_OKDx-T/90-W12-xxx-C.A02 Page 8 of 71
OKDx-T/90-W12-xxx-C
90A Digital PoL DC-DC Converter Series
Typical Output Characteristics, VO = 1.8 V
Standard configuration unless otherwise specified, TP1 = +25 °C
Efficiency
Power Dissipation
[%]
[W]
100
15
95
12
VI
VI
90
7.5 V
85
9.6 V
80
12 V
75
14 V
7.5 V
9
9.6 V
6
12 V
14 V
3
0
70
0
10
20
30
40
50
60
70
80
0
90 [A]
20
30
40
50
60
70
80
90 [A]
Efficiency vs. load current and input voltage.
Dissipated power vs. load current and input voltage.
Output Current Derating for SIP version
Output Current Derating for Horizontal versions
[A]
[A]
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
3.0 m/s
2.0 m/s
1.0 m/s
0.5 m/s
Nat. Conv.
0
10
20
40
60
80
100
120 [°C]
3.0 m/s
2.0 m/s
1.0 m/s
0.5 m/s
Nat. Conv.
0
20
40
60
80
100
120 [°C]
Available load current vs. ambient air temperature and airflow at
VI = 12 V. See section Thermal Consideration.
Available load current vs. ambient air temperature and airflow at
VI = 12 V. See section Thermal Consideration.
Output Ripple and Noise
Transient Response
Fundamental output voltage ripple at VI = 12 V, IO = max IO,
COUT = 10 x 470 µF/5 mΩ + 10 x 100 µF.
Scale: 5 mV/div, 2 µs/div, 20 MHz bandwidth.
See section Output Ripple and Noise.
Output voltage response to load current step change (22.5–67.5–22.5 A) at
VI = 12 V, COUT = 10 x 470 µF/5 mΩ + 10 x 100 µF, di/dt = 2 A/µs,
ASCR Gain = 350 and ASCR Residual = 90.
Scale from top: 50 mV/div, 20 A/div, 100 µs/div.
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MDC_OKDx-T/90-W12-xxx-C.A02 Page 9 of 71
OKDx-T/90-W12-xxx-C
90A Digital PoL DC-DC Converter Series
Typical On/Off Characteristics
Standard configuration, TP1 = +25 °C, VO = 1.0 V
Enable by input voltage – PG Open-Drain (default)
Disable by input voltage – PG Open-Drain (default)
VI
VI
VO
VO
PG
PG
Output enabled by applying VI. VI = 12 V, IO = max IO.
TON_DELAY = TON_RISE = 5 ms, POWER_GOOD_DELAY = 2 ms.
USER_CONFIG = 0x1480 (default). PG pulled up to external voltage.
Note: PG being high before Vin applied can be avoided by pulling up PG to Vout.
Scale from top: 10, 0.5, 2 V/div, 20 ms/div.
Output disabled by removing VI. VI = 12 V, IO = max IO.
Scale from top: 10, 0.5, 2 V/div, 1 ms/div.
Enable by input voltage – PG Push-Pull
Disable by input voltage – PG Push-Pull
Output enabled by applying VI. VI = 12 V, IO = max IO.
TON_DELAY = TON_RISE = 5 ms, POWER_GOOD_DELAY = 2 ms.
USER_CONFIG = 0x1484 (PG push-pull).
Scale from top: 10, 0.5, 2 V/div, 20 ms/div.
Output disabled by removing VI. VI = 12 V, IO = max IO.
Scale from top: 10, 0.5, 2 V/div, 1 ms/div.
Enable by CTRL pin
Disable by CTRL pin
VI
VO
PG
CTRL
CTRL
VO
VO
PG
PG
Output enabled by CTRL pin. VI = 12 V, IO = max IO.
TON_DELAY = TON_RISE = 5 ms, POWER_GOOD_DELAY = 2 ms.
Scale from top: 5, 0.5, 2 V/div, 10 ms/div.
Output disabled by CTRL pin. VI = 12 V, IO = max IO.
Scale from top: 5, 0.5, 2 V/div, 1 ms/div.
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MDC_OKDx-T/90-W12-xxx-C.A02 Page 10 of 71
OKDx-T/90-W12-xxx-C
90A Digital PoL DC-DC Converter Series
Typical Charactersitics
Standard configuration unless otherwise specified, TP1=+25 °C
Efficiency vs. Output Current and
Switching Frequency
Power Dissipation vs. Output Current and
Switching Frequency
[%]
[W]
95
15
200 kHz
12
200 kHz
VI
VI
85
320 kHz
9
320 kHz
80
480 kHz
6
480 kHz
75
640 kHz
3
640 kHz
90
70
0
0
10
20
30
40
50
60
70
80
90 [A]
0
10
20
30
40
50
60
70
80
90 [A]
Efficiency vs. load current and switching frequency at
VI = 12 V, VO = 1.0 V, CO = 10 x 470 µF/5 mΩ + 10 x 100 µF.
Frequency changed by PMBus command FREQUENCY_SWITCH.
Dissipated power vs. load current and switching frequency at
VI = 12 V, VO = 1.0 V, CO = 10 x 470 µF/5 mΩ + 10 x 100 µF.
Frequency changed by PMBus command FREQUENCY_SWITCH.
Output Ripple vs. Switching Frequency
Load Transient vs. ASCR Gain and
External Output Capacitance
[mVpk-pk]
[mV]
8
100
80
6
10x100
µF +
10x470
µF/5 mΩ
VO
0.6 V
4
2
60
1.0 V
40
1.8 V
20
0
10x100
µF +
4x470
µF/5 mΩ
0
200
300
400
500
600 [kHz]
Output voltage ripple Vpk-pk vs. switching frequency at
VI = 12 V, IO = max IO, CO = 10 x 470 µF/5 mΩ + 10 x 100 µF.
Frequency changed by PMBus command FREQUENCY_SWITCH.
150
200
250
300
350
400
450
500
Load transient peak voltage deviation vs. ASCR gain and external capacitance.
Step (22.5–67.5–22.5 A).
VI = 12 V, VO = 1.0 V, fsw = 320 kHz, ASCR residual =90, di/dt = 2 A/µs.
ASCR gain changed by PMBus command ASCR_CONFIG.
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MDC_OKDx-T/90-W12-xxx-C.A02 Page 11 of 71
OKDx-T/90-W12-xxx-C
90A Digital PoL DC-DC Converter Series
EMC Specification
Conducted EMI is measured according to the test set-up below. The typical
fundamental switching frequency is 320 kHz.
Output Ripple and Noise
Output ripple and noise are measured according to figure below. A 50 mm
conductor works as a small inductor forming together with the two
capacitances a damped filter.
Vout
+S
co
50 mm conductor
Tantalum
Capacitor
10 µF
Ceramic
Capacitor
0.1 µF
Load
Conducted EMI Input terminal value (typical for standard configuration). VI =
12 V, VO = 1.0 V, IO = 90 A.
−S
GND
50 mm conductor
BNC-contact to
oscilloscope
Output ripple and noise test set-up.
The digital compensation of the product is designed to automatically provide
stability, accurate line and load regulation and good transient performance for
a wide range of operating conditions (switching frequency, input voltage,
output voltage, output capacitance). Inherent from the implementation and
normal to the product there will be some low frequency ripple at the output, in
addition to the fundamental switching frequency output ripple. The total output
ripple and noise is maintained at a low level.
EMI without filter.
VI = 12 V, VO = 1.0 V, IO = 90 A, COUT = 10 x 470 μF/5 mΩ + 10 x 100 μF,
5 mV/div, 50 µs/div
Example of low frequency ripple at the output.
Test set-up conducted emission, power lead.
DUT = Product mounted on a 182 cm2 test board with the external capacitances CIN =
1000 μF/12 mΩ + 24 x 10 μF and COUT = 10 x 470 μF/5 mΩ + 10 x 100 μF.
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MDC_OKDx-T/90-W12-xxx-C.A02 Page 12 of 71
OKDx-T/90-W12-xxx-C
90A Digital PoL DC-DC Converter Series
PMBus Interface
Power Management Overview
This product incorporates a wide range of configurable power management
features that are simple to implement with a minimum of external
components. Additionally, the product includes protection features that
continuously safeguard the load from damage due to unexpected system
faults.
The product’s standard configuration is suitable for a wide range of operation
in terms of input voltage, output voltage, and load. The configuration is stored
in an internal Non-Volatile Memory (NVM). All power management functions
can be reconfigured using the PMBus interface.
Throughout this document, different PMBus commands are referenced. A
detailed description of each command is provided in the appendix at the end of
this specification.
SMBus Interface
The product can be used with any standard two-wire I2C or SMBus host
device. See Electrical Specification for allowed clock frequency range. In
addition, the product is compatible with PMBus version 1.2 and includes an
SALERT line to help mitigate limitations related to continuous fault monitoring.
The PMBus signals SCL, SDA and SALERT require passive pull-up resistors as
stated in the SMBus Specification. Pull-up resistors values should be selected
to guarantee the rise time according to equation below:
τ = RP C p ≤ 1µs
where Rp is the pull-up resistor value and Cp is the bus loading. The maximum
allowed bus load is 400 pF. The pull-up resistor should be tied to an external
supply voltage in range from 2.5 to 5.5 V, which should be present prior to or
during power-up. If the proper power supply is not available, voltage dividers
may be applied. Note that in this case, the resistance in the equation above
corresponds to parallel connection of the resistors forming the voltage divider.
PMBus Addressing
The PMBus address is configured with a resistor connected between the SA
pin and the PREF pin, as shown in the Typical Application Circuit.
Recommended resistor values are shown in the table below. 1% tolerance
resistors are required.
RSA [kΩ]
Address
RSA [kΩ]
Address
0 (short)
0x26
42.2
0x28
10
0x19
46.4
0x29
11
0x1A
51.1
0x2A
12.1
0x1B
56.2
0x2B
13.3
0x1C
61.9
0x2C
14.7
0x1D
68.1
0x2D
16.2
0x1E
75
0x2E
17.8
0x1F
82.5
0x2F
19.6
0x20
90.9
0x30
21.5
0x21
100
0x31
23.7
0x22
110
0x32
26.1
0x23
121
0x33
28.7
0x24
133
0x34
31.6
0x25
147
0x35
34.8
0x26
162
0x36
38.3
0x27
178
0x37
Infinite (open)
0x28
Reserved Addresses
Addresses listed in the table below are reserved or assigned according to the
SMBus specification and may not be usable. Refer to the SMBus specification
for further information.
Address
Comment
0x00
General Call Address / START byte
0x01
CBUS address
0x02
Address reserved for different bus format
0x03 - 0x07
Reserved for future use
0x08
SMBus Host
0x09 - 0x0B
Assigned for Smart Battery
0x0C
SMBus Alert Response Address
0x28
Reserved for ACCESS.bus host
0x2C - 0x2D
Reserved by previous versions of the SMBus
specification
0x37
0x48 - 0x4B
Reserved for ACCESS.bus default address
Reserved by previous versions of the SMBus
specification
Unrestricted addresses
0x61
SMBus Device Default Address
0x78 - 0x7B
10-bit slave addressing
0x7C - 0x7F
Reserved for future use
0x40 - 0x44
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MDC_OKDx-T/90-W12-xxx-C.A02 Page 13 of 71
OKDx-T/90-W12-xxx-C
90A Digital PoL DC-DC Converter Series
Monitoring via PMBus
It is possible to continuously monitor a wide variety of parameters through the
PMBus interface. These include, but are not limited to, the parameters listed in
the table below.
Parameter
Input voltage
PMBus Command
READ_VIN
Output voltage
READ_VOUT
Total output current
Controller temperature (TP3)
READ_IOUT
READ_IOUT0
READ_IOUT1
READ_TEMPERATURE_1
Switching frequency
READ_FREQUENCY
Duty cycle
Highest temperature of power
switches (TP1, TP2)
READ_DUTY_CYCLE
Output current of each phase
MFR_READ_VMON *
* Reports a voltage level corresponding to the temperature. See command details in the
end of this specification for formula to use.
Monitoring Faults
Fault conditions can be monitored using the SALERT pin, which will be
asserted low when any number of pre-configured fault or warning conditions
occur. The SALERT pin will be held low until faults and/or warnings are cleared
by the CLEAR_FAULTS command, or until the output voltage has been reenabled.
It is possible to mask which fault conditions should not assert the SALERT pin
by the command MFR_SMBALERT_MASK.
In response to the SALERT signal, the user may read a number of status
commands to find out what fault or warning condition occurred, see table
below.
Fault & Warning Status
Overview, Power Good
PMBus Command
STATUS_WORD
STATUS_BYTE
Output voltage level
STATUS_VOUT
Output current level
STATUS_IOUT
Input voltage level
STATUS_INPUT
Temperature level
STATUS_TEMPERATURE
PMBus communication
STATUS_CML
Miscellaneous
STATUS_MFR_SPECIFIC
Snapshot Parameter Capture
This product offers a special feature that enables the user to capture
parametric data during normal operation by a single PMBus command. The
following parameters are stored:
•
•
•
•
•
•
•
Input voltage
Output voltage
Output current
Controller temperature
Switching frequency
Duty cycle
Status and fault information
When a fault occurs the Snapshot functionality will automatically store this
parametric data to NVM. The data can then later be read back using the
SNAPSHOT command to provide valuable information for analysis. It is possible
to select which faults will trigger a store to NVM by the PMBus command
SNAPSHOT_FAULT_MASK.
PMBus/I2C Timing
SCL
VIH
VIL
SDA
VIH
VIL
tset
thold
Setup and hold times timing diagram.
The setup time, tset, is the time data, SDA, must be stable before the rising
edge of the clock signal, SCL. The hold time thold, is the time data, SDA, must
be stable after the falling edge of the clock signal, SCL. If these times are
violated incorrect data may be captured or meta-stability may occur and the
bus communication may fail. All standard SMBus protocols must be followed,
including clock stretching. Refer to the SMBus specification, for SMBus
electrical and timing requirements.
This product supports the BUSY flag in the status commands to indicate
product being too busy for SMBus response. A bus-free time delay according
to this specification must occur between every SMBus transmission (between
every stop & start condition).
The product supports PEC (Packet Error Checking) according to the SMBus
specification.
When sending subsequent commands to the same module, it is recommended
to insert additional delays according to the table below.
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MDC_OKDx-T/90-W12-xxx-C.A02 Page 14 of 71
OKDx-T/90-W12-xxx-C
90A Digital PoL DC-DC Converter Series
Command Protection
The user may write-protect specific PMBus commands in the User NVM by
using the command UNPROTECT.
Required delay before
additional command
After sending PMBus Command
STORE_USER_ALL
100 ms
Initialization Procedure
The product follows an internal initialization procedure after power is applied
to the VIN pins:
STORE_DEFAULT_ALL
RESTORE_USER_ALL
100 ms
RESTORE_DEFAULT_ALL
1. Self test and memory check.
10 ms
2 ms after reading
10 ms after writing
VOUT_MAX
Any other command
2. The address pin-strap resistors are measured and the associated PMBus
address is defined.
Non-Volatile Memory (NVM)
The product incorporates two Non-Volatile Memory areas for storage of the
PMBus command values; the Default NVM and the User NVM.
The Default NVM is pre-loaded with factory default values. The Default NVM is
write-protected and can be used to restore the factory default values through
the command RESTORE_DEFAULT_ALL.
The User NVM is pre-loaded with factory default values. The User NVM is
writable and open for customization. The values in NVM are loaded during
initialization according to section Initialization Procedure, whereafter
commands can be changed through the PMBus Interface. The
STORE_USER_ALL command will store the changed parameters to the User
NVM.
Pin-strap resistors
INITIALIZATION
Default NVM
INITIALIZATION
Factory default
Write-protected
RESTORE_DEFAULT_ALL
3. The output voltage pin-strap resistor is measured and the associated
output voltage level will be loaded to operational RAM of PMBus command
VOUT_COMMAND.
4. Factory default values stored in default NVM memory are loaded to
operational RAM. This overwrites any previously loaded values.
5. Values stored in the User NVM are loaded into operational RAM memory.
This overwrites any previously loaded values (e.g. VOUT_COMMAND by
pin-strap).
6. Check for external clock signal at the SYNC pin and lock internal clock to
the external clock if used.
Once this procedure is completed and the Initialization Time has passed (see
Electrical Specification), the output voltage is ready to be enabled using the
CTRL pin. The product is also ready to accept commands via the PMBus
interface, which in case of writes will overwrite any values loaded during the
initialization procedure.
RAM
User NVM
Factory default
Customizable
INITIALIZATION
STORE_USER_ALL
RESTORE_USER_ALL
Illustration Initialization time.
WRITE
PMBus interface
READ
Illustration of memory areas of the product.
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MDC_OKDx-T/90-W12-xxx-C.A02 Page 15 of 71
OKDx-T/90-W12-xxx-C
Operating Information
90A Digital PoL DC-DC Converter Series
Input Voltage
The input voltage range 7.5 - 14 V makes the product
easy to use in intermediate bus applications when powered
by a non-regulated bus converter or a regulated bus converter.
Input Under Voltage Protection (IUVP)
The product monitors the input voltage and will turn-on and turn-off at
configured thresholds (see Electrical Specification). The turn-on input voltage
threshold is set higher than the corresponding turn-off threshold. Hence, there
is a hysteresis between turn-on and turn-off input voltage levels. Once the
input voltage falls below the turn-off threshold, the device can respond in
several ways as follows:
1.
Immediate and definite shutdown of output voltage until the fault is
cleared by PMBus command CLEAR_FAULTS or the output voltage is reenabled.
2.
Immediate shutdown of output voltage while the input voltage is below
the turn-on threshold. Operation resumes automatically and the output is
enabled when the input voltage has risen above the turn-on threshold.
The default response is option 2. The IUVP function can be reconfigured using
the PMBus commands VIN_UV_FAULT_LIMIT (turn-off threshold),
VIN_UV_WARN_LIMIT (turn-on threshold) and VIN_UV_FAULT_RESPONSE.
For products configured to operate in current sharing mode, response option 1
will always be used, regardless of VIN_UV_FAULT_RESPONSE command
settings.
Input Over Voltage Protection (IOVP)
The product monitors the input voltage continuously and will respond as
configured when the input voltage rises above the configured threshold level
(see Electrical Specification). Refer to section “Input Under Voltage Protection”
for functionality, response configuration options and default setting.
The IOVP function can be reconfigured using the PMBus commands
VIN_OV_FAULT_LIMIT (turn-off threshold), VIN_OV_WARN_LIMIT (turn-on
threshold) and VIN_OV_FAULT_RESPONSE.
Input and Output Impedance
The impedance of both the input source and the load will interact with the
impedance of the product. It is important that the input source has low
characteristic impedance. If the input voltage source contains significant
inductance, the addition of a capacitor with low ESR at the input of the product
will ensure stable operation.
External Input Capacitors
The product is a two-phase converter which gives lower input ripple than a
single phase design, see picture below. Thus, ripple-current-rating
requirements for the input capacitors are lower relatively to a single phase
converter.
The input ripple RMS current in a two-phase buck converter can be estimated
to
I inputRMS = I load D(0.5 − D )
(valid for D < 0.5)
Where I load is the output load current and D is the duty cycle. The maximum
load ripple current becomes I load/4. The ripple current is divided into three
parts, i.e., currents in the input source, external input capacitor, and internal
input capacitor. How the current is divided depends on the impedance of the
input source, ESR and capacitance values in the capacitors.
For most applications non-tantalum capacitors are preferred due to the
robustness of such capacitors to accommodate high inrush currents of
systems being powered from very low impedance sources. It is recommended
to use a combination of ceramic capacitors and low-ESR electrolytic/polymer
bulk capacitors. The low ESR of ceramic capacitors effectively limits the input
ripple voltage level, while the bulk capacitance minimizes deviations in the
input voltage at large load transients.
If several products are connected in a phase spreading setup the amount of
input ripple current, and capacitance per product, can be reduced.
Ceramic input capacitors must be placed close to the input pins of a converter
and with low impedance connections to the VIN and GND pins in order to be
effective.
External Output Capacitors
The output capacitor requirement depends on two considerations; output ripple
voltage and load transient response. To achieve low ripple voltage, the output
capacitor bank must have a low ESR value, which is achieved with ceramic
output capacitors. A low ESR value is critical also for a small output voltage
deviation during load transients. Designs with smaller load transients can use
fewer capacitors and designs with more dynamic load content will require
more load capacitors to minimize output voltage deviation. Improved transient
response can also be achieved by adjusting the settings of the control loop of
the product. Adding output capacitance decreases loop band-width.
It is recommended to place low ESR ceramic and low ESR electrolytic/polymer
capacitors as close to the load as possible, using several capacitors in parallel
to lower the effective ESR. It is important to use low resistance and low
inductance PCB layouts in order for capacitance to be effective.
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MDC_OKDx-T/90-W12-xxx-C.A02 Page 16 of 71
OKDx-T/90-W12-xxx-C
90A Digital PoL DC-DC Converter Series
Dynamic Loop Compensation (DLC)
The typical design of regulated power converters includes a control function
with a feedback loop that can be closed using either analog or digital
circuits. The feedback loop is required to provide a stable output voltage, but
should be optimized for the output filter to maintain output voltage regulation
during transient conditions such as sudden changes in output current and/or
input voltage. Digitally controlled converters allow one to optimize loop
parameters without the need to change components on the board, however,
optimization can still be challenging because the key parameters of the output
filter include parasitic impedances in the PCB and the often distributed filter
components themselves.
[µs]
130
110
90
[mV]
100
80
10x100
µF +
10x470
µF/5 mΩ
60
50
30
50
60
20
80
90
100
110
Load step 22.5–67.5–22.5 A, di/dt = 2 A/µs.
VI = 12 V, VO = 1.0 V, fsw = 320 kHz, Gain factor = 300.
Residual factor changed by PMBus command ASCR_CONFIG.
Recovery time vs.control loop residual setting and output capacitance.
By default the product is configured with a moderate gain factor to provide a
trade-off between load transient performance and output ripple for a wide
range of operating conditions. For a specific application the gain factor can be
increased to improve load transient response.
Remote Sense
The product has remote sense to compensate the voltage drops between the
output and the point of load. The sense traces should be laid out as a
differential pair and preferably be shielded by the PCB ground layer to reduce
noise susceptibility. If the remote sense is not used, +S must be connected to
VOUT and −S must be connected to GND.
In cases where the external output filter includes an inductor (forming a pi
filter) according to the picture below, the LEXT/CEXT resonant frequency places
an upper limit on the controller loop bandwidth. If the resonance frequency is
high the sense lines can be connected after the filter (as shown in the picture)
– if the resonant frequency is low and the DC drop from LEXT is acceptable,
sensing before the filter may be better.
Vout
10x100
µF +
4x470
µF/5 mΩ
40
70
CO
LEXT
CEXT
Load
Control may be set more or less aggressive by adjusting a gain factor, set by
the PMBus command ASCR_CONFIG. Increasing the gain factor, i.e the control
effort, will reduce the voltage deviation at load transients, at the expense of
somewhat increased ripple on the output. Below graph exemplifies the effect
of the gain factor on the voltage deviation during a load transient. The typical
range of the gain factor is 200 - 600.
10x100
µF +
4x470
µF/5 mΩ
70
Dynamic Loop Compensation has been developed to solve the problem of
compensation for a converter with a difficult to define output filter. This task is
achieved by utilization of algorithms that can identify an arbitrary output filter
based on accurate measurements of the output voltage in response to a very
small excitation signal initiated by the algorithm, or occurring due to the
changes in operating conditions, and automatically adjust feedback loop
parameters to match the output filter.
Control Loop
The products use a fully digital control loop that achieves precise control of the
entire power conversion process, resulting in a very flexible device that is also
very easy to use.
A non-linear charge-mode control algorithm is implemented that responds to
output current changes within a single PWM switching cycle, achieving a
smaller total output voltage variation with less output capacitance than
traditional PWM controllers, thus saving cost and board space.
10x100
µF +
10x470
µF/5 mΩ
GND
-S
+S
0
150
200
250
300
350
400
450
500
Load step 22.5–67.5–22.5 A, di/dt = 2 A/µs.
VI = 12 V, VO = 1.0 V, fsw = 320 kHz, Residual factor = 90.
Gain factor changed by PMBus command ASCR_CONFIG.
Voltage deviation vs. control loop gain setting and output capacitance.
The user may also adjust the residual factor, set by the ASCR_CONFIG
command, to improve the recovery time after a load transient. The typical
usable range of the residual factor is 70 - 127. A higher value than 127 may
damage the device and must not be used. A graph below illustrates the
effect of the residual factor on the recovery time after a load transient. Note
that also the gain factor will affect the recovery time.
External output filter with inductor (pi filter).
Enabling Output Voltage
The following options are available to enable and disable this device:
1.
Output voltage is enabled through the CTRL pin.
2.
Output voltage is enabled using the PMBus command OPERATION.
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MDC_OKDx-T/90-W12-xxx-C.A02 Page 17 of 71
OKDx-T/90-W12-xxx-C
90A Digital PoL DC-DC Converter Series
The CTRL pin can be used with active high (positive) logic or active low
(negative) logic.
The CTRL pin polarity can be reconfigured using the PMBus command
ON_OFF_CONFIG.
The CTRL pin has an internal 10 kΩ pull-up resistor to 5 V. The external device
must have a sufficient sink current ability to be able pull CTRL pin voltage
down below logic low threshold
level (see Electrical Characteristics). When the CTRL pin is left open, the
voltage on the CTRL pin is pulled up to 5 V.
If the device is to be synchronized to an external clock source, the clock
frequency must be stable prior to enabling the output voltage.
Output Voltage Adjust using Pin-strap Resistor
Using an external Pin-strap resistor, RSET, the output voltage can be set to
several predefined levels shown in the table below. Only the voltage levels
specified in the table can be set by RSET. The resistor should be applied
between the VSET pin and the PREF pin as shown in the Typical Application
Circuit. Maximum 1% tolerance resistors are required.
RSET [kΩ]
VOUT [V]
RSET [kΩ]
VOUT [V]
0 (short)
1.00
26.1
1.10
10
0.60
28.7
1.15
11
0.65
31.6
1.20
12.1
0.70
34.8
1.25
13.3
0.75
38.3
1.30
14.7
0.80
42.2
1.40
16.2
0.85
46.4
1.50
17.8
0.90
51.1
1.60
19.6
0.95
56.2
1.70
21.5
1.00
61.9
1.80
23.7
1.05
Infinite (open)
1.20
operating range. This functionality can also be used to test of supply voltage
supervisors. Margin limits of the nominal output voltage ±5% are default, but
the margin limits can be reconfigured using the PMBus commands
VOUT_MARGIN_LOW and VOUT_MARGIN_HIGH. Margining is activated by the
command OPERATION and can be used regardless of the output voltage being
enabled by the CTRL pin or by the PMBus.
Output Voltage Trim
The actual output voltage can be trimmed to optimize performance of a
specific load by setting a non-zero value for PMBus command VOUT_TRIM.
The value of VOUT_TRIM is summed with the nominal output voltage set by
VOUT_COMMAND, allowing for multiple products to be commanded to a
common nominal value, but with slight adjustments per load.
Output Voltage Range Limitation
The output voltage range that is possible to set by configuration or by the
PMBus interface is hardware limited by the pin-strap resistor RSET. The
maximum output voltage is set to 115% of the output value defined by RSET.
This protects the application circuit from an over voltage due to an accidental
PMBus command.
The limitation applies to the actual regulated output voltage rather than to the
configured value. Thus, it is possible to write and read back a
VOUT_COMMAND value higher than the limit, but the actual output voltage will
be limited.
The output voltage limit can be reconfigured to a lower than 115% of Vout
value by writing the PMBus command VOUT_MAX.
Output Over Voltage Protection (OVP)
The product includes over voltage limiting circuitry for protection of the load.
The default OVP limit is 15% above the nominal output voltage. The product
can be configured to respond in different ways to the output voltage exceeding
the OVP limit:
1.
Immediate and definite shutdown of output voltage until the fault is
cleared by PMBus command CLEAR_FAULTS or the output voltage is reenabled.
2.
Immediate shutdown of output voltage followed by continuous restart
attempts of the output voltage with a preset interval (“hiccup” mode).
The default response is option 2. The OVP limit and fault response can be
reconfigured using the PMBus commands VOUT_OV_FAULT_LIMIT,
VOUT_OV_FAULT_RESPONSE and OVUV_CONFIG.
RSET also sets the maximum output voltage; see section Output Voltage Range
Limitation. The resistor is sensed only during the initialization procedure after
application of input voltage. Changing the resistor value during normal
operation will not change the output voltage. See Ordering Information for
output voltage range.
Output Voltage Adjust using PMBus
The output voltage set by pin-strap can be overridden up to a certain level (see
section Output Voltage Range Limitation) by using the PMBus command
VOUT_COMMAND. See Electrical Specification for adjustment range.
Voltage Margining Up/Down
Using the PMBus interface it is possible to adjust the output voltage to one of
two predefined levels above or below the nominal voltage setting in order to
determine whether the load device is capable of operating outside its specified
supply voltage range. This provides a convenient method for dynamically
testing the operation of the load circuit outside its typical
For products configured to operate in current sharing mode, response option 1
will always be used, regardless of this command configuration.
Output Under Voltage Protection (UVP)
The product includes output under voltage limiting circuitry for protection of
the load. The default UVP limit is 15% below the nominal output voltage. Refer
to section Output Over Voltage Protection for response configuration options
and default setting.
The UVP limit and fault response can be reconfigured using the PMBus
commands VOUT_UV_FAULT_LIMIT and VOUT_UV_FAULT_RESPONSE.
Power Good
The power good pin (PG) indicates when the product is ready to provide
regulated output voltage to the load. During ramp-up and during a fault
condition, PG is held low. By default, PG is asserted high after the output has
ramped to a voltage above 90% of the nominal voltage, and deasserted if the
output voltage falls below 85% of the nominal voltage. These
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MDC_OKDx-T/90-W12-xxx-C.A02 Page 18 of 71
OKDx-T/90-W12-xxx-C
90A Digital PoL DC-DC Converter Series
thresholds may be changed using the PMBus commands POWER_GOOD_ON
and VOUT_UV_FAULT_LIMIT.
The time between when the POWER_GOOD_ON threshold is reached and when
the PG pin is actually asserted is set by the PMBus command
POWER_GOOD_DELAY. See Electrical Specification for default value and
range.
By default the PG pin is configured as an open drain output but it is also
possible to set the output in push-pull mode by the command USER_CONFIG.
The PG output is not defined during ramp up of the input voltage due to the
initialization of the product.
Over Current Protection (OCP)
The product includes robust current limiting circuitry for protection at
continuous overload. After ramp-up is complete the product can detect an
output overload/short condition. The following OCP response options are
available:
1.
Immediate and definite shutdown of output voltage until the fault is
cleared by PMBus command CLEAR_FAULTS or the output voltage is reenabled.
2.
Immediate shutdown of output voltage followed by continuous restart
attempts of the output voltage with a preset interval (“hiccup” mode).
Eliminating the slow beat frequencies (usually
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