MU9C3640L-90TZC

Data Sheet LIST-XL Family APPLICATION BENEFITS • • • • • • LAN Address processing • Cache tag buffers Hash collision resolution Branch tables Data decoders • Other processes or algorithms that require table searches • • • • • • • DISTINCTIVE CHARACTERISTICS • 256 word and 512 word by 64-bit content addressable memory (CAM) Compare any data with all the entries stored in the memory array in a single 70 ns cycle Add or delete data in the CAM in a single cycle Match and Multiple match signals Immediate access to associated data translations, attributes or pointers Flexible patented CAM/RAM partitioning Two selectable mask registers with bit by bit capability Powerful and flexible instruction set Proximate match capability 16-bit I/O; 32Pin LQFP; 3.3 volt operation (Also available in lead-free package) DATA (16) I/O BUFFERS MUX DATA (64) VCC GND DQ (15—0) (16) DATA (16) DEMUX DATA (64) COMMANDS & STATUS (16) SOURCE AND DESTINATION SEGMENT COUNTERS ADDRESS DECODER COMPARAND MASK 1 MASK 2 2N X 2 VALIDITY BITS PRIORITY ENCODER /MA /MM /MF /E /W CONTROL /CM /RESET INSTRUCTION (W/O) ADDRESS NEXT FREE ADDRESS (R/O) CONTROL SEGMENT CONTROL STATUS (15-0) (R/O) STATUS (31-16) (R/O) REGISTER SET MATCH ADDR, /MF /MM, /FF N CAM ARRAY 2N WORDS X 64 BITS N+1 2 Block Diagram MUSIC Semiconductors, the MUSIC logo, and the phrase "MUSIC Semiconductors" are Registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of MUSIC Semiconductors. May 3, 2005 Rev. 3.1 LIST-XL Family General Description GENERAL DESCRIPTION The MUSIC LIST-XL family consists of 256 word and 512 word by 64-bit content-addressable memory (CAM), ideal for time critical applications requiring intensive list processing where space and cost are important. Content-addressable memories, also known as associative memories, operate in the converse way to random access memories (RAM). In a RAM, the input to the device is an address and the output is the data stored at that address. In a CAM, the input is a data sample and the output is a flag to indicate a match and the address of the matching data. As a result, a CAM searches large databases for matching data in a short, constant time period, no matter how many entries are in the database. The ability to search data words up to 64 bits wide allows large address spaces to be searched rapidly and efficiently. A patented architecture links each CAM entry to associated data and makes this data available for use after a successful compare operation. The MUSIC LIST-XL is an inexpensive powerful solution for any application having to retrieve or translate data in a fast, time deterministic manner. It is well suited to handle and speed up functions usually done in software, such as data caches, branch tables, LAN address processing, data translations, high speed data filters, and algorithms having to search, recognize, and make decisions on data or a data subset. OPERATIONAL OVERVIEW To use the LIST-XL, the user loads the data into the Comparand register, which is automatically compared to all valid CAM locations. The device then indicates whether or not one or more of the valid CAM locations contains data that matches the target data. Two validity bits at each memory location determines the status of each CAM location. The two bits are encoded to render four validity conditions: Valid, Skip, Empty, and Random Access, as shown in Table 1. The memory can be partitioned into CAM and associated RAM segments on 16-bit boundaries, but by using one of the two available mask registers, the CAM/RAM partitioning can be set at any arbitrary size between zero and 64 bits. The LIST-XL's internal data path is 64 bits wide for rapid internal comparison and data movement. Loading data to the Control, Comparand, and Mask registers automatically triggers a compare. Compares may also be initiated by a command to the device. Associated RAM data is available immediately after a successful compare operation. The Status register reports the results of compares including all flags and addresses. Two Mask registers are available and can be used in two different ways, to mask comparisons or to mask data writes. The random access validity type (see Table 1) allows additional masks to be stored in the CAM array where they may be retrieved rapidly. A simple three-wire control interface and commands loaded into the Instruction decoder control the device. A powerful instruction set increases the control flexibility and minimizes software overhead. These and other features make the LIST-XL a powerful associative memory that drastically reduces search delays. Skip Bit 0 0 1 1 Empty Bit 0 0 0 1 Validity Type Valid /FF GND /CM VCC DQ0 DQ1 DQ2 DQ3 Empty Skip RAM DQ4 DQ5 VCC GND GND DQ6 DQ7 NC 1 2 3 4 5 6 7 8 25 26 27 28 29 30 31 32 24 23 22 /MM /MF VCC GND /RESET VCC /E /W Table 1: Validity Bits vs Validity Types 32-pin LQFP (top view) /CW LOW LOW HIGH HIGH /CM LOW HIGH LOW HIGH Cycle Type Command Write Cycle Data Write Cycle Command Read Cycle Data Read Cycle 21 20 19 18 17 16 15 14 13 12 11 10 9 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ15 DQ14 Table 2: I/O Cycles 2 Rev. 3.1 Pin Descriptions LIST-XL Family PIN DESCRIPTIONS All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW. Inputs should never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of good layout and bypassing techniques. Refer to the Electrical Characteristics section for more information. /E (Chip Enable, Input, TTL) The /E input enables the device while LOW. The falling edge registers the control signals /W and /CM. The rising edge turns off the DQ pins and clocks the Destination and Source Segment counters. The four cycle types enabled by /E are shown in Table 2 on page 2. /W (Write Enable, Input, TTL) The /W input selects the direction of data flow during a device cycle. /W LOW selects a Write cycle and /W HIGH selects a Read cycle. /CM (DATA/Command Select, Input, TTL) The /CM input selects whether the input signals on DQ15-0 are data or commands. /CM LOW selects Command cycles and /CM HIGH selects Data cycles. /DQ15-0 (Data Bus, I/O, TTL) The DQ15-0 lines convey data, commands, and status to and from the LIST-XL. /W and /CM controls the direction and nature of the information that flows to or from the device.When /E is HIGH, DQ15-0 go to Hi-Z. /MF (Match Flag, Output, TTL) The /MF output goes LOW when one or more valid matches occur during the current or most recent compare cycle. /MF is HIGH if there is no match. /MF will be reset when the active configuration register set is changed. /MM (Device Multiple Match Flag, Output, TTL) The /MM output is LOW when more than one valid match occurs during the current or the most recent compare cycle. /MM will be reset when the active register set is changed. /FF (Full Flag, Output, TTL) The /FF output goes LOW when no empty memory locations exist within the device. /RESET (Reset, Input, TTL) /RESET must be driven LOW to place the device in aknown state before operation, which will reset the device to the conditions shown in Table 4 on page 8. The /RESET pin should be driven by TTL levels, not directly by an RC time-out. /E must be kept HIGH during /RESET. VCC, GND (positive Power Supply, Ground) These pins are the power supply connections to the LIST XL. VCC must meet the voltage supply requirements in the Operating Conditions section relative to the GND pins, which are at 0 Volts (system reference potential), for correct operation of the device. All the ground and power pins must be connected to their respective planes with adequate bulk and high frequency bypassing capacitors in close proximity to the device. Rev. 3.1 3 LIST-XL Family Functional Description FUNCTIONAL DESCRIPTION The LIST-XL is a content-addressable memory (CAM) with 16-bit I/O for network address filtering and translation, virtual memory, data compression, caching, and table lookup applications. The memory consists of static CAM, organized in 64-bit data fields. Each data field can be partitioned into a CAM and a RAM subfield on 16-bit boundaries. The contents of the memory can be randomly accessed or associatively accessed by the use of a compare. During automatic comparison cycles, data in the Comparand register is automatically compared with the "Valid" entries in the memory array. The Device ID can be read using a TCO PS instruction (see Table 11 on page 16). Data Input and Output Characteristics The data inputs and outputs of the LIST-XL are multiplexed for data and instructions over a 16-bit I/O bus. Internally, data is handled on a 64-bit basis, since the Comparand register, the mask registers, and each memory entry are 64 bits wide. Memory entries are globally configurable into CAM and RAM segments on 16-bit boundaries, as described in US Patent 5,383,146 assigned to MUSIC Semiconductors. Seven different CAM/RAM splits are possible, with the CAM width going from one to four segments, and the remaining RAM width going from three to zero segments. Finer resolution on compare width is possible by invoking a mask register during a compare, which does global masking on a bit basis. The CAM subfield contains the associative data, which enters into compares, while the RAM subfield contains the associated data, which is not compared. In LAN bridges, the RAM subfield could hold, for example, port-address and aging information related to the destination or source address information held in the CAM subfield of a given location. In a translation application, the CAM field could hold the dictionary entries, while the RAM field holds the translations, with almost instantaneous response. Validity Bits Each entry has two validity bits (known as Skip bit and Empty bit) associated with it to define its particular type: empty, valid, skip, or RAM. When data is written to the active Comparand register, and the active Segment Control register reaches its terminal count, the contents of the Comparand register are automatically compared with the CAM portion of all the valid entries in the memory array. For added versatility, the Comparand register can be barrel-shifted right or left one bit at a time. A Compare instruction can then be used to force another compare between the Comparand register and the CAM portion of memory entries of any one of the four validity types. After a Read or Move from Memory operation, the validity bits of the location read or moved will be copied into the Status register, where they can be read from the Status register using Command Read cycles. 4 Data Movement (Read/Write) Data can be moved from one of the data registers (CR, MR1, or MR2) to a memory location that is based on the results of the last comparison (Highest-Priority Match or Next Free), or to an absolute address, or to the location pointed to by the active Address register. Data also can be written directly to the memory from the DQ bus using any of the above addressing modes. The Address register may be directly loaded and may be set to increment or decrement, allowing DMA-type reading or writing from memory. Configuration Register Sets Two sets of configuration registers (Control, Segment Control, Address, Mask Register 1, and Persistent Source and Destination) are provided to permit rapid context switching between foreground and background activities. Writes, reads, moves, and compares are controlled by the currently active set of configuration registers. The foreground set would typically be pre-loaded with values useful for comparing input data, often called filtering, while the background set would be pre-loaded with values useful for housekeeping activities such as purging old entries. Moving from the foreground task of filtering to the background task of purging can be done by issuing a single instruction to change the current set of configuration registers. The match condition of the device is reset whenever the active register set is changed. Control Register The active Control register determines the operating conditions within the device. Conditions set by this register's contents are reset, CAM/RAM partitioning, disable or select masking conditions, and disable or select auto-incrementing or -decrementing the Address register. The active Segment Control register contains separate counters to control the writing of 16-bit data segments to the selected persistent destination, and to control the reading of 16-bit data segments from the selected persistent source. Rev. 3.1 Operational Characteristics LIST-XL Family Mask Registers There are two active mask registers at any one time, which can be selected to mask comparisons or data writes. Mask Register 1 has both a foreground and background mode to support rapid context switching. Mask Register 2 does not have this mode, but can be shifted left or right one bit at a time. For masking comparisons, data stored in the active selected mask register determines which bits of the comparand are compared against the valid contents of the memory. If a bit is set HIGH in the mask register, the same bit position in the Comparand register becomes a "don't care" for the purpose of the comparison with all the memory locations. During a Data Write cycle or a MOV instruction, data in the specified active mask register can also determine which bits in the destination will be updated. If a bit is HIGH in the mask register, the corresponding bit of the destination is unchanged. Highest Priority/Multiple Match The match line associated with each memory address is fed into a priority encoder where multiple responses are resolved, and the address of the highest-priority responder (the lowest numerical match address) is generated. In LAN applications, a multiple response might indicate an error. In other applications the existence of multiple responders may be valid. Input Control Signals and Commands Three input control signals and commands loaded into an instruction decoder control the LIST-XL. Two of the three input control signals determine the cycle type. The control signals tell the device whether the data on the I/O bus represents data or a command, and is input or output. Commands are decoded by instruction logic and control moves, forced compares, validity bit manipulations, and the data path within the device. Registers (Control, Segment Control, Address, Next Free Address, etc.) are accessed using Temporary Command Override instructions. The data path from the DQ bus to/from data resources (comparand, masks, and memory) within the device are set until changed by Select Persistent Source and Destination instructions. After a Compare cycle (caused by either a data write to the Comparand or mask registers, a write to the Control register, or a forced compare), the Status register contains the address of the Highest-Priority Matching location, along with flags indicating match, multiple match, and full. The /MF, /MM, and /FF flags also are available directly on output pins. OPERATIONAL CHARACTERISTICS Note: Throughout the following, “aaaH” represents a three-digit hexadecimal number “aaa,” while “bbB” represents a two-digit binary number “bb.” All memory locations are written to or read from in 16-bit segments. Segment 0 corresponds to the lowest order bits (bits 15–0) and Segment 3 corresponds to the highest order bits (bits 63–48). Control Bus Refer to the Block Diagram on page 1 for the following discussion. The inputs Chip Enable (/E), Write Enable (/W), and Command Enable (/CM) are the primary control mechanism for the LIST-XL. Instructions are the secondary control mechanism. Logical combinations of the Control Bus inputs, coupled with the execution of Select Persistent Source (SPS), Select Persistent Destination (SPD), and Temporary Command Override (TCO) instructions allow the I/O operations to and from the DQ15-0 lines to the internal resources, as shown in Table 3 on page 7. The Comparand register is the default source and destination for Data Read and Write cycles. This default state can be overridden independently by executing a Select Persistent Source or Select Persistent Destination instruction, selecting a different source or destination for data. Subsequent Data Read or Data Write cycles will access that source or destination until another SPS or SPD instruction is executed. The currently selected persistent source or destination can be read back through a TCO PS or PD instruction. The sources and destinations available for persistent access are those Rev. 3.1 resources on the 64-bit bus: Comparand register, Mask Register 1, Mask Register 2, and the Memory array. The default destination for Command Write cycles is the Instruction decoder, while the default source for Command Read cycles is the Status register. Temporary Command Override (TCO) instructions provide access to the Control register, the Segment Control register, the Address register, and the Next Free Address register. TCO instructions are active only for one Command Read or Write cycle after being loaded into the Instruction decoder. The data and control interfaces to the LIST-XL are synchronous. During a Write cycle, the Control and Data inputs are registered by the falling edge of /E. When writing to the persistently selected data destination, the Destination Segment counter is clocked by the rising edge of /E. During a Read cycle, the Control inputs are registered by the falling edge of /E, and the Data outputs are enabled while /E is LOW. When reading from the persistently selected data source, the Source Segment counter is clocked by the rising edge of /E. 5 LIST-XL Family Operational Characteristics The Register Set The Control, Segment Control, Address, Mask Register 1, and the Persistent Source and Destination registers are duplicated, with one set termed the Foreground set, and the other the Background set. The active set is chosen by issuing Select Foreground Registers or Select Background Registers instructions. By default, the Foreground set is active after a reset. Having two alternate sets of registers that determine the device configuration allows for a rapid return to a foreground network filtering task from a background housekeeping task. Writing a value to the Control register or writing data to the last segment of the Comparand or either mask register will cause an automatic comparison to occur between the contents of the Comparand register and the words in the CAM segments of the memory marked valid, masked by MR1 or MR2 if selected in the Control register. Instruction Decoder The Instruction decoder is the write-only decode logic for instructions and is the default destination for Command Write cycles. If an instruction's Address Field flag (bit 11) is set to a 1, it is a two-cycle instruction that is not executed immediately. For the next cycle only, the data from a Command Write cycle is loaded into the Address register and the instruction then completes at that address. The Address register will then increment, decrement, or stay at the same value depending on the setting of Control Register bits CT3 and CT2. If the Address Field flag is not set, the memory access occurs at the address currently contained in the Address register. Control Register (CT) The Control register is composed of a number of switches that configure the LIST-XL, as shown in Table 7 on page 15. It is written or read using a TCO CT instruction. If bit 15 of the value written during a TCO CT is a 0, the device is reset (and all other bits are ignored). See Table 4 for the Reset states. Bit 15 always reads back as a 0. A write to the Control register causes an automatic compare to occur (except in the case of a reset). Either the Foreground or Background Control register will be active, depending on which register set has been selected, and only the active Control register will be written to or read from. Control Register bits 8-6 control the CAM/RAM partitioning. The CAM portion of each word may be sized from a full 64 bits down to 16 bits in 16-bit increments. The RAM portion can be at either end of the 64-bit word. Compare masks may be selected by bits 5 and 4. Mask Register 1, Mask Register 2, or neither may be selected to mask compare operations. The address register behavior is controlled by bits 3 and 2, and may be set to increment, decrement, or neither after a memory access. 6 Segment Control Register (SC) The Segment Control register, as shown in Table 8 on page 16, is accessed using a TCO SC instruction. On read cycles, D15, D10, D5, and D2 will always read back as 0s. Either the Foreground or Background Segment Control register will be active, depending on which register set has been selected, and only the active Segment Control register will be written to or read from. The Segment Control register contains dual independent incrementing counters with limits, one for data reads and one for data writes. These counters control which 16-bit segment of the 64-bit internal resource is accessed during a particular data cycle on the 16-bit data bus. The actual destination for data writes and source for data reads (called the persistent destination and source) are set independently with SPD and SPS instructions, respectively. Each of the two counters consists of a start limit, an end limit, and the current count value which points to the segment to be accessed on the next data cycle. The current count value can be set to any segment, even if it is outside the range set by the start and end limits. The counters count up from the current count value to the end limit and then jump back to the start limit. If the current count is greater than the end limit, the current count value will increment to 3, then roll over to 0 and continue incrementing until the end limit is reached; it then jumps back to the start limit. If a sequence of data writes or reads is interrupted, the Segment Control register can be reset to its initial start limit values by using an RSC instruction. After the LIST-XL is reset, both Source and Destination counters are set to count from Segment 0 to Segment 3 with an initial value of 0. Address Register (AR) The Address register points to the CAM memory location to be operated upon when M@[AR] or M@aaaH is part of the instruction. It can be loaded directly by using a TCO AR instruction or indirectly by using an instruction requiring an absolute address, such as MOVaaaH, CR,V.After being loaded, the Address register value will then be used for the next memory access referencing the Address register. A reset sets the Address register to zero. Rev. 3.1 Operational Characteristics LIST-XL Family Cycle Type Cmd Write /E L /CM L /W L I/O Status IN IN IN IN OUT OUT OUT OUT OUT OUT OUT IN IN IN IN IN IN OUT OUT OUT OUT OUT HIGH-Z SPS SPD TCO 3 3 3 3 3 Operation Load Instruction decoder Load Address register Load Control register Load Segment Control register Read Next Free Address register Read Address register Read Status Register bits 15–0 Read Status Register bits 31–16 Read Control register Read Segment Control register Read Current Persistent Source or Destination Load Comparand register Load Mask Register 1 Load Mask Register 2 Write Memory Array at address Write Memory Array at Next Free address Write Memory Array at Highest-Priority match Read Comparand register Read Mask Register 1 Read Mask Register 2 Read Memory Array at address Read Memory Array at Highest-Priority match Deselected Notes 1 2,3 3 3 3 3 4 5 3 3 3,10 6,9 7,9 7,9 7,9 7,9 7,9 6, 9 8, 9 8, 9 8, 9 7, 8 Cmd Read L L H 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Data Write L H L Data Read L H H H X X Table 3: Input/Output Operations Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Default Command Write cycle destination (does not require a TCO instruction). Default Command Write cycle destination (no TCO instruction required) if Address Field flag was set in bit 11 of the instruction loaded in the previous cycle. Loaded or read on the Command Write or Read cycle immediately following a TCO instruction. Active for one Command Write or Read cycle only. NFA register can not be loaded this way. Default Command Read cycle source (does not require a TCO instruction). Default Command Read cycle source (does not require a TCO instruction) if the previous cycle was a Command Read of Status Register Bits 15–0. If next cycle is not a Command Read cycle, any subsequent Command Read cycle accesses the Status Register Bits 15–0. Default persistent source and destination on power-up and after Reset. If other resources were sources or destinations, SPD CR or SPS CR restores the Comparand register as the destination or source. Selected by executing a Select Persistent Destination instruction. Selected by executing a Select Persistent Source instruction. Access may require multiple 16-bit Read or Write cycles. The Segment Control register controls the selection of the desired 16-bit segment(s) by establishing the Segment counters’ start and end limits and count values. A Command Read cycle after a TCO PS or TCO PD reads back the Instruction decoder bits that were last set to select a persistent source or destination. The TCO PS instruction also reads back the Device ID. Control Register Bits CT3 and CT2 set the Address register to automatically increment or decrement (or not change) during sequences of Command or Data cycles. The Address register will change after executing an instruction that includes M@[AR] or M@aaaH, or after a data access to the end limit segment (as set in the Segment Control register) when the persistent source or destination is M@[AR] or M@aaaH. Either the Foreground or Background Address register will be active, depending on which register set has been selected, Rev. 3.1 and only the active Address register will be written to or read from. Next Free Address Register (NF) The LIST-XL automatically stores the address of the first empty memory location in the Next Free Address register, which is then used as a memory address pointer for M@NF operations. The Next Free Address register, shown in Table 9 on page 16, can be read using a TCO NF instruction. After a reset, the Next Free Address register is set to zero. 7 LIST-XL Family Operational Characteristics CAM Status Validity bits at all memory locations CAM/RAM Partitioning Comparison Masking Address register auto-increment or auto-decrement Source and Destination Segment counters count ranges Address register and Next Free Address register Page Address and Device Select registers Control register after reset (including CT15) Persistent Destination for Command writes Persistent Source for Command reads Persistent Source and Destination for Data reads and writes Configuration Register set /RESET Condition Skip = 0, Empty = 1 (empty) 64 bits CAM, 0 bits RAM Disabled Disabled 00B to 11B; loaded with 00B Contain all 0s Contain all 0s (no change on software reset) Contains 0008H Instruction decoder Status register Comparand register Foreground Table 4: Device Control State After Reset Status Register The 32-bit Status register, as shown in Table 10 on page 16, is the default source for Command Read cycles. Bit 31 is the internal Full flag, which will go LOW if there are no empty memory locations. Bit 30 is the internal Multiple Match flag, which will go LOW if a Multiple match was detected. Bits 29 and 28 are the Skip and Empty Validity bits, which reflect the validity of the last memory location read. After a reset, the Skip and Empty bits will read 11 until a read or move from memory has occurred. The rest of the Status register down to bit 1 contains the address of the Highest-Priority match. After a reset or a no-match condition, the match address bits will be all 1s. Bit 0 is the internal Match flag, which will go LOW if a match was found. Comparand Register (CR) The 64-bit Comparand register is the default destination for data writes and reads, using the Segment Control register to select which 16-bit segment of the Comparand register is to be loaded or read out. The persistent source and destination for data writes and reads can be changed to the mask registers or memory by SPS and SPD instructions. During an automatic or forced compare, the Comparand register is simultaneously compared against the CAM portion of all memory locations with the correct validity condition. Automatic compares always compare against valid memory locations, while forced compares, using CMP instructions, can compare against memory locations tagged with any specific validity condition. The Comparand register may be shifted one bit at a time to the right or left by issuing a Shift Right or Shift Left instruction, with the right and left limits for the wrap-around determined by the CAM/RAM partitioning set in the Control register. During shift rights, bits shifted off the LSB of the CAM partition will reappear at the MSB of the CAM partition. Likewise, bits shifted off the MSB of the CAM partition will reappear at the LSB during shift lefts. Mask Registers (MR1, MR2) The Mask registers can be used in two different ways, either to mask compares or to mask data writes and moves. Either mask register can be selected in the Control register to mask every compare, or selected by instructions to participate in data writes or moves to and from Memory. If a bit in the selected mask register is set to a 0, the corresponding bit in the Comparand register will enter into a masked compare operation. If a Mask bit is a 1, the corresponding bit in the Comparand register will not enter into a masked compare operation. Bits set to 0 in the mask register cause corresponding bits in the destination register or memory location to be updated when masking data writes or moves, while a bit set to 1 will prevent that bit in the destination from being changed. Either the Foreground or Background MR1 can be set active, but after a reset, the Foreground MR1 is active by default. MR2 incorporates a sliding mask, where the data can be replicated one bit at a time to the right or left with no wrap-around by issuing a Shift Right or Shift Left instruction. The right and left limits are determined by the CAM/RAM partitioning set in the Control register. For a Shift Right the upper limit bit is replicated to the next lower bit, while for a Shift Left the lower limit bit is replicated to the next higher bit. 8 Rev. 3.1 Operational Characteristics LIST-XL Family The Memory Array Memory Organization The Memory array is organized into 64-bit words with each word having an additional two validity bits (Skip and Empty). By default, all words are configured to be 64 CAM cells. However, bits 8-6 of the Control register can divide each word into a CAM field and a RAM field. The RAM field can be assigned to the least-significant or most-significant portion of each entry. The CAM/RAM partitioning is allowed on 16-bit boundaries, permitting selection of the configuration shown in Table 7 on page 15, bits 8-6 (e.g., "001" sets the 48 MSBs to CAM and the 16 LSBs to RAM). Memory Array bits designated as RAM can be used to store and retrieve data associated with the CAM content at the same memory location. Memory Access There are two general ways to get data into and out of the memory array: directly or by moving the data through the Comparand or mask registers. The first way, through direct reads or writes, is set up by issuing a Set Persistent Destination (SPD) or Set Persistent Source (SPS) command. The addresses for the direct access can be directly supplied; supplied from the Address register, supplied from the Next Free Address register, or supplied as the Highest-Priority Match address.Additionally, all the direct writes can be masked by either mask register. The second way is to move data via the Comparand or mask registers. This is accomplished by issuing Data Move commands (MOV). Moves using the Comparand register can also be masked by either of the mask registers. I/O Cycles The LIST-XL supports four basic I/O cycles: Data Read, Data Write, Command Read, and CommandWrite.The type of cycle is determined by the states of the /W and /CM control inputs. These signals are registered at the beginning of a cycle by the falling edge of /E. Table 2 on page 2 shows how the /W and /CM lines select the cycle type. During Read cycles, the DQ15-0 outputs are enabled after /E goes LOW. During Write cycles, the data or command to be written is captured from DQ15-0 at the beginning of the cycle by the falling edge of /E. Figures 1 and 2 on page 10 show Read and Write cycles respectively. Figure 3 on page 10 shows typical cycle-to-cycle timing with the Match flag valid at the end of the Comparand Write cycle. Data writes and reads to the comparand, mask registers, or memory occur in one to four 16-bit cycles, depending on the settings in the Segment Control register. The Compare operation automatically occurs during Data writes to the Comparand or mask registers when the destination segment counter reaches the end count set in the Segment Control register. If there was a match, the second cycle reads status or associated data, depending on the state of /CM. The minimum timings for the /E control signal are given in the Switching Characteristics section on page 18. Note that at minimum timings the /E signal is non-symmetrical, and that different cycle types have different timing requirements, as given in Table 6 on page 15. Compare Operations During a Compare operation, the data in the Comparand register is compared to all locations in the Memory array simultaneously. Any mask register used during compares must be selected beforehand in the Control register. There are two ways compares are initiated: Automatic and Forced compares. Automatic compares perform acompare of the contents of the Comparand register against Memory locations that are tagged as "Valid," and occur whenever the following happens: • The Destination Segment counter in the Segment Control register reaches its end limit during writes to the Comparand or mask registers. After a command write of a TCO CT is executed (except for a software reset), so that a compare is executed with the new settings of the Control register. • Forced compares are initiated by CMP instructions using one of the four validity conditions, V, R, S, and E. The forced compare against "Empty" locations automatically masks all 64 bits of data to find all locations with the validity bits set to "Empty," while the other forced compares are masked only as selected in the Control register. INITIALIZING THE LIST-XL Initialization of the LIST-XL is required to configure the various registers on the device. Since a Control register reset establishes the operating conditions shown in Table 4 on page 8, restoration of operating conditions better suited for the application may be required after a reset, whether using the Control Register reset or the /RESET pin. When the device powers up, the memory and registers are in an unknown state, so the /RESET pin must be asserted to place the device in a known state. Rev. 3.1 9 LIST-XL Family Operational Characteristics /E /W /CM DQ15-0 DATA OUT Figure 1: Read Cycle /E /W /CM DQ15–0 Figure 2: Write Cycle COMPARAND WRITE C YC L E /E STATUS READ C YC L E ASSOCIATED DATA READ CYCLE /CM /W DQ15–0 /MF, /MM DATA DATA DATA /MF AND /MM FLAGS UPDATED Figure 3: Cycle-to-Cycle Timing Example Cycle Type Op-Code on DQ Bus Control Bus /E L L L L L L L L /CM L L L L L L L L /W H L L L L L L L Clear power-up anomalies Target Control register for reset. Causes Reset. Target Control register for initial values. Control register value. Target Segment Count Control register Set both Segment counters to write to Segment 1, 2, and 3, and read from Segment 0. Set Data reads from Segment 0 of the Highest-Priority match Comments Notes Command read Command write Command write Command write Command write Command write Command write Command write TCO CT 0000H TCO CT 8040H TCO SC 3808H SPS M@HM 1 2 Table 5: Initialization Routine Example Notes: 1. 2. A software reset using a TCO CT followed by 0000H puts the device in a known state. Good programming practice dictates a software reset for initialization to account for all possible conditions. A typical LIST-XL control environment: 48 CAM bits, 16 RAM bits; Disable comparison masking; and Enable address increment. See Table 7 for Control Register bit assignments. 10 Rev. 3.1 Instruction Set Descriptions LIST-XL Family INSTRUCTION SET DESCRIPTIONS Instruction: Select Persistent Source (SPS) Binary Op-Code: 0000 f000 0000 0sss f Address Field flag sss Selected source This instruction selects a persistent source for data reads, until another SPS instruction changes it or a reset occurs. The default source after reset for Data Read cycles is the Comparand register. Setting the persistent source to M@aaaH loads the Address register with "aaaH" and the first access to that persistent source will be at aaaH, after which the AR value increments or decrements as set in the Control register.The SPS M@[AR]instruction does the same except the current Address Register value is used. Instruction: Temporary Command Override (TCO) Binary Op-Code: 0000 0010 00dd d000 Register selected as source or destination for only the next Command Read or Write cycle TCO instruction selects a register as the source or destination for only the next Command Read or Write cycle, so a value can be loaded or read out of the register. Subsequent Command Read or Write Cycles revert to reading the Status register and writing to the Instruction decoder.All registers but the NF, PS, and PD can be written to, and all can be read from. The Status register is only available via non-TCO Command Read cycles. Reading the PS register also outputs the Device ID on bits 15-4 as shown in Table 11 on page 16. Instruction: Data Move (MOV) Binary Op-Code: 0000 f011 mmdd dsss or 0000 f011 mmdd dvss Address Field flag Mask Register select Destination of data Source of data Validity setting if destination is a Memory location The MOV instruction performs a 64-bit move of the data in the selected source to the selected destination. If the source or destination is aaaH, the Address register is set to "aaaH." For MOV instructions to or from aaaH or [AR], the Address register will increment or decrement from that value after the move completes, as set in the Control register. Data transfers between the Memory array and the Comparand register may be masked by either Mask Register 1 or Mask Register 2, in which case, only those bits in the destination which correspond to bits in the selected mask register set to 0 will be changed. A Memory location used as a destination for a MOV instruction may be set to Valid or left unchanged. If the source and destination are the same register, no net change occurs (a NOP). f mm ddd sss v ddd Instruction: Select Persistent Destination (SPD) Binary Op-Code: 0000 f001 mmdd dvvv Address Field flag Mask Register select Selected destination Validity setting for Memory Location destinations This instruction selects a persistent destination for data writes, which remains until another SPD instruction changes it or a reset occurs. The default destination for Data Write cycles is the Comparand register after a reset. When the destination is the Comparand register or the memory array, the data written may be masked by either Mask Register 1 or Mask Register 2, so that only destination bits corresponding to bits in the mask register set to 0 will be modified. An automatic compare will occur after writing the last segment of the Comparand or mask registers, but not after writing to memory. Setting the persistent destination to M@aaaH loads the Address register with "aaaH," and the first access to that persistent destination will be at aaaH, after which the AR value increments or decrements as set in the Control register. The SPD M@[AR] instruction does the same except the current Address Register value is used. f mm ddd vvv Rev. 3.1 11 LIST-XL Family Instruction Set Descriptions Instruction: Validity Bit Control (VBC) Binary Op-Code: 0000 f100 00dd dvvv f Address Field flag ddd Destination of data vvv Validity setting for Memory location The VBC instruction sets the Validity bits at the selected memory locations to the selected state. This feature can be used to find all valid entries by using a repetitive sequence of CMP V through a mask of all 1s followed by a VBC HM, S. If the VBC target is aaaH, the Address register is set to "aaaH." For VBC instructions to or from aaaH or [AR], the Address register will increment or decrement from that value after the operation completes, as set in the Control register. Instruction: Special Instructions Binary Op-Code: 0000 0110 00dd drrr ddd Target resource rrr Operation Two alternate sets of configuration registers can be selected by using the Select Foreground and Select Background Registers instructions. These registers are the Control, Segment Control, Address, Mask Register 1, and the PS and PD registers. An RSC instruction resets the Segment Control register count values for both the Destination and Source counters to the original Start limits. The Shift instructions shift the designated register one bit right or left. The right and left limits for shifting are determined by the CAM/RAM partitioning set in the Control register. The Comparand register is a barrel-shifter, and for the example of a device set to 64 bits of CAM executing a Shift Comparand Right instruction, bit 0 is moved to bit 63, bit 1 is moved to bit 0, and bit 63 is moved to bit 62. For a Shift Comparand Left instruction, bit 63 is moved to bit 0, bit 0 is moved to bit 1, and bit 62 is moved to bit 63. MR2 acts as a sliding mask, where for a Shift Right instruction bit 1 is moved to bit 0, while bit 0 "falls off the end," and bit 63 is replicated to bit 62. For a Shift Mask Left instruction, bit 0 is replicated to bit 1, bit 62 is moved to bit 63, and bit 63 "falls off the end." With shorter width CAM fields, the bit limits on the right or left move to match the width of CAM field. Instruction: Compare (CMP) Binary Op-Code: 0000 0101 0000 0vvv vvv Validity condition A CMP V, S, or R instruction forces a Comparison of Valid, Skipped, or Random entries against the Comparand register through a mask register, if one is selected. During a CMP E instruction, the compare is only done on the Validity bits and all data bits are automatically masked. Notes: * Instruction cycle lengths given in Table 6 on page 15. † If f=1, the instruction requires an absolute address to be supplied on the following cycle as Command write. The value supplied on the second cycle will update the address register. After operations involving M@[AR] or M@aaaH, the Address register will be incremented or decremented depending on the setting in the Control register. 12 Rev. 3.1 Instruction Set Summary LIST-XL Family INSTRUCTION SET SUMMARY Mnemonic Format: INS dst, src[msk], val INS: Instruction mnemonic dst: Destination of the data src: Source of the data msk: Mask register used val: Validity condition set at the location written Instruction: Select Persistent Source Operation Comparand Register Mask Register 1 Mask Register 2 Memory Array at Addr. Reg. Memory Array at Address Mem. at Highest-Priority Match Instruction: Select Persistent Destination (continOperation Masked by MR1 Masked by MR2 Mem. at High.-Prio. Match, Random Mnemonic SPD M@HM[MR1],S SPD M@HM[MR2],S SPD M@HM,R SPD M@HM[MR1],R SPD M@HM[MR2],R SPD M@NF,V SPD M@NF[MR1],V SPD M@NF[MR2],V SPD M@NF,E SPD M@NF[MR1],E SPD M@NF[MR2],E SPD M@NF,S SPD M@NF[MR1],S SPD M@NF[MR2],S SPD M@NF[MR1],R SPD M@NF[MR2],R Op-Code 012EH 016EH 01AEH 012FH 016FH 01AFH 0134H 0174H 01B4H 0135H 0175H 01B5H 0136H 0176H 01B6H 0137H 0177H 01B7H Mem. at Highest-Prio. Match, Skip SPD M@HM,S Masked by MR1 Masked by MR2 Mnemonic SPS CR SPS MR1 SPS MR2 SPS M@[AR] SPS M@aaaH SPS M@HM Op-Code 0000H 0001H 0002H 0004H 0804H 0005H Mem. at Next Free Addr., Valid Masked by MR1 Masked by MR2 Mem. at Next Free Addr., Empty MaskedbyMR1 MaskedbyMR2 Mem. at Next Free Addr., Skip Masked by MR1 Masked by MR2 Instruction: Select Persistent Destination Operation Comparand Register Masked by MR1 Masked by MR2 Mask Register 1 Mask Register 2 Mem. at Addr. Reg. set Valid Masked by MR1 Masked by MR2 Mem. at Addr. Reg. set Empty Masked by MR1 Masked by MR2 Mem. at Addr. Reg. set Skip Masked by MR1 Masked by MR2 Mem. at Addr.Reg. set Random Masked by MR1 Masked by MR2 Memory at Address set Valid Masked by MR1 Masked by MR2 Memory at Address set Empty Masked by MR1 Masked by MR2 Memory at Address set Skip Masked by MR1 Masked by MR2 Memory at Address set Random Masked by MR1 Masked by MR2 Masked by MR1 Masked by MR2 Masked by MR1 Masked by MR2 Mem. at Next Free Addr., Random SPD M@NF,R Mnemonic SPD CR SPD CR[MR1] SPD CR[MR2] SPD MR SPD MR2 SPD M@[AR],V SPD M@[AR][MR1],V SPD M@[AR][MR2],V SPD M@[AR],E SPD M@[AR][MR1],E SPD M@[AR][MR2],E SPD M@[AR],S SPD M@[AR][MR1],S SPD M@[AR][MR2],S SPD M@[AR],R SPD M@[AR][MR1],R SPD M@[AR][MR2],R SPD M@aaaH,V SPD M@aaaH[MR1],V SPD M@aaaH[MR2],V SPD M@aaaH,E SPD M@aaaH[MR1],E SPD M@aaaH[MR2],E SPD M@aaaH,S SPD M@aaaH[MR1],S SPD M@aaaH[MR2],S SPD M@aaaH,R SPD M@aaaH[MR1],R SPD M@aaaH[MR2],R SPD M@HM[MR1],V SPD M@HM[MR2],V SPD M@HM[MR1],E SPD M@HM[MR2],E Op-Code 0100H 0140H 0180H 0108H 0110H 0124H 0164H 01A4H 0125H 0165H 01A5H 0126H 0166H 01A6H 0127H 0167H 01A7H 0924H 0964H 09A4H 0925H 0965H 09A5H 0926H 0966H 09A6H 0927H 0967H 09A7H 012CH 016CH 01ACH 012DH 016DH 01ADH Masked by MR1 Masked by MR2 Instruction: Temporary Command Override Operation Control Register Segment Control Register Read Next Free Address Address Register Read Persistent Source Read Persistent Destination Mnemonic TCO CT TCO SC TCO NF TCO AR TCO PS TCO PD Op-Code 0200H 0210H 0218H 0220H 0230H 0238H Instruction: Data Move Operation Comparand Register from: No Operation Mask Register 1 Mask Register 2 Memory at Address Reg. Masked by MR1 Masked by MR2 Memory at Address Masked by MR1 Masked by MR2 Mem. at Highest-Prio. Match MaskedbyMR1 MaskedbyMR2 Mask Register 1 from: Comparand Register No Operation Mask Register 2 Memory at Address Reg. Memory at Address Mem. at Highest-Prio. Match MOV MR1,CR NOP MOV MR1,MR2 MOV MR1,[AR] MOV MR1,aaaH MOV MR1,HM 0308H 0309H 030AH 030CH 0B0CH 030DH NOP MOV CR,MR1 MOV CR,MR2 MOV CR,[AR] MOV CR,[AR][MR1] MOV CR,[AR][MR2] MOV CR,aaaH MOV CR,aaaH[MR1] MOV CR,aaaH[MR2] MOV CR,HM MOV CR,HM[MR1] MOV CR,HM[MR2] 0300H 0301H 0302H 0304H 0344H 0384H 0B04H 0B44H 0B84H 0305H 0345H 0385H Mnemonic Op-Code Mem. at Highest-Prio. Match, Valid SPD M@HM,V Mem. at Highest-Prio. Match, Emp. SPD M@HM,E Rev. 3.1 13 LIST-XL Family Instruction Set Summary Instruction: Data Move (continued) Operation Mask Register 2 from: Comparand Register Mask Register 1 No Operation Memory at Address Reg. Memory at Address Mem. at Highest-Prio. Match Comparand Register Masked by MR1 Masked by MR2 Mask Register 1 Mask Register 2 Comparand Register Masked by MR1 Masked by MR2 Mask Register 1 Mask Register 2 Comparand Register Masked by MR1 Masked by MR2 Mask Register 1 Mask Register 2 Comparand Register Masked by MR1 Masked by MR2 Mask Register 1 Mask Register 2 Comparand Register Masked by MR1 Masked by MR2 Mask Register 1 Mask Register 2 Comparand Register Masked by MR1 Masked by MR2 Mask Register 1 Mask Register 2 Comparand Register Masked by MR1 Masked by MR2 Mask Register 1 Mask Register 2 Comparand Register Masked by MR1 Masked by MR2 Mask Register 1 Mask Register 2 MOV MR2,CR MOV MR2,MR1 NOP MOV MR2,[AR] MOV MR2,aaaH MOV MR2,HM MOV [AR],CR MOV [AR],CR[MR1] MOV [AR],CR[MR2] MOV [AR],MR1 MOV [AR],MR2 MOV [AR],CR,V MOV [AR],CR[MR1],V MOV [AR],CR[MR2],V MOV [AR],MR1,V MOV [AR],MR2,V MOV aaaH0,CR MOV aaaH,CR[MR1] MOV aaaH,CR[MR2] MOV aaaH,MR1 MOV aaaH,MR2 MOV aaaH,CR,V MOV aaaH,CR[MR1],V MOV aaaH,CR[MR2],V MOV aaaH,MR1,V MOV aaaH,MR2,V MOV HM,CR MOV HM,CR[MR1] MOV HM,CR[MR2] MOV HM,MR1 MOV HM,MR2 MOV HM,CR,V MOV HM,CR[MR1],V MOV HM,CR[MR2],V MOV HM,MR1,V MOV HM,MR2,V MOV NF,CR MOV NF,CR[MR1] MOV NF,CR[MR2] MOV NF,MR1 MOV NF,MR2 MOV NF,CR,V MOV NF,CR[MR1],V MOV NF,CR[MR2],V MOV NF,MR1,V MOV NF,MR2,V 0310H 0311H 0312H 0314H 0B14H 0315H 0320H 0360H 03A0H 0321H 0322H 0324H 0364H 03A4H 0325H 0326H 0B20H 0B60H 0BA0H 0B21H 0B22H 0B24H 0B64H 0BA4H 0B25H 0B26H 0328H 0368H 03A8H 0329H 032AH 032CH 036CH 03ACH 032DH 032EH 0330H 0370H 03B0H 0331H 0332H 0334H 0374H 03B4H 0335H 0336H Instruction: Validity Bit Control Op-Code Operation Set Validity bits at Address Register Set Valid Set Empty Set Skip Set Random Access Set Validity bits at Address Set Valid Set Empty Set Skip Set Random Access Set Valid Set Empty Set Skip Set Random Access Set Valid Set Empty Set Skip Set Random Access VBC aaaH,V VBC aaaH,E VBC aaaH,S VBC aaaH,R VBC HM,V VBC HM,E VBC HM,S VBC HM,R VBC ALM,V VBC ALM,E VBC ALM,S VBC ALM,R 0C24H 0C25H 0C26H 0C27H 042CH 042DH 042EH 042FH 043CH 043DH 043EH 043FH VBC [AR],V VBC [AR],E VBC [AR],S VBC [AR],R 0424H 0425H 0426H 0427H Mnemonic Mnemonic Op-Code Memory at Address Register, No Change to Validity bits, from: Set Validity bits at Highest-Priority Match Memory at Address Register, Location set Valid, from: Set Validity bits at All Matching Locations Memory at Address, No Change to Validity bits, from: Instruction: Compare Operation Compare Valid Locations Compare Empty Locations Compare Skipped Locations Mnemonic CMP V CMP E CMP S Op-Code 0504H 0505H 0506H 0507H Memory at Address, Location set Valid, from: Comp. Random Access Locations CMP R Instruction: Special Instructions Operation Shift Comparand Right Shift Comparand Left Shift Mask Register 2 Right Shift Mask Register 2 Left Select Foreground Registers Select Background Registers Reset Seg. Cont. Reg. to Initial Val. Memory at Highest-Priority Match, No Change to Validity bits, from: Mnemonic SFT CR, R SFT CR, L SFT M2, R SFT M2, L SFR SBR RSC Op-Code 0600H 0601H 0610H 0611H 0618H 0619H 061AH Memory at Highest-Priority Match, Location set Valid, from: Memory at Next Free Address, No Change to Validity bits, from: Memory at Next Free Address, Location set Valid, from: 14 Rev. 3.1 Instruction Set Summary LIST-XL Family Instruction Cycle Lengths Cycle Length Cycle Type Command Write MOV reg, reg TCO reg (except CT) TCO CT (non-reset, HMA invalid) SPS, SPD, SFR SBR, RSC, NOP MOV reg, mem TCO CT (reset) VBC (NFA invalid) MOV mem, reg TCO CT (non-reset, HMA valid) CMP Status register or 16-bit register Sheets Command Read Data Write Comparand register (not last segment) Mask register (not last segment) Memory array (NFA invalid) Memory array (NFA valid) Comparand register (last segment) Mask register (last segment) Comparand register Mask register Memory array Data Read Short Medium Long VBC (NFA valid) Table 6: Instruction Cycle Lengths Note: The specific timing requirements for Short, Medium, and Long cycles are given in the Switching Characteristics section under the tELEH parameter. For two cycle Command Writes (TCO reg or any instruction with “aaaH” as the source or destination), the first cycle is short, and the second cycle is the length given. Rev. 3.1 15 LIST-XL Family Register Bit Assignments REGISTER BIT ASSIGNMENTS Device Bit(s) 15 14:9 8:6 Name RST 0 CAM/RAM Part Description 0 = Reset Reserved 000 = 64 CAM/0 RAM 001 = 48 CAM/16 RAM 010 = 32 CAM/32 RAM 011 = 16 CAM/48 RAM 100 = 48 RAM/16 CAM 101 = 32 RAM/32 CAM 110 = 16 RAM/48 CAM 111 = No Change 00 = None 01 = MR1 10 = MR2 11 = No Change 00 = Increment 01 = Decrement 10 = Disable 11 = No Change Reserved All 5:4 Comp. Mask 3:2 AR Inc/Dec 1:0 0 Table 7: Control Register Bits Note: D15 reads back as 0 Device Bit(s) 15 14:13 12:11 10 9:8 7:6 5 4:3 2 1:0 Name SDL DCSL DCEL SSL SCSL SCEL LDC DSCV LSC SSCV Description 0 = Set Destination Segment Limits 1 = No Change 00–11 = Destination Count Start Limit 00–11 = Destination Count End Limit 0 = Set Source Segment Limits 1 = No Change 00–11 = Source Count Start Limit 00–11 = Source Count End Limit 0 = Load Destination Segment Count 1 = No Change 00–11 = Destination Seg. Count Value 0 = Load Source Segment Count 1 = No Change 00–11 = Source Segment Count Value All Table 8: Segment Control Register Bits Note: D15, D10, D5, and D2 are read back as 0s. Device 3640L(F) Bit(s) 15:8 7:0 15:9 8:0 Name Reserved NF7-0 Reserved NF8-0 Description All 0’s Next Free Address All 0’s Next Free Address 5640L(F) Table 9: Next Free Address Bits Note: The Next Free Address register is read only, and is accessed by performing a Command Read cycle immediately following a TCO NF Instruction. 16 Rev. 3.1 Register Bit Assignments LIST-XL Family Device Bit(s) 31 30 Name /FL /MM VB1-0 Description 0 = Internal CAM Full 0 = Internal Multiple Match 00 = Valid 01 = Empty 10 = Skip 11 = RAM Reserved Match Address Reserved Match Address Match Flag All 29:28 3640L(F) 27:9 8:1 27:10 9:1 0 0 AM7–0 0 AM8–0 /MF 5640L(F) All Table 10: Status Register Bits Note: The Status register is read only, and is accessed by performing Command Read cycles. On the first cycle, bits 15–0 are output, and if a second Command Read cycle is issued immediately after the first Command Read cycle, bits 31–16 are output. Device 3640L(F) 5640L(F) All Bit(s) 15:4 15:4 3:0 Name DEVID DEVID PS Description Device ID = 341H Device ID = 541H Persistent Source Setting Table 11: Persistent Source Register Bits Note: The Persistent Source register is read only, and is accessed by performing a Command Read cycle immediately following a TCO PS instruction. Rev. 3.1 17 LIST-XL Family Electrical ELECTRICAL Absolute Maximum Ratings Supply Voltage Voltage on all other pins Temperature under bias Storage Temperature DC Output Current -0.5 to 4.6 Volts -0.5 to VCC +0.5 Volts (-2 Volts for 10 ns, measured at the 50% point) -55° C to 125° C -55° C to 125° C 20 mA (per output, one at a time, one second duration) All voltages referenced to GND. Stresses exceeding those listed under Absolute Maximum Ratings may induce failure. Exposure to absolute maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied. Symbol VCC VIH VIL TA Parameter Operating supply voltage Input voltage logic 1 Input voltage logic 0 Ambient operating temperature Commercial Industrial Min. 3.0 2.0 -0.5 0 -40 Typical 3.3 Max. 3.6 VCC + 0.5 0.8 70 85 Units Volts Volts Volts °C °C Notes 1, 2 Still air Table 12: Operating Conditions (Voltages referenced to GND at the device pin) Notes: 1. 2. 1.0 Volts for a duration of 10 ns measured at the 50% amplitude points for Input-only lines (see Figure 5 on page 19). Common I/O lines are clamped, so that signal transients can not fall below -0.5 Volts . Symbol ICC ICC(SB) VOH VOL IIZ IOZ Parameter Average Power Supply Current Stand-by Power Supply Current Output voltage logic 1 Output voltage logic 0 Others Input leakage current Output leakage current /RESET -2 6 -10 9 2.4 0.4 +2 12 10 Min. Typical 20 Max. 30 2 Units mA mA Volts Volts μA Kohms μA Notes tELEL = tELEL(min);9 /E = HIGH IOH = -2.0 mA IOL = 4.0 mA VSS ≤ VIN ≤ VCC VIN = 0 V VSS ≤ VOUT ≤ VCC DQN = High Impedance Table 13: DC Electrical Characteristics Symbol CIN COUT Parameter Input capacitance Output capacitance Max. 6 7 Units pF pF Notes f = 1 MHz, VIN = 0V f = 1 MHz, VOUT = 0V Table 14: Capacitance Input Signal Transitions Input Signal Rise Time Input Signal Fall Time Input Timing Reference Level 0.0 Volts to 3.0 Volts < 3 ns < 3 ns 1.5 Volts Output Timing Reference Level 1.5 Volts Table 15: AC Test Conditions 18 Rev. 3.1 Switching LIST-XL Family SWITCHING Switching Test Figures Vcc Input Waveform R1 Device Under Test C1 R2 0V V IL ( MIN) 50% Amplitude Point 10ns Figure 4: AC Test Load Parameter VCC R1 R2 Test Load A C1 (includes jig) Test Load B 5 pF All Devices 3.3 635 702 30 Figure 5: Input Signal Waveform. Units Volts Ohms Ohms pF Table 16: Switching Test Figures Component Values Rev. 3.1 19 LIST-XL Family SWITCHING CHARACTERISTICS (see note 3) SWITCHING CHARACTERISTICS (SEE NOTE 3) Cycle Time No. 1 Symbol tELEL Parameter Chip Enable Compare Cycle Time Short Cycle 2 tELEH Chip Enable LOW Pulse Width Medium Cycle Long Cycle 3 4 5 6 7 8 9 10 11 12 13 14 tEHEL tCVEL tELCX tELQX tELQV tEHQZ tDVEL tELDX tELFFV tEHMFX tEHMFV tRLRH Chip Enable HIGH Pulse Width Control Input to Chip Enable LOW Setup Time Control Input from Chip Enable LOW Hold Time Chip Enable LOW to Outputs Active Register Read Chip Enable LOW to Outputs Valid -70 Min. 70 15 35 55 15 2 10 3 30 52 3 2 10 50 0 18 100 100 0 10 3 2 10 Max. Min. 90 25 50 75 15 2 10 3 -90 Max Notes 4 4 4 5 5 6 50 75 15 4,6 4,6 7 Memory Read Chip Enable HIGH to Outputs HIGH-Z Data to Chip Enable LOW Setup Time Data from Chip Enable LOW Hold Time Chip Enable LOW to Full Flag Valid Chip Enable HIGH to /MF, /MM Invalid Chip Enable HIGH to /MF, /MMValid Reset LOW Pulse Width 75 25 8 Table 17: Switching Characteristics Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. -1.0 Volts for a duration of 10 ns measured at the 50% amplitude points for Input-only lines (see Figure 5 on page 19). Common I/O lines are clamped, so that signal transients can not fall below -0.5 Volts. Over ambient operating temperature range and Vcc(min.) to Vcc(max.). See Table 6 on page 15. Control signals are /W, and /CM. With load specified in Figure 4 on page 19, Test Load A. With load specified in Figure 4 on page 19, Test Load B. /E must be HIGH during this period to ensure accurate default values in the configuration registers. With output and I/O pins unloaded. 20 Rev. 3.1 Timing Diagrams LIST-XL Family TIMING DIAGRAMS 2 3 2 /E 4 /W 4 /CM 5 3 /E 4 5 /W 4 /CM 5 5 9 10 DQ15 - 0 7 DQ15 - 0 8 11 /FF 6 Figure 6: Read Cycle Figure 7: Write Cycle 1 2 3 /E 4 5 /W 4 5 /CM V AL ID 13 /M F, /M M 12 Figure 8: Compare Cycle Rev. 3.1 21 LIST-XL Family PACKAGE OUTLINE PACKAGE OUTLINE He E A2 A1 Hd D Pin 1 L 1 L e b c Figure 9: 32-Pin LQFP Package Dim. A1 Min. Max. 0.05 0.15 Dim. A2 1.35 1.45 Dim. b 0.30 0.45 Dim. c 0.09 0.02 Dim. D 7.00 Dim. E 7.00 Dim. e 0.80 nom Dim. Hd 9.00 Dim. He 9.00 Dim. L1 1.00 nom Dim. L 0.45 0.75 Table 18: 32-Pin LQFP Dimensions (dimensions are in mm) ORDERING INFORMATION Part Number MU9C3640L-70TZC MU9C3640L-90TZC MU9C3640L-90TZI MU9C5640L-70TZC MU9C5640L-90TZC MU9C5640L-90TZI Cycle Time 70 ns 90 ns 90 ns 70 ns 90 ns 90 ns Package 32-Pin LQFP 32-Pin LQFP 32-Pin LQFP 32-Pin LQFP 32-Pin LQFP 32-Pin LQFP Temperature 0–70° C 0–70° C -40–85° C 0–70° C 0–70° C -40–85° C Voltage 3.3 ± 0.3 3.3 ± 0.3 3.3 ± 0.3 3.3 ± 0.3 3.3 ± 0.3 3.3 ± 0.3 ORDERING INFORMATION FOR LEAD-FREE PRODUCTS: For ordering Lead-Free products please add an "F" directly after the product name (in front of the speed grade). Example: MU9C5640LF-90TZC MUSIC Semiconductors’ agent or distributor: MUSIC Semiconductors reserves the right to make changes to its products and specifications at any time in order to improve on performance, manufacturability or reliability. Information furnished by MUSIC is believed to be accurate, but no responsibility is assumed by MUSIC Semiconductors for the use of said information, nor for any infringements of patents or of other third-party rights which may result from said use. No license is granted by implication or otherwise under any patent or patent rights of any MUSIC company. © Copyright 2000 and 2002, MUSIC Semiconductors Worldwide Headquarters MUSIC Semiconductors 5850 T.G. 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