MU9C8328A-RDC

Preliminary Data Sheet MU9C8328A Ethernet Interface APPLICATION BENEFITS GENERAL DESCRIPTION The MU9C8328A speeds up bridging operations using Ethernet controller chips with serial NRZ data outputs, such as AMD’s MACE™, National’s SONIC™, and Motorola’s QUICC™ controllers, by parsing the Ethernet frame independently of the Ethernet controller device, and notifying it whether to accept or reject the incoming frame. The MU9C8328A supports both positive and negative filtering on the Destination address and learning of new Source addresses, by efficiently controlling the compare activities of the MUSIC LANCAM Family. Filtering and learning routines are user configurable. These routines are automatically invoked by the internal state machine based on the contents of the incoming frame and the configuration settings. For aging and other housekeeping routines, the MU9C8328A provides the proper sequencing and timing of LANCAM accesses for an external processor. The MU9C8328A receives serial NRZ data from the Ethernet controller chip, finds the Start delimiter, and loads the DA and SA into registers. The DA is sent to the LANCAM for filtering and, depending on the filter action DQ(15-0) Ø Single port 10 MHz Ethernet address parsing, filtering, and learning at wire speed Ø Glue-free interface between the MUSIC LANCAM® Family and AMD, National, Motorola, or similar Ethernet Controllers having an NRZ serial data port Ø Selectable filtering and learning decisions on DA and SA compares Ø Supports aging with built-in LRU purge routine Ø Supports cascaded MUSIC LANCAM series for long station lists Ø Host processor port for LANCAM initialization and housekeeping activities Ø Supports system clock rates from 20 MHz to 33 MHz Ø Compatible with MU9C8328 Ø 100-pin PQFP package Ø 5 Volt operation /CM /EC LA N CA M INTER FAC E /CS /AS SE R CL K SE R DAT /NET R DY /REJ ECT N ET W O R K INT ER FA C E STA TE M A C HINE 4 /FF /W /MF /E /WE A(3-0) D(15-0) R EA D Y /INT C O NT R O L STAT U S O P -C O D E ASS O C IATE D DATA SY S C L K /RESE T P R O C ESS O R INT ER FA C E Block Diagram MUSIC Semiconductors, the MUSIC logo, the phrase “MUSIC Semiconductors”, and LANCAM are registered trademarks of MUSIC Semiconductors. All other trademarks are registered by their respective owners. MUSIC is a trademark of MUSIC Semiconductors. 24 June 1999 Rev. 0.8 Draft Note: This document version has not completed MUSIC’s internal approval process, therefore it should be rechecked with a released version or with factory personnel. MU9C8328A Ethernet Interface GENERAL DESCRIPTION Continued selected, notifies the controller whether to copy or purge the frame. The SA is then sent to the LANCAM for comparison, and if no match is found, can be learned to the Next Free address in the LANCAM. Scheduling is done within the MU9C8328A so that each filtering action completes in the time of a minimum length frame. The filtering and learning routines are preprogrammed in the MU9C8328A, with decision options set in the Control register. A Status register is provided so the host processor can determine the results of activities. The specific Op-Code for the LANCAM learning instruction is by default a MOV NF, CR, V, but it can be overridden by writing a value to the Op-Code register. Aging and purging activity is directly controlled by the host processor. The READY signal notifies the host processor that processor operations are complete. The /INT signal notifies the processor that a network frame has been processed and the result stored in the Status register. The processor can turn off the network filtering activity to have total control of the LANCAM; during this time the controller can be notified to accept or reject all frames. PIN DESCRIPTIONS All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW. Inputs should never be left floating. Refer to the Electrical Characteristics section for more information. NETWORK INTERFACE SERCLK (Serial Clock, Input, TTL) SERCLK is the nominally 10 MHz clock from the Ethernet controller chip to the MU9C8328A. Frame parsing begins only after the internal clock detector determines that SERCLK is valid. Internally pulled down with nominal 50K resistor. SERDAT (Serial Data, Input, TTL) SERDAT is the NRZ data from the 10 MHz Ethernet controller chip. The MU9C8328A uses SERCLK to strobe SERDAT looking for a Start Frame delimiter (SFD), at which point it begins filtering and learning activity on the Destination Address (DA) and Source Address (SA). /REJECT (Reject, Output, TTL) The MU9C8328A takes /REJECT LOW to notify the Ethernet controller chip to reject a frame under conditions set in the Filter Control register. /NETRDY (Network Ready, Input, TTL) If /NETRDY is LOW, the MU9C8328A begins parsing frame data received on the SERDAT input if SERCLK is valid. The Ethernet controller chip, or the user, takes /NETRDY HIGH to indicate that SERCLK or SERDAT is invalid or is transmitting. The MU9C8328A frame parser and internal state machines are returned to an idle state after safely completing any LANCAM activity, while ignoring any compare results. Internally pulled down with nominal 50K resistor. PROCESSOR INTERFACE SYSCLK (System Clock, Input, TTL) SYSCLK is a 20 MHz to 33 MHz continuous clock provided by the host system and is the master clock within the MU9C8328A. It is used to determine the presence of a valid clock on the SERCLK input, operate the three internal state machines, and provide the proper timing of the signals on the LANCAM port. If SYSCLK is below 30 MHz, a LANCAM speed grade of 120 ns is acceptable. Above 30 MHz, a LANCAM speed grade of 90 ns or better is required. /CS (Chip Select, Input, TTL) /CS is taken LOW by the host processor to gain access to the registers of the MU9C8328A or to directly access the LANCAM through the MU9C8328A internal LANCAM registers. The state of /CS becomes effective on the rising edge of SYSCLK. When /CS goes HIGH, the MU9C8328A continues filtering and learning based on conditions set in the Filter Control register and the frame activity on the network interface. /AS (Address Strobe, Input, TTL) The falling edge of /AS latches the A(2–0) bus, and when both /AS and /CS are LOW, the processor state machine is enabled by first rising edge of the SYSCLK to begin writes into or reads out of the MU9C8328A. Rev. 0.8 Draft 2 MU9C8328A Ethernet Interface PIN DESCRIPTIONS Continued /WE (Write Enable, Input, TTL) /WE determines the direction of data flow into or out of the MU9C8328As processor interface. It also determines the state of /W to the LANCAM when the processor is accessing the MU9C8328As internal LANCAM registers. If /WE is LOW, the data is written into the register selected by the A(3–0) bus. If /WE is HIGH, then data is read out of the register selected by the A(3–0) bus. A(3–0) (Address Bus, Input, TTL) A(3–0) select the internal register in the MU9C8328A accessed by the host processor as shown in Table 1. A(3–0) are latched by the falling edge of /AS. A(3) is internally pulled down with a nominal 50K resistor to maintain compatibility with the MU9C8328. D(15–0) (Data Bus, I/O, Three-state TTL) D(15–0) is the processor data bus into and out of the MU9C8328A, and is demuxed to the internal registers as selected by the A(2–0) bus. If the register selected is the Control, Status or Op-Code register, when /WE is LOW, D(15–0) is loaded on the second rising edge of SYSCLK after both /AS and /CS are LOW. When /WE is HIGH, data from the selected register is output to the D(15–0) bus on the second rising edge of SYSLCK after both /AS and /CS are LOW. For CAM access, the write or read operation is completed when READY returns HIGH. If /CS is HIGH, or if data is not being read out of the MU9C8328A, the output buffers go to HIGH-Z. Internally pulled down with nominal 50K resistor. READY (Ready, Output, Three-state, TTL) When writing to the Control, Status, or Op-Code register, READY goes LOW on the first rising edge of SYSCLK after both /AS and /CS are LOW and returns HIGH on the next rising edge of SYSCLK. For a read cycle from those registers, READY may only show a negative-going spike at the first rising edge of SYSCLK after both /AS and /CS are LOW. The data will be valid before the next rising edge of SYSCLK. When writing to the CAM registers, READY will go LOW on the first rising edge of SYSCLK after both /CS and /AS are LOW. READY returns HIGH three SYSCLK cycles after. When reading from the CAM registers, READY will return HIGH five SYSCLK cycles later. DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 GND GND VCC VCC DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 55 54 53 58 57 56 52 51 GND VCC DQ1 DQ0 81 82 83 /FF /MF /EC /CM /E /W GND VCC 84 85 86 87 88 89 90 91 92 93 94 /RESET READY /INT /WE /AS /CS 95 96 97 98 99 100 50 49 48 47 46 45 44 SERCLK SERDAT /REJECT NTE ST OUT NTEST_EN (Tie Low) GND VCC /NETRDY TEST 1 TEST 2 TEST 3 TEST 4 TEST 5 D0 MU9C8328A-RDC 100-pin PQFP (Top View) 43 42 41 40 39 38 37 36 35 34 33 32 31 24 25 26 27 28 GND VCC D2 10 11 12 13 14 15 16 17 18 2 3 4 7 8 9 19 20 21 22 23 5 6 D14 D13 D12 D11 GND VCC D10 D9 D8 D7 D6 D5 SYSCLK VCC GND A1 A3 A0 A2 D15 Pinout Diagram 3 Rev. 0.8 Draft D4 D3 D1 29 30 1 MU9C8328A Ethernet Interface PIN DESCRIPTIONS Continued /INT (Interrupt, Output, Three-state TTL) /INT goes LOW to signal the processor that a frame has been processed, and the results loaded into the Status register. /INT returns HIGH when the Status register is read. /RESET (Reset, Input, TTL) When /RESET is taken LOW, all the internal state machines are reset to their initial state. Any data stored in the input address parser is cleared, and the Control, Status, and Learn Op-Code registers are reset to their default values. /RESET is synchronous and should be held LOW for a minimum of two SYSCLK cycles. The user must set the LANCAM Segment Control register after asserting /RESET. /EC (Enable Daisy Chain, Output, TTL) The MU9C8328A takes /EC LOW to control a daisy chain of LANCAMs by generating the /MF output from the LANCAM in the case of a match between the contents of its Comparand register and its memory. When /EC is LOW, only the LANCAM containing the match will respond to write cycles, or output read data. When /EC is HIGH, all LANCAMs will respond to write cycles. /MF (Match Flag, Input, TTL) The LANCAM takes /MF LOW to indicate to the MU9C8328A that a match was found in its memory with the contents of its Comparand register. /MF returns HIGH after the MU9C8328A takes /EC HIGH, or the match condition is no longer valid. In a daisy chain of LANCAMs, the /MF signal comes from the /MF output of the last LANCAM in the string. Internally pulled down with nominal 50K resistor. /FF (Full Flag, Input, TTL) The LANCAM takes /FF LOW to indicate to the MU9C8328A that the LANCAM has no empty locations remaining. /FF is taken HIGH when the LANCAM has one or more locations still empty. In a daisy chain of LANCAMs, the /FF signal comes from the /FF output pin of the last LANCAM in the string. Internally pulled down with nominal 50K resistor. LANCAM INTERFACE DQ(15–0) (CAM Data Bus, I/O, Three-state TTL) The DQ(15–0) bus communicates 16-bit data or instructions between the MU9C8328A and the LANCAM. When no data is being transmitted by either, the bus goes HIGH-Z. Internally pulled down with nominal 50K resistor. /E (Chip Enable, Output, TTL) The MU9C8328A takes /E LOW to initiate LANCAM activity by registering the /W, /CM, /EC, and DQ(15–0) signals into the LANCAM. /E is taken HIGH to register returning data into the MU9C8328A. /W (Write Gate, Output, TTL) The MU9C8328A outputs /W to control the direction of data flow between the MU9C8328A and the LANCAM. If /W is LOW at the falling edge of /E, the MU9C8328A is outputting data to the DQ(15–0) bus for the LANCAM to input. When /W is HIGH at the falling edge of /E, the LANCAM outputs data to the DQ(15–0) bus for input to the MU9C8328A. /CM (Data/Command Select, Output, TTL) The MU9C8328A outputs /CM to control whether the LANCAM interprets the DQ(15–0) bus as containing command information or data. If both /CM and /W are LOW at the falling edge of /E, the MU9C8328A is outputting an instruction for the LANCAM to execute, or a value for one of the LANCAM configuration registers. If /CM is LOW while /W is HIGH, then the LANCAM will be outputting data from one of its configuration registers to the MU9C8328A. If /CM is HIGH while /W is LOW, the MU9C8328A is outputting data for the LANCAM to place in its data registers or memory. If /CM is HIGH while /W is HIGH, the LANCAM is outputting data from one of its data registers or memory to the MU9C8328A. Rev. 0.8 Draft 4 TEST NTEST_EN Reserved–Tie low. NTTESTOUT Reserved–Do not connect. TEST (5–0) Reserved for manufacturing tests–Do not connect. POWER AND GROUND VCC, GND (Positive Power Supply, Ground) The VCC pins must be connected externally to a power source regulated to 5.0 ± 0.5 Volts, and should be adequately bypassed to the Ground pins through both high and low frequency capacitors. The Ground pins should all be connected to a common ground plane. MU9C8328A Ethernet Interface FUNCTIONAL DESCRIPTION The MU9C8328A works with the MUSIC LANCAMs to provide a complementary and versatile 10 MHz Ethernet filtering solution for bridges, routers, and switches. Using the serial NRZ data stream and clock available from many Ethernet controller chips, the MU9C8328A parses the incoming frame, finds the Start Delimiter, and forms the Destination and Source addresses into 16-bit words for relay to the LANCAM. After all three 16-bit DA segments have been loaded into the LANCAM, an automatic compare occurs between the incoming DA and the 48-bit MAC addresses stored in the LANCAM. If a match is found, the MU9C8328A is notified, and if Control register bit 5 is set for negative filtering, the /REJECT line will be asserted if Control register bit 3 is set. An interrupt can also be generated over the /INT pin if Control register bit 8 is set. Also, if Control register bit 0 is set, the Associated data in segment 0 of the matching entry in the LANCAM will be retrieved and stored in the Associated Data register for reading by the host processor. If a match is not found on the DA, and Control register bit 5 was set for positive filtering, the /REJECT line will be asserted. An interrupt can also be enabled for a no-match on a DA using Control register bit 10. After the DA filtering, the Source Address is loaded into the LANCAM in three segments. Upon the last SA load, an automatic compare again takes place. If there is a match between the SA and an entry in the CAM, and Control register bit 7 was set, an interrupt is asserted. Positive and negative filtering on the SA is also possible, set by Control register bit 4, and the /INT pin may be asserted as well. In the case of a no-match on an SA, the SA can be automatically “learned” (that is, moved to the first empty location in the LANCAM) if Control register bit 1 is set. If a Loss of Carrier is detected by SERCLK staying LOW for more than 16 SYSCLK cycles, an interrupt is triggered if Control register bit 12 is set. This interrupt also activates if a collision is detected. The host processor can access the MU9C8328A internal registers, shown in Table 1, at any time, even when a frame is being processed. Access to the LANCAM through the LANCAM access registers (04H to 07H) is arbitrated, however, with the network having precedence. The host processor can have control of the LANCAM by setting the Network Enable bit in the Control register (bit 13) to a 0, which will disable network filtering until it is returned to a 1. While disabled, bit 14 in the Control register sets the MU9C8328A to accept all frames by keeping /REJECT HIGH, or to reject all frames by keeping /REJECT LOW. Registers 04H through 07H give the host processor access to the LANCAM for Command and Data Write and Read cycles, with /EC HIGH or LOW. This is often needed for housekeeping activities, such as preventing the LANCAM from becoming full by aging out old entries based on time stamps stored in the Associated data (Segment 0) of the LANCAM memory. Registers 08H holds the update Op-Code. This is 0300H after reset to maintain compatibility with the MU9C8328. To update a SA entry time stamp, the device must be initialized to auto-learn in the Control register and 0328H (MOV HM, CR) must be written to the update Op-Code register. When filtering the SA, if it does not exist in the CAM, the SA gets put into the next free address. If it already has been entered in the CAM, just the time stamp bits are updated with the value in the time stamp register. Register 08H holds the update Op-Code, 09H is the Purge Routine Op-Code register and 0AH is the Time Stamp register. Writing a value to the TimeStamp register initiates a Purge routine. The lower 8 bits written to the Time Stamp register is the time stamp that will be purged. The upper 8 bits written to the register will be the new time stamp for data. The /INT pin will go LOW at the end of the SA field to indicate an interrupt for any of the reasons set in the Control register. Reading the Status register to discover the nature of the interrupt will take the /INT pin HIGH again. The READY signal goes LOW after a host processor write to a register or the LANCAM to indicate that the Write cycle has begun and return HIGH after a fixed number of SYSCLK cycles. It will also go LOW during a read from the LANCAM and return HIGH when the data from the LANCAM is valid. Since a network compare activity has precedence over a host process access to the LANCAM, READY will stay LOW until the network activity is complete and the host-induced LANCAM read has completed. Figure 1 shows a typical network filtering sequence, where the MU9C8328A’s Control register was set to 2109H. This setting enables network filtering, enables an interrupt for a match found on the DA, enables negative filtering on the DA (reject if a DA match is found), enables asserting the /REJECT pin for compares on the DA, and enables retrieving the Associated Data field from the matching location in the LANCAM. 5 Rev. 0.8 Draft MU9C8328A Ethernet Interface FUNCTIONAL DESCRIPTION Continued A(3–0) 0H 0H 1H 1H 2H 2H 3H 3H 4H 4H 5H 5H 6H 6H 7H 7H 8H 8H 9H 9H AH AH /WE L H L H L H L H L H L H L H L H L H L H L H Resource Selected Control register Control register Reserved Status Register Learn Op-Code Register Learn Op-Code Register Reserved Associated Data Register LANCAM Command Cycle with /EC LOW LANCAM Command Cycle with /EC LOW LANCAM Command Cycle with /EC HIGH LANCAM Command Cycle with /EC HIGH LANCAM Data Cycle with /EC LOW LANCAM Data Cycle with /EC LOW LANCAM Data Cycle with /EC HIGH LANCAM Data Cycle with /EC HIGH Update Op-Code Register Update Op-Code Register Purge Op-Code Register Purge Op-Code Register Time stamp Register Time stamp Register Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Read Write Read Action Write Read Table 1: Address Decode DA Match Found SERDAT /E /CM /W /EC /MF /REJECT /INT Preamble SFD DA1 DA2 DA3 SA1 SA No-Match/Learn SA2 SA3 Length/Type Data Figure 1: Typical Network Filtering Rev. 0.8 Draft 6 MU9C8328A Ethernet Interface FUNCTIONAL DESCRIPTION Continued CONTROL REGISTER (0000) Bit 15 14 13 12 11 10 9 8 7 6 5 Mnemonic DONE P/R NETEN ERR FULL NODA NOSA DA SA REJECT DAPON Description 1: Enables an interrupt when both the DA and SA CAM lookups are complete. 1: Passes all frames, 0: Rejects all frames. NETEN must be set to 0 for this option. 1: Enables network filtering, 0: Disables network filtering. 1: Enables an interrupt for a frame error caused by loss of carrier or collision. 1: Enables an interrupt if the LANCAM is full. 1: Enables an interrupt for a no-match on DA. 1: Enables an interrupt for a no-match on SA. 1: Enables an interrupt for a DA match. 1: Enables an interrupt for an SA match. 1: Enables an interrupt for a reject. 1: Rejects frame if there is no DA match (positive filtering). 0: Rejects frame if there is a DA match (negative filtering). This bit is a “Don’t Care” if DAEN is 0. 1: Rejects frame if there is no SA match (positive filtering). 0: Rejects frame if there is an SA match (negative filtering). This bit is a “Don’t Care” if SAEN is 0. 1: Enables asserting the /REJECT pin after a DA compares, based on bit 5. 1: Enables asserting the /REJECT pin after an SA compares, based on bit 4. 1: Enables auto-learning on no-match of SA. 1: Enables a read of Associated data after a DA match. 4 SAPON 3 2 1 0 DAEN SAEN LEARN ASSOC Table 2: Register Descriptions 7 Rev. 0.8 Draft MU9C8328A Ethernet Interface FUNCTIONAL DESCRIPTION Continued STATUS REGISTER (0001) Bit 15–8 7 6 5 4 3 2 1 0 COL LOC BUSY MATCH FULL DAM SAM REJECT Mnemonic Description Reserved. 1 = Collision detected. 1 = Loss of carrier detected. 1 = Network port is busy using the LANCAM. 1 = A match was found. 1 = The LANCAM is full. 1 = A Destination Address match was found. 1 = A Source Address match was found. 1 = The frame was rejected. LEARN OP-CODE REGISTER (0010) Bit Mnemonic Description Contains the Op-Code to be used for an auto-learn, if enabled. Default is 0334H (MOV NF, CR, V), but can be overwritten. UPDATE OP-CODE REGISTER (1000) Bit 15-0 Mnemonic UOC Description Contains the Op-Code to be used for updating the time stamp on a SA match Default is 0300H (NOP). To update time stamp write 0328H (MOV HM, CR) to this register. PURGE OP-CODE REGISTER (1001) Bit 15-0 Mnemonic POC Description Contains the Op-Code to be used for the purge routine. Default is 043DH (VBC ALM,E). TIME STAMP REGISTER (1010) Bit 15-8 7-0 Mnemonic NEW_TS OLD_TS Description The value used for time stamp updates. The value used to purge old entries. 15–0 ALOC Table 2: Register Descriptions Continued Rev. 0.8 Draft 8 MU9C8328A Ethernet Interface APPLICATIONS Connections Connection diagrams are shown in Figures 2, 3, and 4 for National’s SONIC, AMD’s MACE, and Motorola’s QUICC Ethernet controller chips. Other controller chips that provide a serial NRZ received data port and clock can also be used in similar fashions. The /NETRDY line is provided for controller chips that output data on the received data line while transmitting. If /NETRDY is deasserted, the internal network state machine will safely complete any current activity and then wait until /NETRDY is asserted again before parsing another frame. If the controller chip does not output data on the received data line while transmitting, /NETRDY may be tied to ground, and the MU9C8328As valid clock detector will determine when it is time to start parsing a frame. Initialization of the LANCAM Before using, the MUSIC LANCAMs need to be configured for the number of LANCAMs in a daisy chain and for the filtering conditions in the Control and Segment Control registers. Before configuring the LANCAMs, bit 13 in the MU9C8328A Control register needs to be set to 0, to turn off network filtering. Table 3 shows the steps for configuring two LANCAMs in a daisy chain. The routine selects register 05H in the MU9C8328A, which sends Command Write cycles to the LANCAM. The sequence shown resets the LANCAMs, sets the Page address for both LANCAMs in the daisy chain, then sets the Control and Segment Control registers. If a Mask register were needed, then the sequence would be modified to set the Persistent destination to MR1 or MR2, use MU9C8328A register 07H to write data into the Mask register, change the final Control register value to 8051H or 8061H instead of 8041H to invoke MR1 or MR2 during compares, and then resetting LANCAM /E /CM LANCAM /E /CM /W /EC /MF /FF /W /EC /MF /FF DQ(15-0) DQ(15-0) AM79C940 /E /CM /W /EC /MF /FF SYSCLK /RESET DP83932 /E /CM /W /EC /MF /FF SYSCLK /RESET SRDCLK SRD TXEN /EAM/R SERCLK SERDAT /NETRDY /REJECT /CS /AS RXCo RXDo TXE SERCLK SERDAT /NETRDY /REJECT /CS /AS MU9C8328A /WE A(3-0) D(15-0) READY /INT MU9C8328A /WE A(3-0) D(15-0) READY /INT /PREJ Figure 2: AMD’s MACE™ Connection Diagram Figure 3: National’s SONIC™ Connection Diagram LANCAM MC68160 EE ST RCLK RX RENA /E /CM /W /EC /MF /FF SYSCLK /RESET /CS SERDAT /NETRDY /AS /WE /E /CM /W /EC /MF /FF DQ(15-0) SERCLK MU9C8328A RCLK RXD RENA /RRJCT /REJECT A(3-0) D(15-0) READY /INT MC68360 QUICC Figure 4: Motorola’s QUICC™ Connection Diagram 9 Rev. 0.8 Draft MU9C8328A Ethernet Interface APPLICATIONS Continued the Persistent destination to the Comparand register as shown in Table 3. If only one LANCAM is used, Table 3 would be modified to replace steps 9 through 14 with a TCO DS (0228H) followed by a 0000H. Enabling Network Activity Responding to Interrupts After the LANCAMs have been initialized, the MU9C8328A is enabled to begin processing network traffic by setting bit 13 (NETEN) in its Control register to a 1 along with the desired filtering actions and interrupt enables. Step A(2–0) 0H 1 5H 2 5H 3 5H 4 5H 5 5H 6 5H 7 5H 8 5H 9 5H 10 5H 11 5H 12 5H 13 5H 14 5H 15 5H 16 5H 17 5H 18 5H 19 5H 20 7H 21 5H 22 5H 23 5H 24 5H 25 5H 26 5H 27 5H 28 7H 29 7H 30 7H 31 7H 32 5H 33 5H 34 5H 35 5H 36 0H 37 /WE Mnemonic D(15–0) C000H L 0000H H TCO_DS 0228H L FFFFH L TCO_CT 0200H L 0000H L TCO_PA 0208H L 0000H L SFF 0700H L TCO_PA 0208H L 0001H L SFF 0700H L TCO_CT 0200H L 0000H L SBR 0619H L TCO_CT 0200H L 8111H L TCO_SC 0210H L 0000H L SPD_MR1 0108H L FFF0H L SPD_CR 0100H L SFR 0618H L TCO_CT 0200H L 8041H L SPD_MR1 0108H L TCO_SC 0210H L 1C04H L FFF0H L FFFFH L FFFFH L FFFFH L SPD_CR 0100H L TCO_SC 0210H L 3808H L SPS_HM 0005H L 290BH L Depending on the filtering or error interrupt conditions set in the MU9C8328A Control register, the /INT line will assert at the end of the frame SA field. The host can then read the MU9C8328A Status register to determine the cause of the interrupt, whereupon the Status register is reset. If there was a DA match interrupt and read associated data was set, then the associated data segment stored in the LANCAM at the same location that matched the frame’s DA can be read out of the Associated Data register (03H). Comments Pass all frames during initialization Command Read to reset LANCAM state machines Selects all Device Select registers Selects all LANCAMs Selects all Control registers Resets all memory locations Selects first Page Address register Writes first Page Address value Sets Full flag on first LANCAM Selects second Page Address register Writes second Page Address value Sets Full flag on second LANCAM Selects all Control registers Resets all Full flags Select Background Register set TCO CT 48RAM, 16CAM, MR1, Enhanced mode Select Segment Control register Set Read and Write to segment 0 Set Persistent Destination to Mask Register 1 Setup Time Stamp in lowest 8 bits of segment 0 Set Persistent Destination to Comparand register Select Foreground Register set Select Command register 48CAM, 16RAM, No Mask, Enhanced mode Set Persistent Destination to Mask Register 1 Select Segment Control register Set to write Segments 0, 1, 2, and 3 Write to Segment 0 of MR1 Write to Segment 1 of MR1 Write to Segment 2 of MR1 Write to Segment 3 of MR1 Set Persistent Destination to Comparand register Select Segment Control register Write Segments 1–3, Read Segment 0 Set Persistent source to Highest match Enable filter, Negative filter on DA, enable learn Table 3: LANCAM Initialization Code Rev. 0.8 Draft 10 MU9C8328A Ethernet Interface ABSOLUTE MAXIMUM RATINGS Supply Voltage Voltage on all Other Pins Temperature Under Bias Storage Temperature DC Output Current -0.5 Volts to 7.0 Volts -0.5 to VCC+0.5 Volts (-2.0 Volts for 10 ns, measured at the 50% point) -55°C to +125°C -55°C to +125°C 20 mA (per Output, one at a time, one second duration) Stresses exceeding those listed under Absolute Maximum Ratings may induce failure. Exposure to absolute maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied. All voltages are referenced to GND. OPERATING CONDITIONS (voltages referenced to GND at the device pin) Symbol VCC VIH VIL TA Parameter Operating Supply Voltage Min 4.5 2.0 Input Voltage Logic 1 0.7 VCC -0.5 Input Voltage Logic 0 -0.5 0 Ambient Operating Commercial Temperature Industrial -40 Typical 5.0 Max 5.5 VCC + 0.5 VCC + 0.5 0.8 0.3 VCC 70 +85 Units Volts Volts Volts Volts Volts °C °C Notes D(15-0) and DQ(15-0) only 1 1D(15-0) and DQ(15-0) only Still Air ELECTRICAL CHARACTERISTICS Symbol ICC VOH VOL IIZ IOZ Parameter Average Power Supply Current Output Voltage Logic 1 Output Voltage Logic 0 Input Leakage Current Output Leakage Current -2 20 -10 100 2.4 0.4 2 250 10 Min Typical Max 200 Units mA Volts Volts µΑ µΑ µΑ Notes tELEL = tELEL(min) IOH = -8.0mA IOL = 8.0mA VSS ≤ VIN ≤ VCC VIH = VDD; 9 VSS ≤ VOUT ≤ VCC; DQN = HIGH Z CAPACITANCE Symbol CIN COUT Parameter Input Capacitance Output Capacitance Max 15 15 Units pF pF Notes f=1MHz, VIN = 0 V. f=1MHz, VOUT = 0 V. AC TEST CONDITIONS Input Signal Transitions Input Signal Rise Time Input Signal Fall Time Input Timing Reference Level Output Timing Reference Level 0.0 to 3.0 Volts < 3 ns < 3 ns 1.5 Volts 1.5 Volts SWITCHING TEST FIGURES 5.0 V olts 5.0 V olts Input Waveform R1 = 44 6 Ω To Dev ice Under Test R2 = 17 4 Ω C1 = 30 pf (Incl udes jig) C1 = 5 pf To Dev ice Und er Test R2 = 17 4 Ω R1 = 44 6 Ω 0V V IL (MIN) 50% Amplitude Point 10ns Figure 5: AC Test Load A Figure 6: AC Test Load B 11 Figure 7: Input Signal Waveform Rev. 0.8 Draft MU9C8328A Ethernet Interface SWITCHING CHARACTERISTICS No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol tKHKH tKHKL tKLKH tKHCH tCHKH tCHCH tCHCL tCLCH tSLKH tSHKH tSLSH1 tAVSL tSLAX tWVKH tWVWX tKHWH tDVKH tKHDX tKHRL tKHRH tRLRH1 tTHCH tCHTL tYLTV tKHJL tKHDZ1 tKHDV tKHDZ tRLRH2 tKHEL tKHEH tKHGV tKHGX tEHML tRHSH tSHDZ tKHDX tKHDV tELQV tEHQZ Parameter (all times in nanoseconds) SYSCLK Period SYSCLK HIGH Pulse Width SYSCLK LOW Pulse Width SYSCLK HIGH to SERCLK HIGH Set-up Time SERCLK HIGH to SYSCLK HIGH Set-up Time SERCLK Period SERCLK HIGH Pulse Width SERCLK LOW Pulse Width Chip or Address Select LOW to SYSCLK HIGH Set-up Chip or Address Select HIGH to SYSCLK HIGH Set-up Chip or Address Select LOW Pulse Width - Write Cycle Address Bus VALID to Address Select LOW Set-up Address Select LOW to Address Bus INVALID Hold Write Enable LOW to SYSCLK HIGH Set-up Time Write Enable LOW Pulse Width SYSCLK HIGH to Write Enable HIGH Hold Time Data VALID to SYSCLK HIGH Set-up Time SYSCLK HIGH to Data INVALID Hold Time SYSCLK HIGH to Ready LOW Delay Time SYSCLK HIGH to Ready HIGH Delay Time Ready LOW Pulse Width-Write Cycle SERDAT HIGH to SERCLK HIGH Set-up Time SERCLK HIGH to SERDAT LOW Hold Time NetReady LOW to SERDAT HIGH Set-up Time SYSCLK HIGH to REJECT LOW Delay Time Chip or Address Select LOW Pulse Width-Read Cycle SYSCLK HIGH to Data VALID Delay Time SYSCLK HIGH to Data HIGH-Z Delay Time Ready LOW Pulse Width-CAM Write Cycle SYSCLK HIGH to CAM Enable LOW Delay Time SYSCLK HIGH to CAM Enable HIGH Delay Time SYSCLK HIGH to CAM Controls VALID Delay Time SYSCLK HIGH to CAM Controls INVALID Delay Time CAM Enable HIGH to Match Flag LOW Delay Time Ready HIGH to Chip or Address Select HIGH Set-up Chip or Address Select HIGH to Data HIGH-Z Delay SYSCLK HIGH to Data Bus Active-Read SYSCLK HIGH to Data Bus VALID Delay Time CAM Enable LOW to DQ Bus VALID-Read CAM Enable HIGH to DQ Bus HIGH-Z Min 30 0.4 · tKHKH 0.4 · tKHKH 0 0 0.4 · tCHCH 0.4 · tCHCH 10 10 2 · tKHKH 5 10 10 tKHKH 10 10 10 Typ Max Notes 50 0.6 · tKHKH 0.6 · tKHKH 100 0.6 · tCHCH 0.6 · tCHCH 2 2 30 30 tKHKH 10 10 10 11 · tKHKH 2 · tKHKH 30 30 3 · tKHKH 30 30 30 30 30 5 30 5 50 85 20 6 6 7 8 3 4 5 5 6 Rev. 0.8 Draft 12 MU9C8328A Ethernet Interface NOTES 1. 2. 3. 4. 5. 6. 7. 8. 9. -1.0 Volts for a duration of 10 ns measured at the 50% amplitude points for input-only lines (Figure 7). If this timing parameter is violated, the read or write cycle will start one SYSCLK later (assuming /AS or /CS is held). Before first network data pulse. From the SYSCLK that strobed the last DA or SA segment into the LANCAM. LANCAM Controls include /W, /CM, and /EC. See the LANCAM Handbook for additional information on LANCAM Timing Specs. With load specified in Figure 5. With load specified in Figure 6. Pin A(3) Clock Timing 1 2 3 SYSCLK 4 SERCLK 8 7 6 5 Processor Interface Write Cycle SYSCLK 9 /CS 9 /AS 12 A(2-0) 14 15 /WE 17 D(15-0) 19 READY 21 20 18 16 13 10 10 11 11 13 Rev. 0.8 Draft MU9C8328A Ethernet Interface Network Interface Timing SERCLK 23 1 24 /NETRDY 0 1 0 1 0 1 0 1 1 0 1 0 1 22 SERDAT SYSCLK 25 /REJECT Processor Interface Read Cycle SYSCLK 26 9 /CS 26 9 /AS 12 A(2-0) 15 13 10 10 14 /WE 27 D(15-0) 28 Rev. 0.8 Draft 14 MU9C8328A Ethernet Interface Processor Interface Write Cycle to LANCAM SYSC LK /CS /AS A(2-0) /WE D(15-0) 29 READY 30 /E 32 /CM 32 /W 32 /EC 32 DQ(15-0) 34 /MF 33 33 33 33 31 Processor Interface Read Cycle from LANCAM SYSCLK 35 /CS 35 /AS 36 36 A(2-0) /WE 37 D(15-0) 38 READY /E /CM /W /EC 39 DQ(15-0) 40 15 Rev. 0.8 Draft MU9C8328A Ethernet Interface ORDERING INFORMATION PART NUMBER MU9C8328A - RDC MU9C8328A - RDI PACKAGE 100-PIN PQFP 100-PIN PQFP TEMPERATURE 0–70° C -40– 85° C VOLTAGE 5.0 ± 0.5 5.0 ± 0.5 Package Outline D D1 A A2 A1 E1 E 1 e b L1 L Dimensions are in mm. Dim. A 100-pin PQFP 3.40 Max Dim. A1 Dim. A2 0.00 0.35 2.80 ±0.25 Dim. b 0.22 0.38 Dim. D 23.2 ±0.2 Dim. D1 20.0 ±0.2 Dim. a 0.65 Typ. Dim. E 17.2 ±0.2 Dim. E1 14.0 ±0.2 Dim. L 0.80 ±0.15 Dim. L1 1.60 Ref. MUSIC Semiconductors Agent or Distributor: MUSIC Semiconductors reserves the right to make changes to its products and specifications at any time in order to improve on performance, manufacturability, or reliability. Information furnished by MUSIC is believed to be accurate, but no responsibility is assumed by MUSIC Semiconductors for the use of said information, nor for any infringement of patents or of other third party rights which may result from said use. No license is granted by implication or otherwise under any patent or patent rights of any MUSIC company. ©Copyright 1999, MUSIC Semiconductors European Sales Office Asian Sales Office MUSIC Semiconductors MUSIC Semiconductors Special Export Processing Zone 1 P.O. Box 184 6470 ED Eygelshoven Carmelray Industrial Park The Netherlands Canlubang, Calamba, Laguna Tel: +31 45 546 2177 Philippines Fax: +31 45 546 3663 Tel: +63 49 549 1480 Fax: +63 49 549 1024 Sales Tel/Fax: +632 723 62 15 http://www.music-ic.com email: info@music-ic.com Rev. 0.8 Draft Worldwide Sales Headquarters MUSIC Semiconductors, Inc. 4633 Old Ironsides Drive • Suite #130 Santa Clara, California 95054 USA Tel: 408-330-7550 Fax: 408-330-7559 USA Only: 800/933-1550 Tech Support 888/226-6874 Product Info. 16