MU9C8338A

Advance Information MU9C8338A 10/100Mb Ethernet Filter Interface APPLICATION BENEFITS • • • • • • 10/100Mb Ethernet wire speed switching and bridging for remote access and wireless networks Glueless connection to MUSIC LANCAM and most 10/100Mb Ethernet chip sets Offloads all DA/SA processing and management functions from host processor Supports station lists from 256 up to 32K addresses Full support of Unicast, Multicast, and Broadcast frames Built-in generic processor port DISTINCTIVE CHARACTERISTICS • • • • • • • • • Industry-standard 10/100Mb MII port Supports station list up to 32K addresses Port ID and MAC Frame Reject signal based on DA search results Read search results from the Result port or CPU port Hardware support for Tag switching Optional automatic learning of new SAs Optional automatic Aging and Purging 144–pin LQFP packages 3.3 Volt operation with 5 Volt tolerant I/O 10/100 PHY MII REJECT FR_ERR TAG MUSIC MU9C8338A Processor Interface Processor 10/100 MAC MII and TAG Port Packet Parser Controller Result Port ASIC LANCAM Interface Registers MUSIC LANCAM Figure 1: System Application Diagram MUSIC Semiconductors, the MUSIC logo, and the phrase "MUSIC Semiconductors" are Registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of MUSIC Semiconductors. May 1, 2001 Rev. 0a MU9C8338A 10/100Mb Ethernet Filter Interface General Description GENERAL DESCRIPTION The MU9C8338A, when configured with the MUSIC Semiconductors MU9Cx480B family of LANCAMs provides a high performance, large capacity Ethernet address processing subsystem for use in Ethernet bridge, switch, or remote access products. The device is designed to work in single-port system supporting a 100Mb/s Ethernet port at wire speed. OPERATIONAL OVERVIEW Because of the flexibility of the MU9C8338A, the best way to approach the feature set of the device is to first look at a typical 10/100Mb Ethernet application. The MU9C8338A captures the Destination address (DA) and the Source address (SA) of an incoming Ethernet frame on the MII port. After checking for a frame error or collision, the DA is processed and the result (associated data, usually a port ID) is made available. The SA then is checked, and either learned if new, or aged if already in the list. for the MII port to relay the Tag ID to the system for systems that support Tag switching. When the DA is processed, the MU9C8338A first checks if the frame is Unicast, Multicast, or Broadcast. Unicast frames destined for the same collision domain (visible on the same switch port as it came in on) are rejected. If the DA is found in the CAM database, the port ID associated with it is stored in the Result register. Multicast and Broadcast frames may also be processed by the system if the MU9C8338A is configured to do so. When Multicast is enabled, a default action is configured which causes frames with unknown group addresses to be processed correctly. Once processing completes, the Result register is accessed through the Result port or Processor port. Provided the frame length is correct, and no errors are detected, the SA is processed. If the SA exists in the CAM database, the time stamp and Port ID are updated. If the SA is not found in the CAM database, the address is learned automatically, along with its Port ID and the current time stamp information. Address processing always has priority over management routines, such as purging aged entries, inserting permanent entries, deleting entries, or reading from the CAM database. Typical MU9C8338A Application The MU9C8338A plays an integral role in the example of an Ethernet bridge system, shown in Figure 1. This system can handle up to 32,768 addresses on a bidirectional 100Mb Ethernet port by utilizing the MU9C8338A device and four LANCAMs connected as shown in Figure 1. The MII bus is "tapped" to collect packet data as it passes from the Ethernet PHY to the MAC. That data is processed automatically by the MU9C8338A/LANCAM combination. The MU9C8338A transfers the DA and SA to the CAMs for comparison. The results of MU9C8338A/LANCAM data processing are available through the Result bus or through the Processor bus. In addition to the Result bus, there is a serial Tag port 2 Rev. 0a Pin Descriptions MU9C8338A 10/100Mb Ethernet Filter Interface PIN DESCRIPTIONS Note: All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW. Inputs should never be left floating. Refer to the Electrical Characteristics section for more information. GND /RESET INCR VDD / INTR PROC_RDY /PCS /PCSS /WRITE A6 A7 GND 126 120 144 138 132 114 VDD RP0 RP1 RP2 RP3 GND RP4 RP5 RP6 VDD RP7 RP8 RP9 RP10 RP11 RP12 GND RP13 RP14 RP15 RP_DV VDD NC SC_ENB TST_HLD GND TST_HLD2 NC VDD RP_NXT RP_SEL GND NC NC NC GND 1 D12 D13 D14 GND 108 A0 A1 A2 VDD A3 A4 A5 D0 D1 D2 D3 D4 D5 VDD D6 D7 D8 D9 D10 D11 6 102 12 96 18 90 24 84 30 78 42 48 54 60 66 MII Interface Note: The MII interface does not know if the system PHY is operating in Full Duplex, Half Duplex or Loopback mode. Therefore, in applications that use Half Duplex or Loopback mode, care must be taken to ensure that unnecessary MII frames are not placed on the interface. It is recommended that only valid Receive Frames are allowed to be sent to the MU9C8338A. RXD[3:0] (Receive Data, Input, TTL) RX_ER (Receive Error, Input, TTL) RXD[3:0] is the 4-bit MII Receive Data nibble (see Timing Diagrams: Timing Data for RXD, RX_DV, and RX_ER). RX_DV (Receive Data Valid, Input, TTL) Data Valid is on RX_DV; RX_DV is asserted by the PHY at the beginning of the first nibble of the data frame and deasserted at the end of the last nibble of the frame. It indicates that the data is synchronous to RX_CLK and is itself synchronous to the clock (see Timing Diagrams: Timing Data for RXD, RX_DV, and RX_ER). Rev. 0a VDD REJ FRX_ER TP_SD TP_DV GND NC NC NC NC NC NC NC NC NC NC NC GND RXD3 RXD2 RXD1 RXD0 VDD RX_DV RX_CLK RX_ER COL CRS GND TDO GND TDI TMS TCK /TRST VDD Figure 2: Pinout RX_ER indicates a data symbol error in 100Mb/s mode or any other error that the PHY can detect, even if the MAC is not capable of detecting that error (see Timing Diagrams: Timing Data for RXD, RX_DV, and RX_ER). RX_CLK (Receive Clock, Input, TTL) RX_CLK is the receive clock recovered from the data by the PHY. It is equal to 25MHz in 100Base-X mode or 2.5MHz in 10Base-X mode. CRS (Carrier Sense, Input, TTL) Carrier sense CRS indicates that the medium is active (non-idle) and remains asserted during a collision. For Rx or Tx: CRS is HIGH in 10/100Base-X half-duplex mode; for Rx it is HIGH in repeater, full-duplex, and loopback modes. CRS is not synchronized to RX_CLK. 3 72 36 VDD D15 NC /RESET_LC /W /E /CM /EC GND /MI /FI VDD DQ0 DQ1 GND DQ2 DQ3 DQ4 DQ5 VDD DQ6 NC DQ7 DQ8 DQ9 DQ10 GND DQ11 DQ12 DQ13 NC DQ14 DQ15 GND SYSCLK NC MU9C8338A 10/100Mb Ethernet Filter Interface Pin Descriptions COL (Collision, Input, TTL) RP[15:0] (Result Port Data, Output, Tri-state, TTL) Collision detect COL is asserted by the PHY upon detection of a collision on the medium and remains asserted as long as the collision persists. It is HIGH in half-duplex modes and remains HIGH for 1 microsecond following the end of transmission; it is LOW in full-duplex mode. It is asserted in response to signal_quality_error message from the PMA in 10Base-X Heartbeat mode. The Result Port Data carries the results of recently processed packets detected on the MII port. See Table 1 for details of the Result Port Data bit descriptions. These are identical to the Result Data register bits. RP_DV (Result Port Data Valid, Output TTL) The Result Port Data Valid indicates that the RP port carries valid packet data. As long as there is valid packet data, RP_DV will stay HIGH. RP_NXT (Result Port Next Data, Input, TTL) Tag Port Interface REJ (Reject, Output, TTL) REJ is the reject packet command issued by the MU9C8338A. REJ is driven HIGH to reject a data frame, and can be detected by and responded to by the MAC device from 2 bit times after SFD to 512 bit times (64 byte times) after SFD. The REJ signal can be made active LOW by setting Bit 0 in the SSCFG register. (See Timing Diagrams: REJ Timing Data. FRX_ER (Frame Error, Output, TTL) The Result Port Next pin brings the next result to the RP bus if RP_SEL is asserted. If there are no additional results available, the RP_DV will drop LOW after the time interval specified in the Result Port Timing specification. RP_SEL (Result Port Select, Input, TTL) The Forced Receive Error pins provide the logical OR of the RX_ER and REJ lines for the MII port (see Timing Diagrams: Timing Data for FRX_ER in Relation to REJ and RX_ER). TP_SD (Tag Port Data, Output, TTL) The Result Port Select pin controls RP[15:0] and RP_NXT. RP_NXT and RP_SEL are connected by a logical AND. Therefore, RP_SEL must be HIGH in order for RP_NXT to bring the next result to the RP bus. RP_SEL can stay continuously HIGH as long as there is valid packet data, RP_DV will stay HIGH. Table 1: Result Port Bit Descriptions Bit(s) 15:10 9:8 7 6:1 0 Description 6-Bit Source Port ID Packet Type: Broadcast = 00, Multicast = 01, Unicast = 10 Match Found 6-Bit (if CAM Match Found) Destination Port ID (If Match Found) Destination Port = Source Port The Tag Port Serial Data pin carries the destination Port ID to external circuitry as soon as it is collected from the CAM (see Timing Diagrams: Timing Data for Tag Ports TP_DV and TP_SD). TP_DV (Tag Port Data Valid, Output, TTL) The Tag Port Data Valid pin is driven HIGH for as long as unread data exists for the Destination Port ID. Pin TP_SD carries the Destination Port ID (6 bits) to external circuitry as soon as it is collected from the CAM (see Timing Diagrams: Timing Data for Tag Ports TP_DV and TP_SD). Control Interfaces See Timing Diagrams: Timing Data for Control Interfaces. SYSCLK (System Clock, Input, TTL) Result Port Interface See Timing Diagrams: Timing Data for Result Port Interface. Table 1 shows the Result Port bit descriptions. Note: Although the result data register can also be read through the processor port, it is important to note that the means of retrieving the data must be unique. Therefore, if the user is not using the Result Port Interface, but is reading result data through the processor port, RP_NXT and RP_SEL should be pulled low. This ensures that all result data remains in the Result Data register until read through the processor port. RP_NXT and RP_SEL should be pulled low to 0 volts through a pull-down resistor (typically 10k ohms). CLK is the user-supplied system clock for synchronous chip operation; its frequency must be 25-50 MHz with duty cycle between 45 to 55 percent. /RESET (Reset, Input, TTL) When system Reset is taken LOW, all internal state-machines are reset to their initial state and any data is cleared. All registers are returned to default values. /RESET is synchronous and should be held LOW for a minimum of two SYSCLK cycles. The user must set the LANCAM Segment Control register after asserting /RESET. 4 Rev. 0a Pin Descriptions INCR (Increment Time Stamp Counters, Input, TTL) MU9C8338A 10/100Mb Ethernet Filter Interface /WRITE (Processor Port Read/Write, Input, TTL) INCR is a user command to invoke the built-in purge routine. Both STCURR and STPURG 8-bit counters are advanced one count on the rising edge of INCR, and the time stamp stored with each LANCAM entry is compared with STPURG. Matching entries subsequently are purged or deleted. This pin must be configured, if it is required, by setting bit 2 and bit 3 in the System Target (STARG) register. INCR must be held HIGH for a minimum of one SYSCLK cycle. Consecutive assertions of INCR must be a minimum of 8 SYSCLK cycles apart. Each counter can be incremented individually through the Processor Port. (see Operational Characteristics: STARG System Target Register Mapping). Read/Write determines the direction of data flow into or out of the MU9C8338A host processor interface. If /WRITE is LOW, the data is written into the register selected by A[7:0] and /PCS or /PCSS; if HIGH, the data is read from the register selected by A[7:0] and /PCS or /PCSS. A[7:0] (Processor Port Address, Input, TTL) Processor Address bus A[7:0] selects the MU9C8338A register accessed by the host processor. D[15:0] (Processor Port Data, Input/Output, Tri-state, TTL) Host Processor Interface The Host Processor interface is asynchronous to the System Clock. This interface is controlled by the /PCS or /PCSS (whichever is appropriate) and PROC_RDY signals, which form the handshaking between the processor and the MU9C8338A. This allows the end system to use a processor that runs at a different clock speed than the clock required by the MU9C8338A. (see Timing Diagrams: Timing Data for Host Processor Interface). /PCS (Processor Port Chip Select, Input, TTL) Processor Data bus D[15:0] is the tri-state processor data bus for the MU9C8338A. PROC_RDY (Processor Port Ready, Output, Tri-state, TTL) When reading from or writing to any MU9C8338A internal register, the PROC_RDY tri-state output goes LOW on the falling edge of /PCS or /PCSS. If it is a read cycle, PROC_RDY goes HIGH on the rising edge of SYSCLK once data is available. If it is a write cycle, PROC_RDY goes HIGH on the rising edge of SYSCLK when the internal register is ready to accept data. /INTR (Processor Interrupt, Output, TTL) Processor Chip Select is taken LOW by the host processor to gain access to the MU9C8338A Port or Chip registers. /PCSS (Processor Port Chip Select System, Input, TTL) Processor Chip Select System is taken LOW by the host processor to gain access to the MU9C8338A System registers or to access the LANCAM. /INTR goes LOW to signal that one of the two configurable interrupt conditions have been satisfied. The two separate conditions are configured by setting bits in the appropriate register. /INTR returns HIGH when the appropriate register is read. See Table 2 for details of which interrupt conditions are possible and which register must be read to reset the /INTR pin to HIGH. Table 2: /INTR Settings Register Required to To clear /INTR, Read Select Interrupt Condition PTARG Interrupt Condition RSTAT. Please note that /INTR will only return The MII port has parsed an incoming packet. The DA lookup HIGH when all possible result data has been read. has been performed and the result data is available to be read from RDAT register. SSTAT. Please note that /INTR will only return HIGH when the LANCAM has become not full. Therefore, after the SSTAT register read has confirmed the status of the interrupt condition, an entry should be removed from the LANCAM by using the PURGE sequence. The /FF output from the LANCAM(s) has indicated that the LANCAM is full. When reading the SSTAT register, a full condition is indicated by bit 0 = 0. STARG Rev. 0a 5 MU9C8338A 10/100Mb Ethernet Filter Interface Pin Descriptions /FI (LANCAM Bus Full Flag, Input, TTL) LANCAM Interface See Timing Diagrams: Timing Data for LANCAM Interface. DQ[15:0] (LANCAM Bus, Input/Output, Tri-state, TTL) DQ[15: 0] tri-state 16- bit bus transfers data or instructions between the MU9C8338A and the LANCAM. When no data or instructions are present on the bus, the bus goes HIGH-Z. /E (LANCAM Bus Enable, Output, Tri-state, TTL) The /FI LANCAM Full flag input is used to indicate to the MU9C8338A the condition of the LANCAM Full flag. The /FF output from the LANCAM should be connected to this pin. If more than one LANCAM is used, /FI should be connected to the /FF of the last device in the daisy chain. /RESET_LC (Reset LANCAM, Output, TTL) The /E chip enable is taken LOW to initiate LANCAM activity. On LANCAM read cycles, /E is taken HIGH after the MU9C8338A registers the data. /W (LANCAM Bus Write, Output, Tri-state, TTL) /RESET_LC is LOW whenever /RESET is LOW. It is taken HIGH only by writing to bit 0 in the System Dynamic Configuration (SDCFG) register. See SDCFG register information. Test SC_ENB (Scan Enable) The MU9C8338A outputs /W (read/write select) to control the direction of data flow between the MU9C8338A and the LANCAM. If /W is LOW at the falling edge of /E, the MU9C8338A outputs data on the DQ[15:0] bus for the LANCAM as input. When /W is HIGH at the falling edge of /E, the LANCAM outputs data on the DQ[15:0] bus to the MU9C8338A as input. /CM (LANCAM Bus Command Mode, Output, Tri-state, TTL) Enables scan chain for testing. Pin may be left unconnected or tied to GND for normal operation TST_HLD, TST_HLD2 (Test Hold) Enables test mechanism. Pins may be left unconnected or tied to GND for normal operation. JTAG Note: Please refer to IEEE Standard 1149.1 for information on using the mandatory JTAG functions. The optional HIGH-Z function is implemented and may be activated by writing 0011 to the JTAG Instruction register. /TRST (JTAG Reset, Input) The MU9C8338A outputs /CM Data/Command Select to control whether the LANCAM interprets the DQ[15:0] bus contents as command information or data. If both /CM and /W are LOW at the falling edge of /E, the MU9C8338A outputs an instruction for the LANCAM to execute or a value for one of the LANCAM configuration registers. If /CM is LOW while /W is HIGH, then the LANCAM will output data from one of its configuration registers to the MU9C8338A. If /CM is HIGH while /W is LOW, the MU9C8338A will output data for the LANCAM to place in one of its data registers or memory. If /CM is HIGH while /W is HIGH, the LANCAM outputs data from one of its data registers or memory to the MU9C8338A. /EC (LANCAM Bus Enable Chain, Output, Tri-state, TTL) The /TRST is the Test Reset pin. It is internally pulled up with a 3k minimum resistor. It must be tied to /RESET or tied LOW when the JTAG port is not used. TMS (JTAG Test Mode Select, Input) The TMS input is the Test Mode Select input. This pin is internally pulled up with a 3k minimum resistor. TCK (JTAG Test Clock, Input) The TCK input is the Test Clock input. It can be tied at a valid logic level 1 when not in use. This pin is internally pulled up with a 3k minimum resistor. TDI (JTAG Test Data Input, Input) The Daisy Chain Enable signal performs two functions. The /EC signal enables the LANCAMs /MF output to show the results of a comparison. If /EC is LOW at the falling edge of /E in a cycle, the /MF flag output is enabled; otherwise, /MF is held HIGH. The /EC signal also enables the /MF-/MI daisy chain that serves to select the device with the highest-priority match in a string of LANCAMs. /MI (LANCAM Bus Match Flag, Input, TTL) The TDI input is the Test Data input. This pin is internally pulled up with a 3k minimum resistor. TDO (JTAG Test Data Output, Output) The TDO output is the Test Data output. Power and Ground VDD, GND (Positive Power Supply, Ground) The /MI LANCAM Match flag input is used to indicate to the MU9C8338A the conditions of the LANCAM Match flag. The /MF output from the LANCAM should be connected to this pin. If more than one LANCAM is used, /MI should be connected to the /MF pin of the last LANCAM in the daisy chain. 6 These pins are the power supply connections to the MU9C8338A. VDD must meet the voltage supply requirements in the Operating Conditions section relative to the GND pins, which are at 0 Volts (system reference potential), for correct operation of the device. Rev. 0a Functional Description MU9C8338A 10/100Mb Ethernet Filter Interface FUNCTIONAL DESCRIPTION Internal Functions MU9C8338A internal functions are shown in Figure 3. Before discussing the individual blocks, the underlying principles are presented. The network interface is monitored for network and data symbol errors. Receive data [RXD] is clocked into a register using the 25MHz recovered clock for 100Base-X or 2.5MHz clock for 10Base-X. The Preamble and Start Frame delimiter (SFD) are scanned to locate the Destination address (DA) and the Source address (SA). The MU9C8338A schedules communication with the host processor and the CAM through an arbitration process. Once the system is initialized and configured, highest-priority is given to network traffic. The LANCTL block generates the command cycles and operational codes to complete CPU-requested actions and network-generated requests. The CPU must initialize the CAM, write the permanent station list, and initiate other housekeeping functions. Network traffic initiates DA filtering, SA learning, and time stamp updates. All state-machines required for real-time operations are implemented in the ASIC hardware; the host CPU runs the non-time-critical initialization routine. Information on the LANCAM operation and instruction set can be found in the appropriate LANCAM data sheet for each device. LANCAM Bus FRX_ER REJ TP_SD TP_DV Tag Port Interface LANCAM Interface RX_DV RX_ER RXD[3:0] RX_CLK CRS COL MII Interface MAC Receiver LANCTL Configuration, Control and Status Registers JTAG Controller TCK TMS TDI TDO /TRST CPU Bus Host CPU Interface Result Bus Result Bus Interface FIFO Figure 3: Functional Block Diagram Rev. 0a 7 MU9C8338A 10/100Mb Ethernet Filter Interface Functional Description Destination Address Processing Once configured, the MU9C8338A will extract the DA from the frames that are received through the MII port. An automatic address processing function is subsequently triggered. Once the DA processing function is triggered, the frame is monitored to detect whether it is a broadcast, multicast, or unicast frame and the appropriate actions are taken. DA processing consists of the following actions: • • • Packets are characterized as Broadcast, Multicast, or Unicast types. Unicast packets initiate a search of the CAM for existing entries. Multicast and Broadcast packets will also initiate a search if the PCFG_EXT register is appropriately configured. If a DA match is found, the Port ID read from the CAM is compared to the Source Port ID. If the Source Port ID and Destination Port ID match, the frame is rejected. If the Port IDs are different, the Tag information is made available for MACs that support Tag switching, through the Tag port. If a DA match is not found and the packet characterized as Multicast or Broadcast, a default action is carried out if Multicast Processing is enabled. This allows Multicast and Broadcast packets to be processed appropriately and is configured in the PCFG_EXT register. If the MU9C8338A rejects the frame, it asserts the Reject output pin (REJ) and forces the MII RX_ER output (FRX_ER) HIGH for the MII Port. This causes the MAC to discard the frame. Once the DA processing function is complete, the MU9C8338A stores the result. This result indicates the characterization of the processed frame. (Broadcast, Multicast, or Unicast) and the Source Port ID. Additionally, if a unicast frame was processed, the result of the search and the port ID of the DA is also stored. Finally, the detail of whether the Destination port and the Source port are identical is also stored. The result of DA processing may be read in two ways. 1. An interrupt may be sent to the host processor indicating that there is a result available. The host processor would read the result from an internal Result Data register. 2. External circuitry can monitor the status of the Result Port Data valid (RP_DV) output pin. This output indicates that there is a result available in the internal register which can be read through the Result port. The external circuitry can read the data by asserting the Result Port Select (RP_SEL) pin. Assertion of Result Port Next (RP_NXT) clears the value and advances the next entry if there is one available. Source Address Processing • Once configured, the MU9C8338A also will perform SA processing functions after the address information has been extracted from a received frame. The SA of each arriving frame is stored by the MU9C8338A for further processing, along with the port ID and the current time stamp. Note that at start-up, permanent addresses and their Port ID are loaded into the LANCAM through the CPU port; as message traffic proceeds, new addresses are learned and added to the LANCAM database, and aged addresses are purged. SA processing consists of the following actions: • The SA field is collected and temporarily stored. Note the SA cannot be a Broadcast or Multicast address by definition. When the complete packet has arrived, the CRC field is checked and the length of the packet is checked. Any errors result in no further SA processing. If the packet did not contain any errors, (or the CRC check facility is disabled), the SA field is compared with the address fields that are stored in the LANCAM. If a match is found, the Port ID and time stamp for that entry are updated. If no match is found, the SA is added to the CAM, along with the current time stamp and the Port ID assigned to that particular Source port. • • • • • • • 8 Rev. 0a Functional Description MU9C8338A 10/100Mb Ethernet Filter Interface MAC Address Storage When the MU9C8338A performs an SA processing function, it automatically extracts the MAC address from the packet. The database is searched and the MAC address is added to the LANCAM database if necessary. Similarly, when a DA processing function is performed, the MU9C8338A automatically searches the database for the extracted DA MAC address. It is important that the user is aware of the byte ordering of the 48-bit MAC address when it is stored in the LANCAM database. This is because the user must byte-order MAC addresses identically when a database entry is to be manually added or deleted. Similarly, if the user wishes to read out a MAC address, they should also be aware of the byte ordering when the relevant data registers are read. Throughout this data sheet MAC addresses are shown as bit 47 being the most significant bit, which is placed on the left. Similarly, bit 0 is shown as the least significant bit and placed on the right. Using this notation, the Individual/Group (I/G) bit subfield would be shown as bit 40. This bit would be the first bit of an address transmitted onto the serial network and also the first bit received. The IEEE 802.3 refers to the I/G bit subfield as bit 0. If the bit is set to 1, it indicates that the address is a group address. Conversely, if the bit is set to 0, it indicates it is an individual address. Figure 4 shows a typical 48-bit MAC address used in Ethernet or IEEE 802.3 networks. MAC Address 47 02 40 : 39 60 32 : 31 8C 24 : 23 12 16 15 : 34 08 : 07 56 00 If the user wishes to use the built-in routines to manually add, delete, or read MAC addresses from the database, the System CAM Word registers (SCDW) are used as shown in Figure 5. It shows how the MAC address, used as an example in Figure 4, would be transferred using the SCDW registers. If the user intended to delete the MAC address, the SCDW registers would be written as shown in item 1 and the SDO_DELETE routine would be invoked. If the user intended to add the address manually, the SCDW registers would be written as shown in item 2 and the SDO_ADD routine would be invoked. Finally, if the user intended to read an entry, the SDO_READ routine would be invoked and the address would be read from the SCDW registers as shown in item 3. The built-in routines are explained more fully later in this document. 1 SCDW3 SDO_DELETE not used SCDW2 6002 SCDW1 128C SCDW0 5634 2 SCDW3 SDO_ADD 6002 SCDW2 128C SCDW1 5634 SCDW0 assoc. data 3 SCDW3 SDO_READ 6002 SCDW2 128C SCDW1 5634 SCDW0 assoc. data Figure 5: SCDW Register Order Functional Blocks The building blocks that make up the MU9C8338A are shown in Figure 3, and their functions are described by the following. MII Interface (MII Port) 0000 0010 IEEE bit 0 I/G bit LANCAM Database Entry seg 3 6002 seg 2 128C seg 1 5634 seg 0 assoc. data The incoming asynchronous receive data is registered for subsequent processing. MU9C8338A internal processing is synchronous with the system clock. Tag Port Interface (Tag Port) Figure 4: MAC Address Byte Order If the MAC address shown in Figure 4 is added to the database by the MU9C8338A, it is stored as follows: • • • • Segment 3 = 6002h Segment 2 = 128Ch Segment 1 = 5634h Segment 0 = Associated data (permanent bit, time stamp and port ID) Rejection of a packet is indicated by the assertion of REJ. The FRX_ER line, which otherwise reflects the state of the RX_ER pin, is forced to HIGH at the same time. If the DA is matched in the LANCAM, the TP_DV pin is asserted and the destination port ID, high-order bit first, is clocked out through the TP_SD pin transitioning after the RX_CLK rising edge. MAC Receiver This block performs tasks that are a subset of the Ethernet MAC. It detects errors, (CRS, COL, RX_ER, and Runt Frame), determines the start of frame, parses addresses, computes the CRC for 10Base-X packets, and formats the 4-bit nibbles into 48-bit SA and DA registers. 9 Rev. 0a MU9C8338A 10/100Mb Ethernet Filter Interface Functional Description LANCAM Sequencer Aging and Purging The sequencer is a state machine that generates the control signals required for CAM read and write cycles, and multiplexes appropriate data and operational codes to LANCAM data lines. The sequencer operations are: • • • • • • • Execute LANCAM cycles for CPU port DA processing SA processing Purging of aged entries Add Permanent Entries to LANCAM database Delete Entries from LANCAM database Read Entries from the LANCAM database. FIFO and Result Port Time stamps are added automatically to the LANCAM entries by the MU9C8338A. Two counters are provided to store the current and purge time stamps. The Current Time Stamp is the 8-bit value that automatically is added or updated when a SA processing function is completed. The Purge Time stamp is the 8-bit value that is compared with the 8-bit time stamps stored with the LANCAM entries during purges. The initial value of the counters are STPURG = 01H and STCURR = 00H. The counters may be incremented individually through the CPU commands. Either the CPU or the external INCR pin can increment both counters simultaneously. Whenever STPURG is incremented, a purge operation is initiated. The counters roll-over so the times should be thought of as slots to be used and reused in a round-robin fashion. The existence of two counters (time stamps) allows the data-aging rate to be varied according to network traffic density. When the difference between the counters is large (default), the address data is purged less frequently; shrinking the counter difference causes the data to age sooner. Incoming SAs are time stamped or updated with the current value of STCURR. Older entries time stamped with the same value as STPURG are purged upon the increment of STPURG. The permanent address database built using the Add routine is not affected by time stamps. The data age gap is effectively the length of time an entry will exist in the LANCAM database if it is not updated. This gap is the difference between the STCURR and STPURG counter. When network traffic is low, STCURR may be increased in order to increase the length of time an entry will exist. When network traffic is high, STPURG may be increased in order to decrease the length of time an entry will exist. When STPURG is incremented older entries are also purged from the database if their time stamp matches STPURG. STCURR and STPURG may be incremented simultaneously to keep the data age gap constant and to purge the older entries from the database. To maintain "current" time, STCURR is advanced in any one of the three ways: 1. The CPU issues an increment STCURR command. Only the STCURR counter is increased. 2. The CPU issues an increment STCURR and STPURG command. Both counters are increased simultaneously. 3. The INCR pin is asserted. Both counters are increased simultaneously. To maintain "purge" time and to purge aged CAM entries, STPURG is advanced in any one of the following three ways: 10 Rev. 0a When the DA sequence is executed, the result is stored in a FIFO for later collection by either the CPU over the Processor Bus from the Result register, or by external hardware attached to the Result port. Initialization At power-up or after a hardware reset, the host processor should download the LANCAM configuration and register contents to enable the LANCAM to operate as required. The LANCAM initialization and configuration that is downloaded by the CPU should do the following: The individual Page Address registers of each LANCAM in the LANCAM chain should be set with appropriate values. The Foreground Register set should be set to allow normal DA and SA filtering. This involves setting the Control, Segment Control, and Mask registers to suit. The Background Register set should be set to allow the background management tasks to be preformed. This involves setting the Control, Segment Control, and Mask registers to suit. The LANCAM should be configured to store 48-bit MAC addresses in segments 3–1 and the associated data in segment 0. The allocation of bits in the 16-bit associated data segment is specified in the description of the SCDW0 Association Data register. Permanent Station Addresses Using the Add Entry routine, the nonvolatile station list can be added to the LANCAM by the host processor. The Associated Data bit 15 is set to 1, to indicate a permanent entry. Permanent entries are removed only with the Delete Entry routine. Management The Delete Entry and Read Entry routines are available for database maintenance and housekeeping. Although permanent addresses cannot be purged, they can be deleted using the management Delete Entry routine. Functional Description MU9C8338A 10/100Mb Ethernet Filter Interface 1. The CPU issues an increment STPURG command. Only the STPURG counter is increased. 2. The CPU issues an increment STCURR and STPURG command. Both counters are increased simultaneously. 3. The INCR pin is asserted. Both counters are increased simultaneously. If the STPURG value was incremented, the MU9C8338A initiates a purge operation using the new STPURG value. STPURG should never be incremented to equal STCURR. The time stamping of LANCAM entries and the procedure required to initiate a purge is explained as follows: 1. Incoming SAs to be learned are associated with the most recent STCURR value. The time stamps of each SA already in the CAM database is updated to STCURR, each time a packet with that SA is processed. 2. STPURG and STCURR are advanced as described earlier to purge entries that have the same time stamp value as STCURR. Following is an example, beginning with the defaults, initially, STCURR = 00H and STPURG = 01H. As packets arrive, learned or refreshed, SAs are labeled with STCURR = 00H. (At that moment STPURG = 01H). Increment, either hardware or software initiated, results in STCURR = 01H and STPURG=02H. A purge operation is initiated that will eliminate all CAM entries with time stamp = 02H. The oldest entries (SAs) that have not been updated in 255 increment times are purged automatically without further involvement. If the CAM Full flag is asserted, an interrupt (if configured) to the CPU is generated. Assume that STCURR = F0H, and STPURG = F1H. The CPU may initiate an increment STPURG operation so that older entries may be purged. This increases the value of STPURG to F2H. A purge operation is initiated that will eliminate all CAM entries with time stamp = F2H. The CPU should monitor the System Status register, and if the CAM is still full, the operation can be repeated until entries are purged and the CAM Full flag is de-asserted. Assume that STPURG was incremented 128 times. This would purge the oldest half of the time stamp values and thus, reduce the maximum age to half the previous 255. This can be accomplished without disturbing ongoing normal increment time stamp update operations. CRC and Other Data Integrity Checks For 10Base-X packets, a 32-bit cyclic redundancy check is calculated from the data frame (exclusive of the preamble and start frame delimiter) and compared to the frame check sequence (FCS). This check is only performed if the PCFG register is set accordingly to enable the facility. Also, according to the MII interface specifications, the RX_ER, CRS, and COL signals are monitored and error conditions are recognized. If any error is identified, the source address is not processed. This is intended to maintain the integrity of the LANCAM database. Rev. 0a 11 MU9C8338A 10/100Mb Ethernet Filter Interface Software Model SOFTWARE MODEL The MU9C8338A has three sets of internal registers: System, Chip, and Port. The System registers are accessed using the /PCSS input, and the Chip and Port registers are accessed using the /PCS input. System Registers One set of registers is available to address the MU9C8338A component and its attached LANCAMs as a single system. The application decodes one range of addresses to produce a Processor Chip Select System Table 3: System Registers Name SSTAT SSCFG SDCFG STARG SCDW0 SCDW1 SCDW2 SCDW3 STPURG STCURR SMXSADACYC SCSWB SCSWA SSAU SSAL SLCCS SDO_DELETE SDO_ADD SDO_READ SDO_INCTS SDO_INCPR SDO_INCTSPR SDO_SETADD R/W R R/W R/W R/W R/W R/W R/W R/W R R R/W R R R/W R/W W W W W W W W W Description System Status System Static Configuration System Dynamic Configuration System Targets CAM Data Word 0 CAM Data Word 1 CAM Data Word 2 CAM Data Word 3 Time Stamp to Purge Time Stamp Current Max SA/DA Cycle CAM Status Word B CAM Status Word A SA Update Op-Code SA Learn Op-Code LANCAM Control Signals Perform Delete Sequence Perform Add Sequence Perform Read Sequence Perform Increment STCURR Sequence Perform Increment STPURG Sequence Perform Increment STCURR & STPURG Sequence Perform SetAddr. Sequence signal (/PCSS). The lowest address in this application-defined address range, shown in Table 3, is referred to as SYSTEM_BASE. Address SYSTEM_BASE + 0H SYSTEM_BASE + 1H SYSTEM_BASE + 2H SYSTEM_BASE + 3H SYSTEM_BASE + 5H SYSTEM_BASE + 6H SYSTEM_BASE + 7H SYSTEM_BASE + 8H SYSTEM_BASE + 9H SYSTEM_BASE + AH SYSTEM_BASE + CH SYSTEM_BASE + DH SYSTEM_BASE + EH SYSTEM_BASE + 10H SYSTEM_BASE + 11H SYSTEM_BASE + 12H SYSTEM_BASE + 20H SYSTEM_BASE + 21H SYSTEM_BASE + 24H SYSTEM_BASE + 26H SYSTEM_BASE + 27H SYSTEM_BASE + 28H SYSTEM_BASE + 29H Default Settings N/A 0000H 0H 0H N/A N/A N/A N/A 01H 00H 20H N/A N/A 0368H 0334H 0FH N/A N/A N/A N/A N/A N/A N/A System Status Register The System Status register (SSTAT) provides a CPU visibility into the state of the LANCAM array. The /FF bit indicates the current state of the Full Flag output of the LANCAM array. The /MF bit indicates the Match Flag output of the LANCAM array. Table 4: SSTAT: System Status Register Mapping Name /FF /MF Bits 0 1 Description Full Flag from LANCAM array Match Flag from LANCAM array Table 5 shows a CAM_SPD setting for a 120 ns speed grade LANCAM component. 120 ns LANCAMs are no longer available and it is recommended that when using a 90 ns LANCAM, set SSCFG[3:1] to 000. This setting accommodates most applications and has the added benefit of using the least amount of power. Table 5: SSCFG: System Static Configuration Register Name CAM_SPD Bits 3:1 Description 000 = 120 ns (90 ns) 001 = 90 ns 010 = 70 ns 011 = RESERVED 100 = RESERVED 101 = RESERVED 110 = RESERVED 111 = RESERVED 0 = Active HIGH 1 = Active LOW System Static Configuration Register The System Static Configuration register (SSCFG) allows the CPU to configure the LANCAM array. These are set and forget values. The CAM_SPD sets the controller to match the speed grade of the LANCAM components attached. A 50MHz clock is assumed. The INV_REJ bit configures the REJ port to be active LOW instead of active HIGH. 12 INV_REJ 0 Rev. 0a Software Model MU9C8338A 10/100Mb Ethernet Filter Interface The System Dynamic Configuration Register System CAM Word Registers The System Dynamic Configuration Register (SDCFG) allows the CPU to control the MU9C8338A /RESET_LC output pin. This pin normally would be connected to the /RESET input of all the LANCAMs in a chain of LANCAMs. When the RST_CAM bit is logic 0 the /RESET_LC output is LOW and when the RST_CAM bit is logic 1 the /RESET_LC output is HIGH. Note that if a hardware reset is performed by taking the MU9C8338A /RESET input LOW, /RESET_LC is asserted LOW. However once /RESET has been taken HIGH, /RESET_LC remains LOW, holding the LANCAM(s) in the reset condition. The RST_CAM bit must be set to 1 to return /RESET_LC HIGH and hence allow the LANCAMs to operate normally. Table 6: SDCFG: System Dynamic Configuration Register Name RST_CAM Bits 0 Description 0: Reset 1: Normal Operation When using the series of built-in routines, the SCDW registers are used to transfer data. The bit mapping is different for each routine. Please refer to the appropriate mapping for the relevant routine. Also refer to section MAC Address Storage on page 9. Table 8: SCDW: Data Mapping Contents Name SCDW0 [15:0] SCDW1 [15:0] SCDW2 [15:0] SCDW3 [15:0] SDO_DELETE Sequence MAC_AD [15:0] MAC_AD [31:16] MAC_AD [47:32] Not used Other Routines Associated data MAC_AD [15:0] MAC_AD [31:16] MAC_AD [47:32] During the LANCAM initialization and configuration process, SCDW0 is used with SLCSS to configure the LANCAMs. When SCDW0 is used to transfer associated data, the bit mapping is as shown in Table 9. SCDW0 has an additional purpose that allows the associated data to be read after a DA processing function has completed. After every DA is processed, the associated data read from the LANCAM is placed in the SCDW0 register, Therefore, if the system software reads the SCDW0 register after a packet is processed, the Port ID, Timestamp, and permanent bit information may be found. Table 9: SCDW0: Associated Data Register Mapping Name Time_Stamp Port_ID Reserved Permanent Bits 7:0 13:8 14 15 System Target Register The System Target Register (STARG) allows the CPU to determine how events are to be handled. The INCR_PIN bits enable or disable to INCR hardware input. The EN_FF_INT bits enable or disable whether the LANCAM /FF output will produce an interrupt when the LANCAM is full. Table 7: STARG: System Target Register Mapping Name INCR_PIN Bits 3:2 Description 00: Disable INCR pin 01: RESERVED 10: RESERVED 11: Enable INCR pin 00: Disable /FI interrupt 01: RESERVED 10: Enable /FI interrupt 11: RESERVED EN_FF_INT 1:0 System Time Stamp Purge Register The System Time Stamp Purge register (STPURG) stores the purge time stamp value. It is a read-only register, but it may be incremented by writing an arbitrary value to the SDO_INCPR register. Table 10: STPURG: System Time Stamp Purge Register Mapping Name Purge Time Stamp Initial Value = 01H Location bits [7:0] Rev. 0a 13 MU9C8338A 10/100Mb Ethernet Filter Interface Software Model System Time Stamp Current Register System LANCAM Control Register The System Time Stamp Current register (STCURR) stores the current time stamp value. It is a read-only register, but it may be incremented by writing an arbitrary value to the SDO_INCTS register. Table 11: STCURR: System Time Stamp Current Register Mapping Name Current Time Stamp Initial Value=00H Location bits [7:0] System Maximum SA/DA Cycles Register This register establishes the number of clock cycles that DA and SA operations will take. This is based on the speed of the attached LANCAM components. Table 12 shows a CAM_SPD setting for a 120 ns speed grade LANCAM component. 120 ns LANCAMs are no longer available and it is recommended that when using a 90 ns LANCAM, set the register to 27H. This setting accommodates most applications and has the added benefit of using the least amount of power. Table 12: SMXSADACYC: System Maximum SA/DA Cycles Register Mapping Name CAM_SPD Bits 5:0 Description 27H = 120 ns (90 ns) 25H = 90 ns 20H = 70 ns others = RESERVED The System LANCAM Control register enables the host CPU to initialize and configure the LANCAMs. During normal system operation bit 4 should be set to zero to disable the LANCAM control bits. When the host CPU wishes to write to the LANCAM (at initialization) bit 4 is set to one while setting bits 3–0 to the values required for a LANCAM data or command cycle. The data or command to be transferred to the LANCAM should be loaded into the SCDW0 register prior to the cycle being initiated. Each LANCAM cycle is a four step process and is described as follows: 1. Load SCDW0 with 16-bit data or command. 2. Load SLCCS with cycle value to take /E HIGH. 3. Load SLCCS with cycle value to take /E LOW. 4. Load SLCCS with cycle value to take /E HIGH. For example a TCO CT command cycle would be SCDW0= 0200H, SLCCS = 19H, 11H, 19H. Table 15: SLCSS: System LANCAM Control Signal Register Mapping Name /EC /CM /W /E ENABLE Bits 0 1 2 3 4 Description Enable Chain Command Mode READ/WRITE Enable 0 => (Normal Operation) Disable Bits [3:0] 1 => Processor Port CAM access System Status Word Registers The Status Word registers store the 32-bit LANCAM status register value after the LANCAM entry read routine is performed. SCSWA stores the lower 16 bits of the status register and SCSWB stores the upper 16 bits. Table 13: SCSW: System Status Word Register Mapping Register SCSWA [15:0] SCSWB [15:0] LANCAM Status Register Bits 15:0 31:16 System Command Registers System SA Op-Code Registers The SA Op-Code registers store the LANCAM Op-Code values required when the MU9C8338A performs the automatic SA search routine. SSAU stores the code required to update an SA and SSAL stores the code required to learn an SA. These registers have the default values required to perform the routines described in Built-in Routines. Table 14: System Op-Code Register Mapping Register SSAU SSAL Bits 15:0 15:0 Default Op-Code 0368H, MOV_HM CR, MR1 0334H, MOV_NF CR, V The System Command registers allow the CPU to execute transactions applied to a LANCAM array. There are seven command registers and they have the prefix SDO. Each register is used to initiate a built-in routine that allows general LANCAM housekeeping tasks to be performed. The housekeeping sequence is initiated by writing any arbitrary value to the appropriate register. Descriptions of the routines performed when SDO_ADD, SDO_DELETE, SDO_READ, and SDO_SETADD are accessed as shown in Built-in Routines. SDO_INCTS, SDO_INCPR, and SDO_INCTSPR control the time stamp counters. SDO_INCPR and SDO_INCTSPR also cause the purge routine described in Built-in Routines to be initiated. The MU9C8338A may hold PROC_RDY inactive, if it is processing any high-priority DA and SA searches. The registers and their address values can be found in Table 3. 14 Rev. 0a Software Model MU9C8338A 10/100Mb Ethernet Filter Interface Chip Registers The system should decode one unique range of addresses to produce an individual chip select (/PCS) signal for the MU9C8338A component. The lowest address in this Table 16: Chip Registers Name CHIPROL CHIPVER RSTAT RDAT R/W R/W R R R Description Chip Role Chip Version Result Status Result Data Address CHIP_BASE + 1H CHIP_BASE + 2H CHIP_BASE + 3H CHIP_BASE + 4H Default 0H 03H N/A N/A application-defined address range is referred to as CHIP_BASE. Table 16 shows the Chip registers and their address values. Chip Role Register Result Status Register The Chip Role register stores the designation of the MU9C8338A. This register defaults to 0H. The register must always contain 0H. All other values are reserved. Table 17: CHIPROL: Chip Role Register Mapping Name CHIPROL Bits 2:0 Function Chip Description 0: Default All other values are Reserved The Result Status register is used to convey whether the Result Data register stores any valid result data. Reading this register resets the /INTR pin if it was asserted because of result data being processed (after all valid result data is read). Table 19: RSTAT: Result Status Register Mapping Name RDATA Bits 0 Description 1: Result Data available 0: No Result Data Chip Version Register The Chip Version register stores the version of the chip. The value of this read-only register will be incremented for each subsequent release. Table 18: CHIPVER: Chip Version Register Mapping Name CHIPVER Bits 4:0 Description Result Data Register The Result Data register stores the result of the automatic SA and DA processing. Table 20: RDAT: Result Data Register Mapping Name Source Port ID Bits 15:10 9:8 Description 6-bit Port ID 00: Broadcast 01: Multicast 10: Unicast 11: RESERVED 0: Match Not Found 1: Match Found 6-bit Port ID 1: Ports are the same 0: Ports are different Chip Version Packet Type Match Found 7 Destination Port ID Destination Port = Source Port 6:1 0 Rev. 0a 15 MU9C8338A 10/100Mb Ethernet Filter Interface Software Model Port Registers The MU9C8338A supports one port. This port is addressed as an offset to the CHIP_BASE for the Table 21: Port Registers Name PID PCFG PTARG PCFG_EXT R/W R/W R/W R/W R/W Description Port ID Configure Port Target Port Configure Port Extended MU9C8338A in which it is implemented. Table 21 shows the Port registers and their address values. Address CHIP_BASE + 40H CHIP_BASE + 41H CHIP_BASE + 42H CHIP_BASE + 44H Default 0H 0H 0H 0H Port ID Register Port Target Register The Port ID register stores the ID associated with the MII port. The 6-bit value is the value added to LANCAM entries when the SA search routine is performed. Table 22: PID: Port ID Register Mapping Name PORT_ID Bits 5:0 Description 6-Bit Port ID The Port Target register allows the operating conditions of the port to be set. Bits 3:0 are Reserved and should be set to 0H. Bits 5 and 4 determine what action is taken after the DA is extracted from a frame that was received on the MII port. Bits 7 and 6 determine what action is taken after the SA is extracted from a frame that was received on the MII port. Table 24: PTARG: Port Target Register Mapping Port Configure Register The Port Configure register enables or disables the 10Base-X CRC check facility. If the facility is enabled, 10Base-X packets found to have CRC errors will not have their Source address processed. If the facility is disabled, the Source address of 10Base-X packets are processed regardless of CRC errors, assuming the PTARG register is configured appropriately. This register only enables a CRC check for 10Base-X packets. The facility should be disabled (bit 1=0) for 100Base - X packets. Table 23: PCFG: Port Configure Register Mapping Name SA Bits 7:6 Description 00: SAs are ignored 01: SAs are processed 10: RESERVED 11: RESERVED 00: DAs are ignored 01: DAs are processed 10: DAs are processed and trigger a CPU interrupt 11: RESERVED Must be set to 0H. All other values: RESERVED DA 5:4 RESERVED Name RESERVED Enable CRC Check Bits 0 1 Description Write 0 0 = Disable (default) 1 = Enable 3:0 16 Rev. 0a Software Model MU9C8338A 10/100Mb Ethernet Filter Interface Port Configure Extended Register The Port Configure Extended register enables or disables Multicast Address processing. When DA processing is enabled in the PTARG register, the default is for Multicast and Broadcast frames to be ignored (no DA processing) thus causing them to be forwarded at all times. If the user wishes Multicast frames to be processed in the same way as Unicast frames, bit 1 should be set to 1. Bit 0 allows the user to set a default action for cases when Multicast processing is enabled but a matching Group Address was not found in the LANCAM. Additionally, Multicast frames may have their SAs processed by setting bit 2 to 1. The register also allows the user to enable a Permanent bit check that is performed during SA processing. When bit 3 is set to 0 (default), the SA processing function will use the command in the SSAU register when it finds a matching LANCAM entry. This typically updates the LANCAM entry by writing to it through a Mask register. In the case when the entry was added as a Permanent entry, the Port ID may be over-written during this operation. If the user wants Permanent entries to be untouched during SA learns; bit 3 should be set 1. This will cause the SA Learn built-in routine to check the permanent bit of the entry. If it shows the entry is a Permanent entry, it is not updated. Non-permanent entries will be updated as normal. Table 25: PCFG_EXT: Port Configure Extended Register Mapping Name Default_Multicast_Action Bits 0 Description If a DA processing function is performed on a Multicast group address, the packet is treated in the following way if the DA is not found in the LANCAM database: 0 = Drop. The REJ signal is asserted. This will inform external hardware (MAC) that the Multicast packet should be rejected (not forwarded). 1 = Pass. The REJ signal is not asserted. Bit 1 must be set; otherwise no Multicast DA processing function is performed. 0 = Disable. Multicast DAs are not processed 1 = Enable. Multicast DAs are processed in the same way as Unicast DAs 0 = Disable. SAs from a packet deemed to have a Multicast DA are not processed. 1 = Enable. SAs from a packet deemed to have a Multicast DA are processed. 0 = The permanent bit of a matching MAC address will not be checked during the SA Learn built-in routine. 1 = The SA Learn routine will read the associated data of the matching LANCAM entry to check the Permanent bit. If set, the SA will not be updated. If not set, the entry will be updated as normal. Reserved = Write as 0H. When reading, these bits will read as 0H DA_Processing_Enable 1 SA_Processing_Enable 2 Permanent_Check 3 RESERVED [15:4] Rev. 0a 17 MU9C8338A 10/100Mb Ethernet Filter Interface Software Model Built-In Routines The MU9C8338A contains a series of built-in routines that can be invoked or triggered by writing any arbitrary value to the appropriate System Command register. There are five built-in routines that can be used to perform general system management functions. Additionally there are two other routines that are used to alter the data-age gap between the two time stamp counters. Details of the built-in routines that are performed when invoked can be found in Applications: Built-In Routines. Details of the appropriate register for each routine can be found in Operational Characteristics: Software Model-System Registers. The following explains the steps that are required when using each of the seven routines: Increment the Current Time Stamp Initiate Set Address Sequence 1. Write the desired address of the CAM entry to be read into SCDW0. 2. Initiate the set address sequence by writing any value to the SDO_SETADD register. Note: This sequence should be initiated prior to the read entry sequence being initiated in order to specify the address that should be read. Initiate Read Entry Sequence Initiates the STCURR increment sequence by writing any arbitrary value to SDO_INCTS. Increment the Purge Time Stamp The Read Entry Sequence should only be used for diagnostic purposes when the MU9C8338A is not processing Source or Destination addresses. Therefore, if the user must read entries while packets are being processed, the SA and DA processing functions should be disabled prior to invoking the sequence. Once the entry has been read, the SA and DA processing functions should be enabled to return the MU9C8338A to normal. 1. Write the Page Address to the CAM device to be read into SCDW0. This should match the value that was configured during any CAM configuration routine. 2. Initiate the read entry sequence by writing any value to the SDO_READ register. 3. The specified entry can be read from SCDW3, 2, and 1 and the associated data can be read from SCDW0. Bits 47–32 should be read from SCDW 3, bits 31–16 from SCDW2, and bits 15–0 from SCDW1. 4. The CAM Status Register bits 31–16 associated with the entry can be read from the System CAM Status Word B (SCSWB) register. 5. The CAM Status Register bits 15–0 associated with the entry can be read from the System CAM Status Word A (SCSWA) register. Note: This sequence should be initiated in conjunction with the set address sequence in order to specify the address that should be read. If successive entries are to be read, SDO_SETADD is used only once as the CAM Address register will increment automatically. Initiates the STPURG increment sequence by writing any arbitrary value to SDO_INCPR. Increment the Current Time Stamp and Purge Time Stamp Initiates the STCURR and STPURG increment sequence by writing any arbitrary value to SDO_INCTSPR. Initiate Delete Sequence 1. Write the address to be deleted into System Command Data Word (SCDW) 2, 1, and 0. Bits 47–32 should be written into SCDW 2, bits 31–16 into SCDW1, and bits 15–0 into SCDW0. 2. Initiate the delete sequence by writing any value to the SDO_DELETE register. Initiate Add Sequence 1. Write the address to be added into System Command Data Word (SCDW) 3, 2, and 1. Bits 47–32 should be written into SCDW 3, bits 31–16 into SCDW2, and bits 15–0 into SCDW1. 2. Write the associated data for this entry into SCDW0. The port ID should be set in bits 13–8 and bit 15 should be set HIGH if the entry is to be permanent. 3. Initiate the add sequence by writing any value to the SDO_ADD register. 18 Rev. 0a Applications MU9C8338A 10/100Mb Ethernet Filter Interface APPLICATIONS Cascading of LANCAMs The MUSIC MU9Cx480B LANCAM family can be vertically cascaded to allow long station lists to be implemented. The MU9C8338A LANCAM interface timing allows up to four LANCAMs to be cascaded as shown in Figure 6. When LANCAMs are cascaded in this way, the system Full and Match flags are connected to the MU9C8338A /FI and /MI inputs respectively. When cascading LANCAMs, a match flag ripple delay is introduced. Care must be taken to ensure that the tMIVKH setup time is satisfied in multiple LANCAM designs. Please refer to the LANCAM B Family Data Sheet for a comprehensive description of the device and how to calculate the ripple delay. DQ[15:0] /MI Vdd /E /W /CM /EC /RESET /FI Gnd CAM 0 /FF /MF DQ[15:0] /MI /E /W /CM /EC /RESET /FI CAM 1 /FF /MF DQ[15:0] /MI /E /W /CM /EC /RESET /FI CAM 2 /FF /MF DQ[15:0] /MI /E /W /CM /EC /RESET /FI CAM 3 /FF System Full Flag /MF System Match Flag Figure 6: LANCAM Cascading Rev. 0a 19 MU9C8338A 10/100Mb Ethernet Filter Interface Applications Built-In Routines The MU9C8338A contains built-in LANCAM routines that perform all the necessary LANCAM operations. The DA and SA search routines are performed automatically by the device in order to provide the search result and update the address table. The other routines are invoked as described in Operational Characteristics: Built-in Routines. Table 26: Destination Address Search Routine Line 1 2 3 4 5 /CM H H H H H /W L L L L H /E Cycle Short Short Short Long Long /EC H H H L H Mnemonic DQ(15:0) xxxxH ddddH ddddH ddddH ddddH Description Dummy write to Segment 0 Write 1st 16 bits to Segment 1 Write 2nd 16 bits to Segment 2 Write 3rd 16 bits to Segment 3 and compare Read Associated Data, FFFFH is no match Notes: aaaaH = CAM Address value (Hexadecimal) ddddH = Data value (Hexadecimal) ppppH = CAM Page Address value (Hexadecimal) xxxxH = "Don’t Care" Table 27: Source Address Search Routine Line 1 2 3 4 /CM H H H H /W L L L L /E Cycle Short Short Short Short /EC H H H L Mnemonic DQ(15:0) xxxxH ddddH ddddH ddddH Description Dummy write to Segment 0 Write 1st 16 bits to Segment 1 Write 2nd 16 bits to Segment 2 Write 3rd 16 bits to Segment 3 and compare If a match is found and PCFG_EXT bit 3 = 0, update time stamp: 5a L L Long H MOV_HM, CR,MR1 0368H Move to Highest match through MR1 to update Time Stamp and Port ID. This command resides in SSAU (see System Op-Code Registers). If a match is found and PCFG_EXT bit 3 = 1, read associated data: 5b H H Long H ddddH Read associated data to check if Permanent bit is set. If Permanent bit = 0, then 5c is performed. Otherwise, the routine is complete. Move to Highest match through MR1 to update Time Stamp and Port ID. This command resides in SSAU (see System Op-Code Registers). 5c L L Long H MOV_HM, CR,MR1 0368H If no match is found, learn new address: 5d L L Long H MOV_NF,CR,V 0334H Move SA to Next Free with Time Stamp and Port ID. This command resides in SSAL (see System Op-Code Registers). Table 28: Purge Routine Line 1 2 3 4 /CM L H L L /W L L L L /E Cycle Short Long Long Short /EC H H H H VBC_ALM,E SFR Mnemonic SBR DQ(15:0) 0619H ddddH 043DH 0618H Description Select Background Register set Purge time stamp value and compare Mark all matching entries “Empty” Select Foreground Register set 20 Rev. 0a Applications MU9C8338A 10/100Mb Ethernet Filter Interface Table 29: Add Permanent Entry Routine Line 1 2 3 4 5 /CM H H H H L /W L L L L L /E Cycle Short Short Short Short Long /EC H H H H H MOV_NF,CR,V Mnemonic DQ(15:0) ddddH ddddH ddddH ddddH 0334H Description Write Perm Bit and Port ID to Segment 0 Write 1st 16 bits to Segment 1 Write 2nd 16 bits to Segment 2 Write 3rd 16 bits to Segment 3 Move to Next Free Table 30: Delete Entry Routine Line 1 2 3 4 5 /CM H H H H L /W L L L L L /E Cycle Short Short Short Short Long /EC H H H L H VBC_HM,E Mnemonic DQ(15:0) xxxxH ddddH ddddH ddddH 042DH Description Dummy Write to Segment 0 Write 1st 16 bits to Segment 1 Write 2nd 16 bits to Segment 2 Write 3rd 16 bits to Segment 3 and compare Set Highest Match to “Empty” Table 31: Set Address Register Routine Line 1 2 3 4 /CM L L L L /W L L L L /E Cycle Short Short Short Short /EC H H H H SFR Mnemonic SBR TCO_AR DQ(15:0) 0619H 0220H aaaaH 0618H Description Select Background Register set Target Address register Address value Select Foreground Register set Table 32: Read Entries Routine Line 1 2 3 4 5 6 7 8 9 10 11 12 /CM L L L H H H H L L L L L /W L L L H H H H H H L L L /E Cycle Short Short Short Long Long Long Long Med Med Short Short Short /EC H H H H H H H H H H H H SFR TCO_DS Mnemonic SBR TCO_DS DQ(15:0) 0619H 0228H ppppH ddddH ddddH ddddH ddddH ddddH ddddH 0228H FFFFH 0618H Description Select Background Register set Target Device Select register Page Address value Data Read, Segment 0 Data Read, Segment 1 Data Read, Segment 2 Data Read, Segment 3 Command Read, Status Register bits 15:0 Command Read, Status Register bits 31:16 Target Device Select register Select all devices Select Foreground Register set Rev. 0a 21 MU9C8338A 10/100Mb Ethernet Filter Interface Electrical ELECTRICAL Absolute Maximum Ratings Supply Voltage Voltage push/pull outputs* Voltage on all other pins Storage Temperature I/O Source Sink Current -0.5 to 3.6 Volts -0.5 to VDD +0.5 Volts -0.5 to 5.5 Volts -65° C to 150° C ±20 mA Stresses exceeding those listed under Absolute Maximum Ratings may induce failure. Exposure to absolute maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied. All voltages referenced to GND. Note: Push/Pull Outputs: FRX_ER, /INTR, REJ, /RESET_LC, RP_DV, TP_DV, and TP_SD Operating Conditions Voltages referenced to GND at the device pin. Symbol VDD VIH VIL t R, t F TA Parameter Operating Supply Voltage Input Voltage Logic 1 Input Voltage Logic 0 Input Transition Time Ambient Operating Temperature Commercial Industrial 0 -40 Min 3.0 2.0 -0.5 2 Typical 3.3 Max 3.6 5.5 0.7 500 70 85 Units Volts Volts Volts ns °C °C Still Air Notes DC Electrical Characteristics Symbol IDD IDD(SB) VOH Parameter Average Power Supply Current Stand-by Power Supply Current Output Voltage Logic 1 2.2 2.2 2.2 2.2 VOL Output Voltage Logic 0 0.4 0.4 0.4 0.4 IIZ Input Leakage Current -1 -170 IOZ Output Leakage Current -1 -170 -66 -66 1 -15 1 -15 Min Typical 75 Max 90 100 Units mA µA Volts Volts Volts Volts Volts Volts Volts Volts µA mA µA µA IOH = 2.0mA1 IOH = 4.0mA2 IOH = 8.0mA3 IOH = 12.0mA4 IOL = 2.0mA1 IOL = 4.0mA2 IOL = 8.0mA3 IOL = 12.0mA4 GND ≤ VIN ≤ VDD VIN ≤ GND5 GND ≤ VOUT ≤ VDD VIN = GND6 Notes Notes: 1. 2. 3. 4. 5. 6. Pins: FRX_ ER, /INTR, REJ, /RESET_LC, RP_DV, TP_DV, TP_SD, and TDO Pins: D[15:0] Pins: PROC_ RDY, RP[15:0], DQ[15:0], and /E Pins: /CM, /EC, and /W Pins: TCK, TDI, TMS, and TRST Pins: DQ[15:0] and /E 22 Rev. 0a Timing Diagrams MU9C8338A 10/100Mb Ethernet Filter Interface Capacitance Symbol CIN COUT CI0 Parameter Input Capacitance Output Capacitance Bi-directional Capacitance Typ 6 9 10 Units pF pF pF Notes f = 1 MHz, VIN = 0 V f = 1 MHz, VOUT = 0 V f = 1 MHz, VI0 = 0 V TIMING DIAGRAMS Host Processor Table 33: Host Processor Interface Timing Data No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Symbol tPLDX tPHDZ tWVPL tPLWX tCHDV tDVPH tPHDX tCHPRH tAVPL tPLAX tPHPL tPLPRL tPRHPRL Parameter (ns) /PCS (/PCSS) LOW to D(15:0) enable /PCS (/PCSS) HIGH to D(15:0) disable /WRITE setup to /PCS (/PCSS) /WRITE hold from /PCS (/PCSS) SYSCLK HIGH to D(15:0) (read) D(15:0) setup to /PCS (/PCSS) HIGH (write) D(15:0) hold from /PCS (/PCSS) HIGH (write) PROC_RDY delay from SYSCLK HIGH A(7:0) setup to /PCS (/PCSS) LOW A(7:0) hold from /PCS (/PCSS) LOW /PCS (/PCSS) HIGH time /PCS (/PCSS) to PROC_RDY LOW PROC_RDY HIGH time 5 3 2*SYSCLK+8 10 1*SYSCLK 5 3 10 3 3 10 Min Max SYSCLK+5 SYSCLK+5 Notes t3 t9 /PCS (/PCSS) t1 D[15:0](read) t10 A[7:0] t4 /WRITE (read) t8 t12 PROC_RDY t13 t5 t2 t11 SYSCLK Figure 7: Host Processor Interface - Read Sequence Rev. 0a 23 MU9C8338A 10/100Mb Ethernet Filter Interface Timing Diagrams t3 t9 /PCS (/PCSS) t10 A[7:0] t8 t12 PROC_RDY t13 t6 t11 t7 D[15:0](write) t4 /WRITE (write) SYSCLK Figure 8: Host Processor Interface - Write Sequence Result Port Interface Table 34: Result Port Interface Timing Data No. 16 17 18 19 20 21 22 23 Symbol tNLSH tSHRPV tNHRPX tNHSL tNHPDL tNHRPnV tNLNH tNHNL Parameter (ns) RP_NXT deassert to RP_SEL assert RP_SEL to RP(15:0) Valid RP_NXT to RP(15:0) invalid RP_NXT to RP_SEL deassert RP_NXT to RP_DV deassert RP_NXT to next Valid RP(15:0) RP_NXT LOW Time RP_NXT pulse width 3*SYSCLK+5 3*SYSCLK+5 0 3*SYSCLK+5 7*SYSCLK+10 7*SYSCLK Min 0 20 Max Notes RP_DV 16 17 RP_SEL 21 18 RP[15:0] 22 valid 23 invalid valid RP_NXT Figure 9: Result Port - Additional Valid Data Packets 20 RP_DV 16 17 19 RP_SEL 18 RP[15:0] 22 valid 23 invalid RP_NXT Figure 10: Result Port - No Additional Valid Data Packets 24 Rev. 0a Timing Diagrams MU9C8338A 10/100Mb Ethernet Filter Interface Table 35: RXD, RX_DV, and RX_ER Timing Data No. 14 15 Symbol tRDVRCLH tRCCHRDX Parameter (ns) Data setup prior to rising RX_CLK edge Data hold after rising RX_CLK edge Min 10 10 Max Notes 14 15 RX_CLK RXD, RX_DV, RX_ER Control Port Interface Table 36: Control Port Interface Timing Data No. 24 25 26 27 28 Symbol tCHRH tRLRLCL tCHRLCL tCHIH tCHIL Parameter (ns) SYSCLK HIGH to /RESET HIGH /RESET LOW to RESET_LC LOW SYSCLK to RESET_LC LOW SYSCLK to /INTR HIGH SYSCLK to /INTR LOW Min 2*SYSCLK 10 0 0 0 4*SYSCLK+10 10 10 10 Max Notes VCC SYSCLK 24 25 /RESET 26 RESET_LC 27 28 /INTR Rev. 0a 25 MU9C8338A 10/100Mb Ethernet Filter Interface Timing Diagrams Table 37: REJ (Base 10) Timing Data No. 36 37 38 39 40 Symbol tJLRCH tRCHJH tJHJL tRCHJH tRCHSL Parameter (ns) REJ to rising edge of RX_CLK Rising edge of RX_CLK to REJ (after SFD event) REJ assertion width RX_CLK rising edge to REJ HIGH RX_CLK rising edge to REJ LOW 0 0 39 RX_CLK RXD[3:0] 36 RX_DV 37 /REJ 38 Preamble Min 400 4800 Max Notes 50400 2*RX_CLK 20 20 40 SFD DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 SA0 SA1 Table 38: REJ (Base 100) Timing Data No. 41 42 43 44 45 Symbol tJLRCH tRCHJH tJHJL tRCHJH tRHJL Parameter (ns) REJ to rising edge of RX_CLK Rising edge of RX_CLK to REJ (after SFD event) REJ assertion width RX_CLK rising edge to REJ HIGH RX_CLK rising edge to REJ LOW 0 0 44 RX_CLK RXD[3:0] 41 RX_DV 42 /REJ 43 Preamble Min 40 480 Max Notes 5040 2*RX_CLK 20 20 45 SFD DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 SA0 SA1 Table 39: FRX_ER in Relation to REJ and RX_ER Timing Data No. 46 47 48 49 Symbol tJLFEH tREHFEH tJHFEL tRFLFEL Parameter (ns) Delay REJ LOW to FRX_ER HIGH Delay RX_ER HIGH to FRX_ER HIGH Delay REJ HIGH to FRX_ER LOW Delay RX_ER LOW to RX_ER LOW Min 0 0 0 0 Max SYSCLK+RX_CLK+10 20 SYSCLK+RX_CLK+10 20 Notes 46 /REJ 47 RX_ER FRX_ER 48 49 26 Rev. 0a Timing Diagrams MU9C8338A 10/100Mb Ethernet Filter Interface Table 40: Tag Ports TP_DV and TP_SD Timing Data No. 50 51 52 53 Symbol tRCJTOH tRCHTSH tRCHTDL tRCHTSL Parameter (ns) Delay RX_CLK HIGH to TP_DV HIGH Delay RX_CLK HIGH to TP_SD HIGH Delay RX_CLK HIGH to TP_DV LOW Delay RX_CLK HIGH to TP_SD LOW Min 0 0 0 0 Max 20 20 20 20 Notes RX_CLK 50 52 TP_DV 51 53 BIT5 (MSB) BIT4 BIT3 BIT2 BIT1 BIT0 (LSB) TP_SD Timing Data for LANCAM Interface Switching Characteristics LANCAM Compare Cycle Time No. 1 Symbol tELEL Parameter Chip Enable Compare Cycle Time Short Cycle 2 tELEH Chip Enable LOW Pulse Width Medium Cycle Long Cycle 3 4 5 tEHEL tEHELC tELQV Chip Enable HIGH Pulse Width Chip Enable HIGH Pulse Width (Compare) Chip Enable LOW to DQ Bus VALID (Read) 70 ns Typ 7*SYSCLK 1*SYSCLK 2*SYSCLK 3*SYSCLK 1*SYSCLK 4*SYSCLK 3*SYSCLK 90 ns Typ 8*SYSCLK 2*SYSCLK 3*SYSCLK 4*SYSCLK 1*SYSCLK 4*SYSCLK 4*SYSCLK All No. 6 7 8 9 10 11 12 13 Symbol tKHEL tKHEH tKHGX tKHGV tKHQV tKHQX tFIVKH tMIVKH Parameter (all times in nanoseconds) SYSCLK HIGH to Chip Enable LOW Delay Time SYSCLK HIGH to Chip Enable HIGH Delay Time SYSCLK HIGH to CAM Controls INVALID Delay Time SYSCLK HIGH to CAM Controls VALID Delay Time SYSCLK HIGH to DQ Bus VALID Delay Time SYSCLK HIGH to DQ Bus INVALID Delay Time Full Input VALID to SYSCLK HIGH Setup Time MATCH Input VALID to SYSCLK HIGH Setup Time Min. 5 5 5 5 5 5 10 5 Max. 19 19 19 19 19 19 5 6 4 4 Notes 120 ns (90 ns) Typ 8*SYSCLK 2*SYSCLK 4*SYSCLK 5*SYSCLK 1*SYSCLK 4*SYSCLK 5*SYSCLK 1 1 1,3 Notes 1 1,2 Notes: 1. 2. 3. 4. 5. 6. The MU9C8338A LANCAM interface must be configured to accept the speed grade of the LANCAM being used. Once it is configured for the appropriate speed grade (70 ns, 90 ns, or 120 ns (90 ns)) the cycle time will vary accordingly. The MU9C8338A contains built-in routines that include LANCAM short, medium, or long cycles. The cycle will vary depending upon what LANCAM cycle is being performed by the MU9C8338A. A LANCAM read cycle initiated by the MU9C8338A could be to the internal memory array or to the LANCAM registers. The timing specified meets the requirements to successfully read from either source. CAM Control signals are /CM, /W, and /EC. The /FI input is latched by the MU9C8338A on every rising edge of SYSCLK. The LANCAM interface is designed to work properly with up to four LANCAMs. Rev. 0a 27 MU9C8338A 10/100Mb Ethernet Filter Interface Timing Diagrams SYSCLK 7 6 2 3 6 /E 9 8 /W 9 8 /CM 9 8 /EC 5 DQ15-0 Figure 11: LANCAM Interface: Read SYSCLK 7 6 2 3 6 /E 9 8 /W 9 8 /CM 9 8 /EC 10 11 DQ15-0 12 /FI Figure 12: LANCAM Interface: Write SYSCLK 6 2 7 1 4 6 /E 9 8 /W 9 8 /CM 9 8 /EC 13 /MI Figure 13: LANCAM Interface: Compare 28 Rev. 0a Notes MU9C8338A 10/100Mb Ethernet Filter Interface Notes Rev. 0a 29 MU9C8338A 10/100Mb Ethernet Filter Interface Notes Notes 30 Rev. 0a Notes MU9C8338A 10/100Mb Ethernet Filter Interface Notes Rev. 0a 31 MU9C8338A 10/100Mb Ethernet Filter Interface Ordering Information ORDERING INFORMATION Part Number MU9C8338A-TFC MU9C8338A-TFI Package 144-Pin LQFP 144-Pin LQFP Temperature 0–70° C -40–85° C Voltage 3.3 3.3 PACKAGE OUTLINE He E A A2 A1 D Hd 1 L1 e b L Table 41: 144-Pin LQFP Dim. A Min. Nom. Max. 1.6 0.15 Dim. A1 0.05 Dim. A2 1.35 1.40 1.45 Dim. b 0.17 0.22 0.27 20.0 20.0 0.5 22.0 22.0 1.0 Dim. D Dim. E Dim. e Dim. Hd Dim. He Dim. L1 L 0.45 0.60 0.75 MUSIC Semiconductors’ agent or distributor: MUSIC Semiconductors reserves the right to make changes to its products and specifications at any time in order to improve on performance, manufacturability or reliability. Information furnished by MUSIC is believed to be accurate, but no responsibility is assumed by MUSIC Semiconductors for the use of said information, nor for any infringements of patents or of other third-party rights which may result from said use. No license is granted by implication or otherwise under any patent or patent rights of any MUSIC company. © Copyright 2001, MUSIC Semiconductors http://www.musicsemi.com email: info@musicsemi.com Worldwide Headquarters MUSIC Semiconductors 1521 California Circle Milpitas, CA 95035 USA Tel: 408 869-4600 Fax: 408 942-0837 USA Only: 800 933-1550 Tech Support 888 226-6874 Product Info Asian Headquarters MUSIC Semiconductors Special Export Processing Zone Carmelray Industrial Park Canlubang, Calamba, Laguna Philippines Tel: +63 49 549-1480 Fax: +63 49 549-1024 Sales Tel/Fax: +632 723-6215 European Headquarters MUSIC Semiconductors P O. Box 184 . 6470 ED Eygelshoven The Netherlands Tel: +31 43 455-2675 Fax: +31 43 455-1573 32 Rev. 0a