MU9C8358L

'DWD 6KHHW MU9C8358L Quad 10/100Mb Ethernet Filter Interface $33/,&$7,21 %(1(),76 • • • • • • • 10/100Mb Ethernet switching, bridging, and remote access at wire speed Glueless connection to MUSIC LANCAM and most 10/100Mb Ethernet chip sets Offloads all DA/SA processing and management functions from host processor Scalable up to eight ports of 100Mb Ethernet sharing a common LANCAM database Support station lists from 0.25K up to 32K Full support of Unicast, Multicast, and Broadcast frames Built-in generic Processor port ',67,1&7,9( &+$5$&7(5,67,&6 • • • • • • • • • •  Four industry-standard 10/100Mb MII ports Supports station list up to 32K addresses Built-in arbitration supports eight 100Mb Ethernet ports Port ID identification and MAC Frame Reject signal based on DA search results Read search results from the Result port or CPU port Hardware support for Tag switching Optional automatic learning of new SAs Optional automatic Aging and Purging 208-pin LQFP package 3.3 Volt operation   0,, 7$* 3RUW $ /$1&$0 ,QWHUID.H 5HVXOW 3RUW     0,, 7$* 3RUW % 6WDWH 0D.KLQH   0,, 7$* 3RUW & &RQILJXUDWLRQ 5HJLVWHUV 3UR.HVVRU 3RUW     0,, 7$* 3RUW ' $UELWHU  Figure 1: Block Diagram /$1&$0 086,& 6HPL.RQGX.WRUV WKH 086,& ORJR DQG WKH SKUDVH 086,& 6HPL.RQGX.WRUV DUH 5HJLVWHUHG WUDGHPDUNV RI 086,& 6HPL.RQGX.WRUV 086,& LV D WUDGHPDUN RI 086,& 6HPL.RQGX.WRUV $XJXVW   5HY  08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H *HQHUDO 'HV.ULSWLRQ *(1(5$/ '(6&5,37,21 The MU9C8358L, when configured with MUSIC Semiconductors MU9Cx480B family of LANCAMs, provides a high performance, large capacity Ethernet address processing subsystem for use in Ethernet bridge, switch, or remote access products. The device is designed to work in multi-port systems that require a common address database for all ports. Built-in arbitration allows two MU9C8358L devices to share a common CAM database, supporting up to eight 100Mb/s Ethernet ports at wire speed. 23(5$7,21$/ 29(59,(: Because of the flexibility of the MU9C8358L, the best way to approach the feature set of the device is to first look at a typical Multiport 10/100Mb Ethernet application. The MU9C8358L captures the Destination address (DA) and the Source address (SA) of an incoming Ethernet frame on the MII port. After checking for a frame error or collision, the DA is processed and the result (associated data, usually a port ID) is made available. The SA then is checked, and either learned if new, or aged if already in the list. When the DA is processed, the MU9C8358L first checks if the frame is Unicast, Multicast, or Broadcast. Unicast frames destined for the same collision domain (visible on the same switch port as it came in on) are rejected. Unicast frames that are destined for a different collision domain (visible on a different switch port) are processed by the system. If the DA is found in the CAM database, the port ID associated with it is stored in the Result register. Multicast and Broadcast frames are not processed by the system. Instead they are identified and their classification is stored in the Result register. Once processing completes, the Result register is accessed through the Result port or Processor port. Provided the frame length is correct, and no errors are detected, the SA is processed. If the SA exists in the CAM database, the time stamp and Port ID are updated. If the SA is not found in the CAM database, the address is learned automatically, along with its Port ID and the current time stamp information. The built-in arbitration allows all ports equal access to the CAM database. The arbitration scheme gives DA processing the highest-priority, then SA processing. Address processing always has priority over management routines, such as purging aged entries, inserting permanent entries, deleting entries, or reading from the CAM database. Using the 70 ns speed grade CAMs and a 50 MHz system clock, there is sufficient time to support eight DA searches, eight SA searches, and one management routine, within the minimum frame time (about 6.2µS). In addition, the arbitration bus allows the MU9C8358L to be used with future MUSIC devices, sharing a common CAM database. 7\SL.DO 08&/ $SSOL.DWLRQ The MU9C8358L plays an integral role in the example of an Ethernet switching system, shown in Figure 2. This system can handle up to 32,768 addresses distributed over eight independent, bidirectional 100Mb Ethernet ports by utilizing two MU9C8358L devices and four LANCAMs connected as shown in Figure 1. The system is based on several industry-standard and proprietary busses, which are described in more detail later. The MII bus is "tapped" to collect packet data as it passes from the PHY to the MAC. That data is processed automatically by the MU9C8358L/LANCAM combination. The LANCAM bus is utilized to transfer the DA and SA to the CAMs for comparisons, and to transfer the match results from the CAMs to the MU9C8358L. The results of MU9C8358L/LANCAM data processing are available through the Result bus or through the Processor bus. In addition to the Result bus, there is a serial Tag port per MII port to relay the Tag ID to the system for systems that support Tag switching. The Arbitration bus provides communication between two MU9C8358L devices to service eight MII ports with a shared CAM-based station list.  5HY  2SHUDWLRQDO 2YHUYLHZ 08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H 5(-(&7 0,, 3RUW 0$& )5B(55 7$* 5(-(&7 0,, 3RUW 0$& )5B(55 7$* /$1&$0 'DWDEDVH 08&/ 5(-(&7 0,, 3RUW 0$& )5B(55 7$* 5(-(&7 0,, 3RUW 0$& )5B(55 7$* 3UR.HVVRU %XV $UELWUDWLRQ %XV /$1&$0 %XV %XV 0,, 3RUW 0$& )5B(55 7$* 5(-(&7 0,, 3RUW 0$& )5B(55 7$* 5(-(&7 0,, 3RUW 08&/ 6\VWHP +DUGZDUH 0$& )5B(55 7$* 5(-(&7 0,, 3RUW 0$& )5B(55 7$* Figure 2: MU9C8358L Typical Application 5HY   &38 +RVW 5(-(&7 5HVXOW +RVW &38 08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H 3LQ 'HV.ULSWLRQV 3,1 '(6&5,37,216 352&B5'< 5(6(7B/& 5(6(59(' 5(6(59(' 5(6(59(' 5(6(59(' 5(6(59(' 5(6(59(' 5(6(59(' 5(6(59(' 5(6(59(' 5(6(59(' 5(6(59(' 6@ 3UR.HVVRU 3RUW 'DWD ,QSXW2XWSXW 7ULVWDWH 77/ Processor Data bus D[15:0] is the tri-state processor data bus for the MU9C8358L. 352&B5'< 3UR.HVVRU 3RUW 5HDG\ 2XWSXW 7ULVWDWH 77/ When reading from or writing to any MU9C8358L internal register, the PROC_RDY tri-state output goes LOW on the falling edge of /PCS or /PCSS. It goes HIGH on the rising edge of the first SYSCLK after /PCS or /PCSS is LOW, to indicate that data is available (read) or data has been accepted (write). 567$7 5HIHU 2QH RI WKH 0,, SRUWV KDV SDUVHG DQ WR 1RWHV EHORZ LQ.RPLQJ SD.NHW 7KH '$ ORRNXS KDV EHHQ SHUIRUPHG DQG WKH UHVXOW GDWD LV DYDLODEOH WR EH UHDG IURP WKH 5'$7 UHJLVWHU 667$7 5HIHU 7KH )) RXWSXW IURP WKH /$1&$0 V WR 1RWHV EHORZ KDV LQGL.DWHG WKDW WKH /$1&$0 LV IXOO :KHQ UHDGLQJ WKH 667$7 UHJLVWHU D IXOO .RQGLWLRQ LV LQGL.DWHG E\ ELW   67$5* Notes: 1. 2. RSTAT–/INTR only returns HIGH when all possible result data has been read. SSTAT–/INTR only returns HIGH when the LANCAM has become not full. Therefore, after the SSTAT register read has confirmed the status of the interrupt condition, an entry should be removed from the LANCAM by using the PURGE sequence. /$1&$0 ,QWHUID.H See Timing Diagrams: Timing Data for LANCAM Interface. '4>@ /$1&$0 %XV ,QSXW2XWSXW 7ULVWDWH 77/ DQ[15:0] tri-state 16-bit bus transfers data or instructions between the MU9C8358L and the LANCAM. When no data or instructions are present on the bus, the bus goes HIGH-Z. These pins have 50-kΩ internal pull-up resistors. ( /$1&$0 %XV (QDEOH 2XWSXW 7ULVWDWH 77/ The /E chip enable is taken LOW to initiate LANCAM activity. On LANCAM read cycles, /E is taken HIGH after the MU9C8358L registers the data. This pin has a 50-kΩ internal pull-up resistor. : /$1&$0 %XV :ULWH 2XWSXW 7ULVWDWH 77/ The MU9C8358L outputs /W (read/write select) to control the direction of data flow between the MU9C8358L and the LANCAM. If /W is LOW at the falling edge of /E, the MU9C8358L outputs data on the DQ[15:0] bus for the LANCAM as input. When /W is HIGH at the falling edge of /E, the LANCAM outputs data on the DQ[15:0] bus to the MU9C8358L as input.  5HY  08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H &0 /$1&$0 %XV &RPPDQG 0RGH 2XWSXW 7ULVWDWH 77/ The MU9C8358L outputs /CM Data/Command Select to control whether the LANCAM interprets the DQ[15:0] bus contents as command information or data. If both /CM and /W are LOW at the falling edge of /E, the MU9C8358L outputs an instruction for the LANCAM to execute or a value for one of the LANCAM configuration registers. If /CM is LOW while /W is HIGH, then the LANCAM will output data from one of its configuration registers to the MU9C8358L. If /CM is HIGH while /W is LOW, the MU9C8358L will output data for the LANCAM to place in one of its data registers or memory. If /CM is HIGH while /W is HIGH, the LANCAM outputs data from one of its data registers or memory to the MU9C8358L. (& /$1&$0 %XV (QDEOH &KDLQ 2XWSXW 7ULVWDWH 77/ The Daisy Chain Enable signal performs two functions. The /EC signal enables the LANCAMs /MF output to show the results of a comparison. If /EC is LOW at the falling edge of /E in a cycle, the /MF flag output is enabled; otherwise, /MF is held HIGH. The /EC signal also enables the /MF-/MI daisy chain that serves to select the device with the highest-priority match in a string of LANCAMs. 0, /$1&$0 %XV 0DW.K )ODJ ,QSXW 77/ The /MI LANCAM Match flag input is used to indicate to the MU9C8358L the conditions of the LANCAM Match flag. The /MF output from the LANCAM should be connected to this pin. If more than one LANCAM is used, /MI should be connected to the /MF pin of the last LANCAM in the daisy chain. ), /$1&$0 %XV )XOO )ODJ ,QSXW 77/ The /FI LANCAM Full flag input is used to indicate to the MU9C8358L the condition of the LANCAM Full flag. The /FF output from the LANCAM should be connected to this pin. If more than one LANCAM is used, /FI should be connected to the /FF of the last device in the daisy chain. 5(6(7B/& 5HVHW /$1&$0 2XWSXW 77/ 6ODYH ,QVWDQ.H  1R &RQQH.WLRQ /RESET_LC is LOW whenever /RESET is LOW. It is taken HIGH only by writing to bit 0 in the System Dynamic Configuration (SDCFG) register. See SDCFG register information. /RESET_LC is used only on the master device; it is left unconnected on the slave device when two MU9C8358Ls are connected together. 3LQ 'HV.ULSWLRQV $UELWUDWLRQ %XV 6@ $UELWHU 3RUW ,QSXW2XWSXW 77/ The MU9C8358L configured as MASTER must monitor the attached slave device to determine which device gains access to the CAM in a given processing cycle. These signals are not used in a single MU9C8358L application, and may be left unconnected. These pins have 50-kΩ internal pull-up resistors. See Timing Diagrams: Timing Data for Control Interfaces. -7$* Please refer to IEEE Standard 1149.1 for information on using the mandatory JTAG functions. The optional HIGH-Z function is implemented and may be activated by writing 0011 to the JTAG Instruction register. 7567 -7$* 5HVHW ,QSXW The /TRST is the Test Reset pin. It is internally pulled up with a 50-kΩ resistor. It must be tied to /RESET or tied LOW when the JTAG port is not used. 7&. -7$* 7HVW &OR.N ,QSXW The TCK input is the Test Clock input. It can be tied at a valid logic level 1 when not in use. This pin is internally pulled up with a 50-kΩ resistor. 706 -7$* 7HVW 0RGH 6HOH.W ,QSXW The TMS input is the Test Mode Select input. This pin is internally pulled up with a 50-kΩ resistor. 7', -7$* 7HVW 'DWD ,QSXW ,QSXW The TDI input is the Test Data input. This pin is internally pulled up with a 50-kΩ resistor. 7'2 -7$* 7HVW 'DWD 2XWSXW 2XWSXW The TDO output is the Test Data output. 7(67(1 This pin is used for internal MUSIC Semiconductor testing only. This pin has a 50-kΩ pull-up resistor to VDD and may be left as "NO CONNECT" in system applications. 3RZHU $QG *URXQG 9'' *1' 3RVLWLYH 3RZHU 6XSSO\ *URXQG These pins are the power supply connections to the MU9C8358L. VDD must meet the voltage supply requirements in the Operating Conditions section relative to the GND pins, which are at 0 Volts (system reference potential), for correct operation of the device.  5HY  )XQ.WLRQDO 'HV.ULSWLRQ 08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H )81&7,21$/ '(6&5,37,21 08&/ ,QWHUQDO )XQ.WLRQV MU9C8358L internal functions are shown in Figure 4. Before discussing the individual blocks, the underlying principles are presented. The network interfaces are monitored for network and data symbol errors. Receive data [RXD] is clocked into a register using the 25 MHz recovered clock for 100Base-X or 2.5 MHz clock for 10Base-X. The Preamble and Start Frame delimiter (SFD) are scanned to locate the Destination address (DA) and the Source address (SA). An addressing mechanism uniquely identifies each MU9C8358L in a system. The Master MU9C8358L schedules communication with the host processor and the CAM through an arbitration process. Once the system is initialized and configured, highest-priority is given to network traffic. The LANCTL block generates the command cycles and operational codes to complete CPU-requested actions and network-generated requests. The CPU must initialize the CAM, write the permanent station list, and initiate other housekeeping functions. Network traffic initiates DA filtering, SA learning, and time stamp updates. All state-machines required for real-time operations are implemented in the ASIC hardware; the host CPU runs the non-time-critical initialization routine. Information on the LANCAM operation and instruction set can be found in the appropriate LANCAM data sheet for each device. 5;B'9 5;B(5 5;'>@ 5;B&/. &56 &2/ )5;B(5 5(73B6' 73B'9 /$1&$0 %XV 5;B'9 5;B(5 0,, ,QWHUID.H 0$& /$1&$0 ,QWHUID.H 0$& 0,, ,QWHUID.H 5;'>@ 5;B&/. &56 &2/ )5;B(5 7DJ 3RUW ,QWHUID.H 7DJ 3RUW ,QWHUID.H 5(73B6' 73B'9 5;B'9 5;B(5 5;'>@ 5;B&/. &56 &2/ )5;B(5 5(73B6' 73B'9 5;B'9 0,, ,QWHUID.H /$1&7/ 0$& 0$& 5;B(5 0,, ,QWHUID.H 5;'>@ 5;B&/. &56 &2/ )5;B(5 7DJ 3RUW ,QWHUID.H 7DJ 3RUW ,QWHUID.H 5(73B6' 73B'9 7&. $UELWUDWLRQ %XV $UELWHU -7$* &RQWUROOHU 706 7', 7'2 7567 &38 %XV +RVW &38 ,QWHUID.H &RQILJXUDWLRQ &RQWURO DQG 6WDWXV 5HJLVWHUV 5HVXOW %XV 5HVXOW %XV ,QWHUID.H ),)2 Figure 4: MU9C8358L Functional Block Diagram 5HY   08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H 'HVWLQDWLRQ $GGUHVV 3UR.HVVLQJ Once configured, the MU9C8358L will extract the DA from the frames that are received through the MII ports. An automatic address processing function is subsequently triggered. Once the DA processing function is triggered, the frame is monitored to detect whether it is a broadcast, multicast, or unicast frame and the appropriate actions are taken. DA processing consists of the following actions: • • • Packets are characterized as Broadcast, Multicast, or Unicast types. Unicast packets initiate a search of the CAM for existing entries. If a DA match is found, the Port ID read from the CAM is compared to the Source Port ID. If the Source Port ID and Destination Port ID match, the frame is rejected. If the Port IDs are different, the Tag information is made available for MACs that support Tag switching, through the Tag port. If the MU9C8358L rejects the frame, it asserts the Reject output pin (REJ) and forces the MII RX_ER output (FRX_ER) HIGH for the appropriate MII Port. This causes the MAC to discard the frame. Once the DA processing function is complete, the MU9C8358L stores the result. This result indicates the characterization of the processed frame. (Broadcast, Multicast, or Unicast) and the Source Port ID. Additionally, if a unicast frame was processed, the result of the search and the port ID of the DA is also stored. Finally, the detail of whether the Destination port and the Source port are identical is also stored. The result of DA processing may be read in two ways. An interrupt may be sent to the host processor indicating that there is a result available. The host processor would read the result from an internal Result Data register. Alternatively, external circuitry can monitor the status of the Result Port Data valid (RP_DV) output pin. This output indicates that there is a result available in the internal register, which can be read through the Result port. The external circuitry can read the data by asserting the Result Port Select (RP_SEL) pin. Assertion of Result Port Next (RP_NXT) clears the value and advances the next entry if there is one available. )XQ.WLRQDO 'HV.ULSWLRQ 6RXU.H $GGUHVV 3UR.HVVLQJ Once configured, the MU9C8358L also will perform SA processing functions after the address information has been extracted from a received frame. The SA of each arriving frame is stored by the MU9C8358L for further processing, along with the ID of the port on which it arrived, and the current time stamp. Note that at start-up, permanent addresses and Port IDs are loaded into the LANCAM through the CPU port; as message traffic proceeds, new addresses are learned and added to the LANCAM database, and aged addresses are purged. SA processing consists of the following actions: • The SA field is collected and temporarily stored. Note the SA cannot be a Broadcast or Multicast address by definition. • When the complete packet has arrived, the CRC field is checked and the length of the packet is checked (if the CRC facility is enabled and the packet is 10 Base - X). Any errors result in no further SA processing. • If the packet did not contain any errors (or the CRC check facility is disabled), the SA field is compared with the address fields that are stored in the LANCAM. • If a match is found, the Port ID and time stamp for that entry are updated. If no match is found, the SA is added to the CAM, along with the current time stamp and the Port ID assigned to that particular Source port. See the PCFG registers section for more information on the CRC check facility. • • •  5HY  )XQ.WLRQDO 'HV.ULSWLRQ 0$& $GGUHVV 6WRUDJH When the MU9C8358L performs an SA processing function, it automatically extracts the MAC address from the packet. The database is searched and the MAC address is added to the LANCAM database if necessary. Similarly, when a DA processing function is performed, the MU9C8358L automatically searches the database for the extracted DA MAC address. It is important that the user is aware of the byte ordering of the 48-bit MAC address when it is stored in the LANCAM database. This is because the user must byte-order MAC addresses identically when a database entry is to be manually added or deleted. Similarly, if the user wishes to read out a MAC address, they also should be aware of the byte ordering when the relevant data registers are read. Throughout this data sheet MAC addresses are shown as bit 47 being the most significant bit, which is placed on the left. Similarly, bit 0 is shown as the least significant bit and placed on the right. Using this notation, the Individual/Group (I/G) bit subfield would be shown as bit 40. This bit would be the first bit of an address transmitted onto the serial network and also the first bit received. The IEEE 802.3 refers to the I/G bit subfield as bit 0. If the bit is set to 1, it indicates that the address is a group address. Conversely, if the bit is set to 0, it indicates it is an individual address. Figure 5 shows a typical 48-bit MAC address used in Ethernet or IEEE 802.3 networks. 0$& $GGUHVV          &              08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H If the MAC address shown in Figure 5 is added to the database by the MU9C8358L, it is stored as follows: • • • • Segment 3 = 6002h Segment 2 = 128Ch Segment 1 = 5634h Segment 0 = Associated data (permanent bit, time stamp and port ID) If the user wishes to use the built-in routines to manually add, delete, or read MAC addresses from the database, the System CAM Word registers (SCDW) are used as shown in Figure 6. It shows how the MAC address, used as an example in Figure 5, would be transferred using the SCDW registers. If the user intended to delete the MAC address, the SCDW registers would be written as shown in item 1 and the SDO_DELETE routine would be invoked. If the user intended to add the address manually, the SCDW registers would be written as shown in item 2 and the SDO_ADD routine would be invoked. Finally, if the user intended to read an entry, the SDO_READ routine would be invoked and the address would be read from the SCDW registers as shown in item 3. The built-in routines are explained more fully later in this document.  6&': 6'2B'(/(7( QRW XVHG 6&':  6&': & 6&':     6&': 6'2B$''  6&': & 6&':  6&': DVVR. GDWD ,((( ELW  ,* ELW  6&': 6&': & 6&':  6&': DVVR. GDWD /$1&$0 'DWDEDVH (QWU\ VHJ   VHJ  & VHJ   VHJ  DVVR. GDWD 6'2B5($'  Figure 6: SCDW Register Order Figure 5: MAC Address Byte Order 5HY   08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H )XQ.WLRQDO 'HV.ULSWLRQ ),)2 DQG 5HVXOW 3RUW When the DA sequence is executed, the result is stored in a FIFO for later collection by either the CPU over the Processor Bus from the Result register, or by external hardware attached to the Result port. ,QLWLDOL]DWLRQ At power-up or after a hardware reset, the host processor should download the LANCAM configuration and register contents to enable the LANCAM to operate as required. The LANCAM initialization and configuration that is downloaded by the CPU should do the following: The individual Page Address registers of each LANCAM in the LANCAM chain should be set with appropriate values. The Foreground Register set should be set to allow normal DA and SA filtering. This involves setting the Control, Segment Control, and Mask registers to suit. The Background Register set should be set to allow the background management tasks to be preformed. This involves setting the Control, Segment Control, and Mask registers to suit. The LANCAM should be configured to store 48-bit MAC addresses in segments 3–1 and the associated data in segment 0. The allocation of bits in the 16-bit associated data segment is specified in the description of the SCDW0 Association Data register. A full description of the configuration routine required for a typical eight port switch is given in AN-N24: Using the MU9C8358L Quad 10/100 Mb Ethernet Filter Interface in Switch Applications. 3HUPDQHQW 6WDWLRQ $GGUHVV Using the Add Entry routine, the nonvolatile station list can be added to the LANCAM by the host processor. The Associated Data bit 15 is set to 1, to indicate a permanent entry. Permanent entries are removed only with the Delete Entry routine. 0DQDJHPHQW The Delete Entry and Read Entry routines are available for database maintenance and housekeeping. Although permanent addresses cannot be purged, they can be deleted using the management Delete Entry routine. $JLQJ DQG 3XUJLQJ Time stamps are added automatically to the LANCAM entries by the MU9C8358L. Two counters are provided to store the current and purge time stamps. The Current Time Stamp is the 8-bit value that automatically is added or updated when a SA processing function is completed. The Purge Time stamp is the 8-bit value that is compared with the 8-bit time stamps stored with the LANCAM entries during purges. The initial value of the counters are STPURG = 01H and STCURR = 00H. The counters may be incremented individually through the CPU commands. )XQ.WLRQDO %OR.NV The MU9C8358L building blocks are shown in Figure 4, and their functions are described by the following. 0,, ,QWHUID.H 0,, 3RUWV $ WKURXJK ' The incoming asynchronous receive data is registered for subsequent processing. MU9C8358L internal processing is synchronous with the system clock. 7DJ 3RUW ,QWHUID.H 7DJ 3RUWV $ WKURXJK ' Rejection of a packet is indicated by the assertion of REJ. The FRX_ER line, which otherwise reflects the state of the RX_ER pin, is forced to HIGH at the same time. If the DA is matched in the LANCAM, the TP_DV pin is asserted and the destination port ID, high-order bit first, is clocked out through the TP_SD pin transitioning after the RX_CLK rising edge. 0$& This block performs tasks that are a subset of the Ethernet MACs. It detects errors, (CRS, COL, RX_ER, and Runt Frame), determines the start of frame, parses addresses, computes the CRC for 10Base-X packets, and formats the 4-bit nibbles into 48-bit SA and DA registers. $UELWHU The arbiter performs prioritization of internal functions and resource allocation. The arbiter allows two MU9C8358Ls to be cascaded and to share a single CAM database. The arbitration scheme requires that one MU9C8358L be the master and the other be the slave. Setting the bits 2–0 in the CHIPROL register to 000 identifies the Master. The MU9C8358L will function either as a Master or a Slave, and arbitration is transparent to the user. /$1&$0 6HTXHQ.HU /$1&7/ The sequencer is a state machine that generates the control signals required for CAM read and write cycles, and multiplexes appropriate data and operational codes to LANCAM data lines. The sequencer operations are: • • • • • • • Execute LANCAM cycles for CPU port DA processing SA processing Purging of aged entries Add Permanent Entries to LANCAM database Delete Entries from LANCAM database Read Entries from the LANCAM database.  5HY  )XQ.WLRQDO 'HV.ULSWLRQ Either the CPU or the external INCR pin can increment both counters simultaneously. Whenever STPURG is incremented, a purge operation is initiated. The counters roll-over so the times should be thought of as slots to be used and reused in a round-robin fashion. The existence of two counters (time stamps) allows the data-aging rate to be varied according to network traffic density. When the difference between the counters is large (default), the address data is purged less frequently; shrinking the counter difference causes the data to age sooner. Incoming SAs are time stamped or updated with the current value of STCURR. Older entries time stamped with the same value as STPURG are purged upon the increment of STPURG. The permanent address database built using the Add routine is not affected by time stamps. The data age gap is effectively the length of time an entry will exist in the LANCAM database if it is not updated. This gap is the difference between the STCURR and STPURG counter. When network traffic is low, STCURR may be increased in order to increase the length of time an entry will exist. When network traffic is high, STPURG may be increased in order to decrease the length of time an entry will exist. When STPURG is incremented older entries are also purged from the database if their time stamp matches STPURG. STCURR and STPURG may be incremented simultaneously to keep the data age gap constant and to purge the older entries from the database. To maintain "current" time, STCURR is advanced in any one of the three ways: 1. The CPU issues an increment STCURR command. Only the STCURR counter is increased. 2. The CPU issues an increment STCURR and STPURG command. Both counters are increased simultaneously. 3. The INCR pin is asserted. Both counters are increased simultaneously. To maintain "purge" time and to purge aged CAM entries, STPURG is advanced in any one of the three ways: 1. The CPU issues an increment STPURG command. Only the STPURG counter is increased. 2. The CPU issues an increment STCURR and STPURG command. Both counters are increased simultaneously. 3. The INCR pin is asserted. Both counters are increased simultaneously. If the STPURG value was incremented, the MU9C8358L initiates a purge operation using the new STPURG value. STPURG should never be incremented to equal STCURR. 08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H The time stamping of LANCAM entries and the procedure required to initiate a purge is explained as follows: 1. Incoming SAs to be learned are associated with the most recent STCURR value. The time stamps of each SA already in the CAM database is updated to STCURR, each time a packet with that SA is processed. 2. STPURG and STCURR are advanced as described earlier to purge entries that have the same time stamp value as STCURR. $JLQJ DQG 3XUJLQJ ([DPSOH This example begins with the initial defaults, STCURR = 00H and STPURG = 01H. As packets arrive, learned or refreshed, SAs are labeled with STCURR = 00H. (At that moment STPURG = 01H). Increment, either hardware or software initiated, results in STCURR = 01H and STPURG=02H. A purge operation is initiated that eliminates all CAM entries with time stamp = 02H. The oldest entries (SAs) that have not been updated in 255 increment times are purged automatically without further involvement. If the CAM Full flag is asserted, an interrupt (if configured) to the CPU is generated. Assume that STCURR = F0H, and STPURG = F1H. The CPU may initiate an increment STPURG operation so that older entries may be purged. This increases the value of STPURG to F2H. A purge operation is initiated that will eliminate all CAM entries with time stamp = F2H. The CPU should monitor the System Status register, and if the CAM is still full, the operation can be repeated until entries are purged and the CAM Full flag is de-asserted. Assume that STPURG was incremented 128 times. This would purge the oldest half of the time stamp values and thus, reduce the maximum age to half the previous 255. This is accomplished without changing STCURR. &5& DQG 2WKHU 'DWD ,QWHJULW\ &KH.NV For 10Base-X packets, a 32-bit cyclic redundancy check is calculated from the data frame (exclusive of the preamble and start frame delimiter) and compared to the frame check sequence (FCS). This check is only performed if the PCFG register for the appropriate port is set accordingly to enable the facility. Also, according to the MII interface specifications, the RX_ER, CRS, and COL signals are monitored and error conditions are recognized. If any error is identified, the source address is not processed. This is intended to maintain the integrity of the LANCAM database. 5HY   08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H 6RIWZDUH 0RGHO 62)7:$5( 02'(/ 6\VWHP 5HJLVWHUV One set of registers is available to address up to two MU9C8358L components and their attached LANCAMs as a single system. The application decodes one range of addresses to produce a Processor Chip Select System 7DEOH  6\VWHP 5HJLVWHUV 1DPH 667$7 66&)* 6'&)* 67$5* 6&': 6&': 6&': 6&': 67385* 67&855 60;6$'$&@ 6&': >@ 6&': >@ 6&': >@ 6'2B'(/(7( 6HTXHQ.H 0$&B$' >@ 0$&B$' >@ 0$&B$' >@ 1RW XVHG 2WKHU 5RXWLQHV $VVR.LDWHG GDWD 0$&B$' >@ 0$&B$' >@ 0$&B$' >@ During the LANCAM initialization and configuration process, SCDW0 is used with SLCCS to configure the LANCAMs. When SCDW0 is used to transfer associated data, the bit mapping is as shown. 7DEOH  6'&: $VVR.LDWHG 'DWD 5HJLVWHU 0DSSLQJ %LW V     1DPH 7LPHB6WDPS 3RUWB,' 5HVHUYHG 3HUPDQHQW 6\VWHP 7DUJHW 5HJLVWHU The System Target Register (STARG) allows the CPU to determine how events are to be handled. The INCR_PIN bits enable or disable to INCR hardware input. The EN_FF_INT bits enable or disable whether the LANCAM /FF output produces an interrupt when the LANCAM is full. 7DEOH  67$5* 6\VWHP 7DUJHW 5HJLVWHU 0DSSLQJ %LW V  1DPH ,1&5B3,1 'HV.ULSWLRQ     'LVDEOH ,1&5 SLQ 5(6(59(' 5(6(59(' (QDEOH ,1&5 SLQ 'LVDEOH ), LQWHUUXSW 5(6(59(' (QDEOH ), LQWHUUXSW 5(6(59(' 6\VWHP 7LPH 6WDPS 3XUJH 5HJLVWHU The System Time Stamp Purge register (STPURG) stores the purge time stamp value. It is a read-only register, but it may be incremented by writing an arbitrary value to the SDO_INCPR register. 7DEOH  67385* 6\VWHP 7LPH 6WDPS 3XUJH 5HJLVWHU 0DSSLQJ 1DPH 3XUJH 7LPH 6WDPS ,QLWLDO 9DOXH + /R.DWLRQ %LWV >@  (1B))B,17     6\VWHP 7LPH 6WDPS &XUUHQW 5HJLVWHU The System Time Stamp Current register (STCURR) stores the current time stamp value. It is a read-only register, but it may be incremented by writing an arbitrary value to the SDO_INCTS register. 7DEOH  67&855 6\VWHP 7LPH 6WDPS &XUUHQW 5HJLVWHU 0DSSLQJ 1DPH &XUUHQW 7LPH 6WDPS ,QLWLDO 9DOXH + /R.DWLRQ %LWV >@ 5HY   08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H 6\VWHP 0D[LPXP 6$'$ &\.OHV 5HJLVWHU This register establishes the number of clock cycles that DA and SA operations will take. This is based on the speed of the attached LANCAM components. 7DEOH  60;6$'$&@ 3&66 6@ ,1&5 '4>@ 352&B5'< ,175 3&6 53>@ 53B'9 53B6(/ 53B1;7 (& 08&/ 6/$9( : &0 ( 0, ), 7R &RQWURO +DUGZDUH 7R /$1&$0 V Figure 7: Cascading Two MU9C8358L Components 5HY   08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H &DV.DGLQJ /$1&$0V The MUSIC MU9Cx480B LANCAM family can be vertically cascaded to allow long station lists to be implemented. The MU9C8358L LANCAM interface timing allows up to four LANCAMs to be cascaded as shown in Figure 8. $SSOL.DWLRQV When LANCAMs are cascaded in this way, the system Full and Match flags are connected to the MU9C8358L /FI and /MI inputs respectively. Please refer to the LANCAM B Family data sheet for a comprehensive description of the device. '4>@ 0, 9.. ( : &0 (& 5(6(7 ), *QG /$1&$0  )) 0) '4>@ 0, ( : &0 (& 5(6(7 ), /$1&$0  )) 0) '4>@ 0, ( : &0 (& 5(6(7 ), /$1&$0  )) 0) '4>@ 0, ( : &0 (& 5(6(7 ), /$1&$0  )) 6\VWHP )XOO )ODJ 0) 6\VWHP 0DW.K )ODJ Figure 8: Cascading LANCAMs  5HY  $SSOL.DWLRQV 08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H %XLOW,Q 5RXWLQHV The MU9C8358L contains built-in LANCAM routines that perform all the necessary LANCAM operations. The DA and SA search routines are performed automatically by the device in order to provide the search result and Definitions: aaaaH = CAM Address value (Hexadecimal) ddddH = Data value (Hexadecimal) ppppH = CAM Page Address value (Hexadecimal) xxxxH = "Don’t Care" 'HVWLQDWLRQ $GGUHVV 6HDU.K 5RXWLQH /LQH      &0 + + + + + : / / / / / ( &\.OH 6KRUW 6KRUW 6KRUW /RQJ /RQJ (& + + + / + 0QHPRQL. '4  [[[[+ GGGG+ GGGG+ GGGG+ GGGG+ 'HV.ULSWLRQ 'XPP\ ZULWH WR 6HJPHQW  :ULWH VW  ELWV WR 6HJPHQW  :ULWH QG  ELWV WR 6HJPHQW  :ULWH UG  ELWV WR 6HJPHQW  DQG .RPSDUH 5HDG $VVR.LDWHG 'DWD ))))+ LV QR PDW.K update the address table. The other routines are invoked as described in Operational Characteristics: Built-in Routines. 6RXU.H $GGUHVV 6HDU.K 5RXWLQH /LQH     &0 + + + + : / / / / ( &\.OH 6KRUW 6KRUW 6KRUW /RQJ (& + + + / 0QHPRQL. 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Pins: FRX_ER_(A–D), /INTR, REJ_(A–D), /RESET_LC, RP_DV, TP_DV_(A–D), TP_SD_(A–D), TDO Pins: ARB[2:0], D[15:0], SYNC Pins: DQ[15:0], RP[15:0] Pins: PROC_RDY, /E Pins: /CM, /EC, /W Pins: TCK, TDI, TMS, and TRST have 50-kΩ (nom.) pull-ups Pins: ARB[2:0], DQ[15:0], /E, and SYNC have 50-kΩ (nom.) pull-ups Push/Pull Outputs: FRX_ER_(A-D), /INTR, REJ_(A-D), /RESET_LC, RP_DV, TP_DV_(A-D), and TP_SD_(A-D). 5HY   08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H 7LPLQJ 'LDJUDPV &DSD.LWDQ.H 6\PERO &,1 &287 3DUDPHWHU ,QSXW .DSD.LWDQ.H 2XWSXW .DSD.LWDQ.H 0D[   8QLWV S) S) 1RWHV I I  0+] 9,1  0+] 9287 9 9 7,0,1* ',$*5$06 7LPLQJ 'DWD IRU +RVW 3UR.HVVRU ,QWHUID.H 1R              6\PERO W3/'; W3+'= W:93/ W3/:; W&+'9 W'93+ W3+'; W&+35+ W$93/ W3/$; W3+3/ W3/35/ W35+35/ 3DUDPHWHU QV 3&6 3&66 /2: WR '  HQDEOH 3&6 3&66 +,*+ WR '  GLVDEOH :5,7( VHWXS WR 3&6 3&66 :5,7( KROG IURP 3&6 3&66 6@  YDOLG  LQYDOLG   53B1;7 Figure 12: Result Port - Additional Valid Data Packets 5HY   08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H 7LPLQJ 'DWD IRU 5;' 5;B'9 DQG 5;B(5 1R   6\PERO W5'95&/+ W5&&+5'; 3DUDPHWHU QV 'DWD VHWXS SULRU WR ULVLQJ 5;B&/. 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