MU9C8K64-35TDC

Datasheet MU9C RCP Family APPLICATION BENEFITS • • • • • Longest Prefix Match searches of IPv4 addresses 28 Million IPv4 packets per second supports up to 18 Gb Ethernet or 7 OC-48 ATM ports at wire speed Longest Prefix Match searches of IPv4 addresses Exact match on MAC addresses Processes DA and SA within 190 ns, supporting three ports of 1 Gb or 34 ports of 100 Mb Ethernet at wire speed Mixed mode L3 and L2 single search engine for two ports at 1 Gb or 29 ports of 100 Mb Ethernet at wire speed Directly addresses external RAM containing associated data of any width Hardware control states directly address memory and registers; Instruction and Status registers for optional software control DISTINCTIVE CHARACTERISTICS • • • • • • • • • • • • • • • 4K, 8K, 16K, 24K, and 32K x 64-bit words 32-bit ternary or 64-bit binary compares 35 ns deterministic compare and output time 32-bit Data I/O port 16-bit Match Address Output port Address/Control bus directly controls device operations for faster operation or higher throughput Seven selectable mask registers Synchronous operation Cascadable for increased depth Extensive set of control states for flexibility JTAG interface 4K and 8K; 100-pin LQFP package 16K, 24K, and 32K; 35mm BGA package 3.3 Volt operation Lead-free, fully RoHS compatible package available • • • DQ31-0 / VB /E / CS1 / CS2 /W / OE / AV AC Bus / DSC / RESET TCLK TMS TDI TDO / TRST CONTROL AND ADDRESS DECODER COMPARAND REGISTER MASK REGISTER 1-7 ADDRESS REGISTER CONFIGURATION REGISTER STATUS REGISTER INSTRUCTION REGISTER DEVICE SELECT REGISTER 4K 8K 16K 24K 32K x x x x x 64 Word (MU9C4K64) 64 Word (MU9C8K64) 64 Word (MU9C16K64) 64 Word (MU9C24K64) 64 Word (MU9C32K64) Address Database PRIORITY ENCODER AND FLAG LOGIC /FI /FF /M I /M F /M M PA3-0 AA Bus Figure 1: Block Diagram MUSIC Semiconductors, the MUSIC logo, and the phrase "MUSIC Semiconductors" are Registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of MUSIC Semiconductors. November 10, 2005 Rev. 8.04 MU9C RCP Family General Description GENERAL DESCRIPTION The MU9C RCP family consists of 4K, 8K, 16K, 24K, and 32K x 64-bit Routing Co-Processors (RCP’s) with a 32-bit wide data interface and a 32-bit ternary compare instruction. The device is designed for use in layer 3 switches, routers, and layer 2 switches to provide very high throughput address translation using tables held in external RAM. The MU9C RCP has a fully deterministic search time, independent of the size of the list and the position of the data in the list. This unique feature guarantees that the wire speed address recognition does not impact the latency or induce jitter on the latency of the global system. Address fields from the packet header are compared against a list of entries stored in the array. As a result of the comparison, the MU9C RCP generates an index that is used to access an external RAM where port mapping data and other associated information is stored. A set of control states provides a powerful and flexible control interface to the MU9C RCP. This control structure allows memory read and write, register read and write, data move, comparison, validity control, addressing control, and initialization operations. The MU9C RCP architecture uses direct hardware control of the device and an independent bus for returning match results. Software control is also supported for systems where maximum performance is not required. OPERATIONAL OVERVIEW The MU9C RCP is designed to act as an address translator for lookup tables in layer 3 switches, routers, and layer 2 switches. Refer to Figure 2 for a simplified block diagram of a switch. During normal operation, the controller extracts the address information from an arriving packet to form the comparand, which is then compared against the contents of the MU9C RCP. The MU9C RCP generates an index that is used to access the data in an external RAM, which holds the destination port for accessing the network. The controller reads the data from the RAM and forwards the packet. A unique feature of the MU9C RCP is its ternary comparison that processes IPv4 CIDR addresses in a single cycle. The bits of each MU9C RCP word are paired, such that each pair can contain two binary values (0,1) or one ternary (0,1,X= "Don't Care") value. A ternary value uses two bits, pairing bit n from the first 32 bits (31-0) with bit n+32. When storing a ternary 0 or 1, the value to be stored is written into bit n (0