MUAA2K80-30QGI

Data Sheet MUAA Routing CoProcessor (RCP) Family APPLICATION BENEFITS • High performance MAC Address processor for multiport switches and routers (Up to 48 10/100 or 4 Gigabit Ethernet at wire speed) Layer 4 flow recognition for Quality of Service up to 16.7 million packets per second ARP Cache manager/IP address caching at 12.5 million packets per second Synchronous interfaces and programmable priority between ports for simplicity of design Learn, age, and auto-age functions with “virtual queues,” keeping track of aged and learned entries Transparent cascade of up to four 2K devices without external logic, software setup, or performance hit DISTINCTIVE CHARACTERISTICS • • • • • 2K and 8K x 80-bit partitionable CAM/RAM data field in address database 32-bit synchronous port with separate inputs and outputs; optional 16-bit configuration 32-bit bi-directional processor port; optional 16-bit configuration Pipelined operation Operations performed from the synchronous port or processor port; all flags independently available to both ports 9-bit internal time stamp 50 MHz clock 388-pin PBGA (8K) and 160-pin PQFP (2K) packages. 3.3 Volt core with 3.3 Volt/5 Volt tolerant IO buffers. IEEE 1149.1 (JTAG) compliant • • • • • • • • • • Sync Port DIN(31:0) Processor Port DIN(31:0) 16/32 to 80-bit mux 16/32 to 80-bit mux 80-bit latch 80-bit latch DINREADY OP(3:0) /DINE 80-bit 2 to 1 mux PROCD(31:0) /FF PROCA(5:0) /PCS R/W PROCREADY INT /RESET CLK Control Address Data Base -- b i t 79 -- ------- ------- b i t 0--Flag and Chain Logic /MF CHAIN CHAINUP CHAINDN /CHAINCS /DOUTVALID /DOUTE /OE Processor Port DOUT(31:0) 80-bit la tch 80-bit la tch 80 to 32/16-bit mux 80 to 32/16-bit mux TDI TMS TCK TRST JTAG TDO Sync Port DOUT(31:0) Figure 1: Block Diagram MUSIC Semiconductors, the MUSIC logo, and the phrase "MUSIC Semiconductors" are Registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of MUSIC Semiconductors. March 26, 2003 Rev. 5 MUAA Routing CoProcessor (RCP) Family General Description GENERAL DESCRIPTION The MUSIC MUAA Routing CoProcessor (RCP) family consists of 80-bit wide content-addressable memories (CAMs), available in depths of 2K and 8K words. The CAM/RAM associated data partition is programmable from 32 bits of CAM and 48 bits of associated data, to 80 bits of CAM and 0 bits of RAM. The MUAA RCP can perform normal routing functions such as search, insert, and delete on single entries and can age multiple entries simultaneously. In addition, there is a learn instruction, particularly useful in networking applications. For maximum flexibility all the operations may be performed either through the processor port or through the synchronous port. Operations may occur on both ports simultaneously; the port with the highest priority will gain access first if both ports require a read or write into the CAM array simultaneously. The synchronous interface consists of 32-bit wide input and output ports, both of which may be configured as 16 bits. The data is multiplexed into and out of the CAM and RAM associated data field. Where input or output data is wider than the port, it is loaded or unloaded in multiple cycles starting with the least significant word. Internally the device is pipelined; once an operation is started on the synchronous port the next operation may be loaded and the results of the previous operation unloaded, thus maximizing device throughput. Multiple 2K MUAA RCPs may be chained transparently to provide deeper memory. No software configuration is necessary. Each MUAA RCP detects where it is in the chain from the chaining pins on the previous device. A register is provided to inform the host of the total available CAM memory and the number of CAMs chained. All operations to the chained CAM are totally transparent. No individual device selection or addressing is required. The MUSIC MUAA RCP has aging, auto-aging, and learning functions. All entries have a 9-bit time stamp and may be marked as static to prevent the aging function from deleting them. When auto aging is enabled it may be configured to have higher or lower priority access than the ports. Two internal virtual queues of learned and aged entries are available. As entries are learned or aged out they are tagged as such and may be read from the device through either of the ports. This feature enables simple host management of aged out and learned entries. IEEE Standard. 1149.1 (JTAG) testability is implemented providing BYPASS, SAMPLE/PRELOAD, EXTEST, CLAMP, and HIGH-Z functions. 2 Rev. 5 Pin Descriptions MUAA Routing CoProcessor (RCP) Family PIN DESCRIPTIONS Note: Signal names that start with a slash (“/”) are active LOW. All signals are 3.3 Volt CMOS level. All input and bi-directional pins are 5-Volt tolerant, except for CLK. Never leave inputs floating except where indicated. The CAM architecture draws large currents during search operations, mandating the use of good layout and bypassing techniques. Refer to the Electrical Characteristics section for more information. See Table 1 for the 388-pin balls and the Packages section for the chip illustrations. VCC DOUT0 GND DIN31 DIN30 DIN29 DIN28 DIN27 GND DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 VCC DIN20 DIN19 DIN18 DIN17 DIN16 DIN15 DIN14 GND DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 VCC DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 GND 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 GN D DOUT1 DOUT2 DOUT3 DOUT4 VCC DOUT5 DOUT6 DOUT7 GN D DOUT8 DOUT9 DOUT10 DOUT11 VCC DOUT12 DOUT13 DOUT14 DOUT15 GN D DOUT16 DOUT17 DOUT18 DOUT19 VCC DOUT20 DOUT21 DOUT22 DOUT23 GN D DOUT24 DOUT25 DOUT26 DOUT27 VCC DOUT28 DOUT29 DOUT30 DOUT31 GN D 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 160-Pin PQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VCC CH A IND N CH A INUP GN D CH A IN3 CH A IN2 CH A IN1 CH A IN0 GN D CH AI NCS PROCD31 PROCD30 PROCD29 PROCD28 PROCD27 PROCD26 PROCD25 PROCD24 VCC PROCD23 PROCD22 PROCD21 PROCD20 PROCD19 PROCD18 GN D PROCD17 PROCD16 PROCD15 PROCD14 PROCD13 PROCD12 VCC PROCD11 PROCD10 PROCD9 PROCD8 PROCD7 PROCD6 GN D DIN[31:0] (Input) DIN[31:0] are synchronous port data input pins. Data is loaded into the MUAA RCP right aligned, least significant word first. /DINE (Input) DIN is sampled by the rising edge of CLK when /DINE is asserted. Refer to Table 1 for slave connections. OP[3:0] (Input) OP[3:0] is a synchronous port operation to be performed on the data applied to the DIN pins. OP is sampled by the rising edge of CLK when /DINE is asserted. When loading the CAM/RAM words to DIN, OP is set to LOAD except for the last word. OP for the last word is set to the desired operation. Rev. 5 VCC CLK GND /MF /FF /DOUTVALID DINREADY INT PROCREADY TDO GND TDI TMS TCK /TRST /OE /DOUTE /DINE OP0 OP1 OP2 OP3 VCC PROCA0 PROCA1 PROCA2 PROCA3 PROCA4 PROCA5 R/W /PCS /RESET GND PROCD0 PROCD1 PROCD2 PROCD3 PROCD4 PROCD5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Figure 2: 160-Pin PQFP (Top View) DINREADY (Output) When DINREADY is HIGH, the synchronous port accepted the current operation. This is affected by the priority set for the DIN port and the processor port. Note, DINREADY may be LOW for up to 800 CLK periods after /RESET is taken HIGH. The JTAG interface is able to set DINREADY to HIGH-Z. Active HIGH. DOUT[31:0] (3-State Output) DOUT[31:0] is the synchronous port data output. Data is read out right aligned, least significant word first. The address index (bits 25–0), SWEX flag (bit 26), PWEX flag (bit 27), LQUEUE flag (bit 28), AQUEUE flag (bit 29), Sync Port Match flag (bit 30), and Full flag (bit 31) may also be read from this port before or after operation data depending on configuration. 3 MUAA Routing CoProcessor (RCP) Family Pin Descriptions /DOUTVALID (Output) /DOUTVALID indicates when new data is available at the synchronous output port. /DOUTVALID is active LOW for one CLK cycle. /DOUTVALID may be configured to become active on the same clock as new DOUT becomes valid or the CLK before. The JTAG interface is able to set /DOUTVALID to HIGH-Z. /OE (Input) /OE is the DOUT High Impedance control. /DOUTE (Input) /DOUTE is the DOUT enable control. When the DOUT data word is configured to be wider than the output port then this strobe enables the next word(s) of the DOUT data onto the DOUT pins. PROCD[31:0] (Bi-directional) The bi-directional Processor data port provides the processor interface to the device. On write cycles all devices respond in parallel. On read cycles the appropriate device responds without additional intervention from the processor. PROCA[5:0] (Input) Processor port address bus. Selects which device register is accessed. Bit 0 is only used when the port is set to 16-bit mode, otherwise it should be held at a valid logic level. R/W (Input) R/W is the processor port read/write control pin. This pin is HIGH for reads, LOW for writes. /PCS (Input) /PCS is the processor port chip select pin. When LOW this pin indicates a cycle to the processor port. On write cycles data must be set up to the rising edge of /PCS. On read cycles /PCS controls the output enable of the PROCD bus. Note that /PCS may be asynchronous to CLK. Refer to Table 1 for slave connections. PROCREADY (Output) When PROCREADY is HIGH, indicates the processor read data is available or the processor write data is accepted. Priority may be set between the DIN port and the processor port. Note PROCREADY may be LOW for up to 800 CLK periods after /RESET is taken HIGH. The JTAG interface is able to set PROCREADY to HIGH-Z. INT (Output) INT interrupt. Indicates the aged or learned queue has at least one entry or a write exception occurred. The service routine should either check the AQUEUE, LQUEUE, and WEX registers, or bits 26–29 of the Address Index register, to determine the cause. The interrupt is cleared after the appropriate flag register has been read and will not be reasserted until either the queue(s) are emptied and 4 then get at least one entry again, or another write exception occurs. The JTAG interface is able to set INT to HIGH-Z. /RESET (Input) The /RESET input is used to reset the MUAA RCP. /RESET must be asserted for at least 3 CLK periods. CLK (Input) The rising edge of CLK input is the device clock. /FF (Full Flag, Output) /FF is active when the device (or chain of devices) is full. /FF becomes inactive when any one device has two open entries. The JTAG interface is able to set /FF to HIGH-Z. CHAIN[3:0 (Input) When two or more devices are chained they communicate among themselves using the CHAIN[3:0] signals. See Chaining section. Internally Pulled-up. Refer to Table 1 for slave connections. CHAINUP (Output) When two or more devices are chained they communicate among themselves using the CHAINUP signals. See Chaining section. The JTAG interface is able to set CHAINUP to HIGH-Z. Refer to Table 1 for slave connections. CHAINDN (Output) When two or more devices are chained they communicate among themselves using the CHAINDN signals. See Chaining section. The JTAG interface is able to set CHAINDOWN to HIGH-Z. Refer to Table 1 for slave connections. CHAINCS (Bi-directional) When two or more devices are chained they communicate among themselves using the CHAINCS signals. See Chaining section. Internally pulled up. Refer to Table 1 for slave connections. /MF (Match Flag, Output) The /MF output indicates whether a match was found. The JTAG interface is able to set /MF to HIGH-Z. /TRST (JTAG Reset, Input) The /TRST is the Test Reset pin. Internally pulled up with 25K minimum. Must be tied to /RESET or tied LOW when not in use. /TCLK (JTAG Test Clock, Input) The /TCLK input is the Test Clock input. Must be tied at a valid logic level when not in use. TMS (JTAG Test Mode Select, Input) The TMS input is the Test Mode Select input. Internally pulled up with 25K minimum. Rev. 5 Pin Descriptions MUAA Routing CoProcessor (RCP) Family TDI (JTAG Test Data Input, Input) The TDI input is the Test Data input. Internally pulled up with 25K minimum. Refer to Table 1 for slave connections. TDO (JTAG Test Data Output, Output) The TDO output is the Test Data output. Refer to Table 1 for slave connections. VCC, GND These pins are the power supply connection to the MUAA RCP. VCC must meet the voltage supply requirements in the Operating Conditions section relative to the GND pins, which are at 0 Volts (system reference potential), for correct operation of the device. All the ground and power pins must be connected to their respective planes with adequate bulk and high frequency bypassing capacitors in close proximity to the device. Ball Descriptions Table 1: Ball Descriptions Functional Group Synchronous Input Port Ball Name(s) DIN[31:0] Function Synchronous port data input. Type Input 5V tol PBGA Ball(s) b0:AA26, b1:AA25, b2:Y26, b3:Y25, b4:W26, b5:W25, b6:V26, b7:V25, b8:U26, b9:U25, b10:T26, b11:T25, b12:R26, b13:R25, b14:P26, b15:P25, b16:N26, b17:N25, b18:M26, b19:M25, b20:L26, b21:L25, b22:K26, b23:K25, b24:J26, b25:J25, b26:H26, b27:H25, b28:G26, b29:G25, b30:F26, b31:F25 T1 T2 R2 P2 b0:U1, b1:U2, b2:U3, b3:T3 H1 /DINE /DINE-S1 /DINE-S2 /DINE-S3 OP[3:0] DINREADY CLK Synchronous Output Port DOUT[31:0] When asserted, DIN is sampled by the rising edge of CLK. Connect to T2, R2, and P2. Slave 1. Connect to T1, /DINE. Slave 2. Connect to T1, /DINE. Slave 3. Connect to T1, /DINE. Synchronous port operation performed on data applied to DIN pins. When HIGH, indicates the synchronous port accepted the current operation. Rising edge is the device clock. Synchronous port data output. Input 5V tol Input 5V tol Input 5V tol Input 5V tol Input 5V tol Output Input D1 3.3V only Output b0:A21, b1:B21, b2:A20, b3:B20, b4:A19, b5:B19, b6:A18, b7:B18, b8:A17, b9:B17, b10:A16, b11:B16, b12:A15, b13:B15, b14:A14, b15:B14, b16:A13, b17:B13, b18:A12, b19:B12, b20:A11, b21:B11, b22:A10, b23:B10, b24:A9, b25:B9, b26:A8, b27:B8, b28:A7, b29:B7, b30:A6, b31:B6 G1 P1 R1 E1 /DOUTVALID /OE /DOUTE /MF Indicates when new data is available at the synchronous output port. DOUT high impedance control. DOUT enable control. Match flag. Indicates if a match was found. Output Input 5V tol Input 5V tol Output Rev. 5 5 MUAA Routing CoProcessor (RCP) Family Pin Descriptions Table 1: Ball Descriptions (continued) Functional Group Processor Port Ball Name(s) PROCD[31:0] Processor port data. Function Type Bidir 5V tol PBGA Ball(s) b0:AB1, b1:AB2, b2:AC1, b3:AC2, b4:AF3, b5:AE3, b6:AF4, b7:AE4, b8:AF5, b9:AE5, b10:AF6, b11:AE6, b12:AF7, b13:AE7, b14:AF8, b15:AE8, b16:AF9, b17:AE9, b18:AF10, b19:AE10, b20:AF11, b21:AE11, b22:AF12, b23:AE12, b24:AF13, b25:AE13, b26:AF14, b27:AE14, b28:AF15, b29:AE15, b30:AF16, b31:AE16 b0:W1, b1:W2, b2:W3, b3:Y1, b4:Y2, b5:Y3 V2 AA1 AA2 AA3 AB3 K1 J1 V1 F1 PROCA[5:0] R/W /PCS /PCS-S1 /PCS-S2 /PCS-S3 PROCREADY INT /RESET /FF Processor port address bus. Processor port read/write control Processor port chip select. Connect to AA2, AA3, and AB3. Slave 1. Connect to AA1, /PCS. Slave 2. Connect to AA1, /PCS. Slave 3. Connect to AA1, /PCS. When HIGH, indicates the processor read data is available or the processor write data is accepted. INT interrupt. Indicates the aged or learned queue has at least one entry or a write exception occurred. Resets the MUAA RCP . Full flag. Active when the device (or chain of devices) is full Input 5V tol Input 5V tol Input 5V tol Input 5V tol Input 5V tol Input 5V tol Output Output Input 5V tol Output 6 Rev. 5 Pin Descriptions MUAA Routing CoProcessor (RCP) Family Table 1: Ball Descriptions (continued) Functional Group Cascade Ball Name(s) CHAIN0 CHAIN1 CHAIN2 CHAIN3 CHAIN0D CHAIN1D CHAIN2D CHAINUP CHAINUP-S1 CHAINUP-S2 CHAINUP-S3 CHAINDN CHAINDN-S1 CHAINDN-S2 CHAIND-S3 CHAINCS CHAINCS-S1 CHAINCS-S2 CHAINCS-S3 CHAIN1X CHAIN2X CHAIN3X JTAG /TRST TCLK TMS TDI TDI-A TDI-B TDI-C TDO TDO-A TDO-B TDO-C Power 3.3V Function NC. For MUSIC production test only. Internal chaining. Connect to AE19, CHAINUP-S1. Internal chaining. Connect to AE20, CHAINUP-S2. Internal chaining. Connect to AE21, CHAINUP-S3. Internal chaining. Connect to AF23, CHAINDN. Internal chaining. Connect to AE23, CHAINDN-S1. Internal chaining. Connect to AD23, CHAINDN-S2. NC. For MUSIC production test only. Internal chaining. Connect to AF19, CHAIN1. Internal chaining. Connect to AF20, CHAIN2. Internal chaining. Connect to AF21, CHAIN3. Internal chaining. Connect to AE22, CHAIN0D. Internal chaining. Connect to AD22, CHAIN1D. Internal chaining. Connect to AC22, CHAIN2D. NC. For MUSIC production test only. Internal chaining. Connect to AE17, AD17, and AC17. Internal chaining. Connect to AF17. Internal chaining. Connect to AF17. Internal chaining. Connect to AF17. NC. For MUSIC production test only. NC. For MUSIC production test only. NC. For MUSIC production test only. Test reset. Test clock input. Test mode select. Test data input. Internal JTAG chain. Connect to L2, TDO-A. Internal JTAG chain. Connect to L3, TDO-B. Internal JTAG chain. Connect to L3, TDO-C. Test data output. Internal JTAG chain. Connect to M2, TDI-A. Internal JTAG chain. Connect to M3, TDI-A. Internal JTAG chain. Connect to M4, TDI-A. Device power, 3.3 volts. Type Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Bidir Bidir Bidir Bidir Input Input Input Input Input Input Input Input Input Input Output Output Output Output N/A AF18 AF19 AF20 AF21 AE22 AD22 AC22 AF22 AE19 AE20 AE21 AF23 AE23 AD23 AC23 AF17 AE17 AD17 AC17 AE18 AD18 AC18 N3 N2 N1 M1 M2 M3 M4 L1 L2 L3 L4 AD7, AD8, AD13, AD14, AD19, AD20, AC7, AC8, AC13, AC14, AC19, AC20, Y4, Y23, Y24, W4, W23, W24, R3, R4, R12, R13, R14, R15, P3, P4 P12, P15, P23, P24, N12, N15, N23, N24, M12, M13, M14, M15, H23, H24, G23, G24, D6, D7, D10, D11, D15, D16, D20, D21, C6, C7, C10, C11, C15, C16, C20, C21 PBGA Ball(s) Rev. 5 7 MUAA Routing CoProcessor (RCP) Family Operational Characteristics Table 1: Ball Descriptions (continued) Functional Group Ground Ball Name(s) GND Device ground. Function Type N/A PBGA Ball(s) AF1, AF2, AF24, AF25, AF26 AE1, AE2, AE24, AE25, AE26 AD1–AD6, AD9– AD12, AD15, AD16, AD21, AD24, AD25, AD26, AC3–AC6, AC9–AC12 AC15, AC16, AC21, AC24–AC26, AB4, AB23–AB26, AA4, AA23, AA24, V3, V4, V23, V24, U4, U23, U24, T4, T11–T16, T23, T24, R11, R16, R23, R24, P11, P13, P14, P16, N4, N11, N13, N14, N16, M11, M16, M23, M24, L11–L16, L23, L24, K23, K24 J23, J24, F23, F24, E23–E26, D2–D5, D8, D9, D12–D14, D17–D19, D22–D26, C1–C5, C8, C9, C12–C14, C17–C19, C22– C26, B1–B5, B22–B26, A1–A5, A22–A26 OPERATIONAL CHARACTERISTICS Loading and Unloading In order to keep data alignment simple, the number of words to be loaded and unloaded for each operation is kept consistent for each CAM/RAM partition configuration and the width of the port. Tables 2 and 3 show the cycle sequence and CAM/RAM bit mappings for 32- and 16-bit bus modes. The bus may be selected for each port independently. Table 4 shows whether CAM, RAM or both types of segments are used on input or output cycles for each operation. Loads always start right aligned from the least significant word, CAM partition first, followed by RAM if necessary. Most instructions do not require the entire 80 bits to be loaded. CAM data is required as an input for all operations except READ LQUEUE and READ AQUEUE. The use of RAM data is optional (i.e., it is not necessary to perform all RAM cycles when inputting data). However, the user must be aware that INSERT and LEARN operations will over-write RAM data. Therefore, the application should remain consistent in the number of RAM bits used for these operations. All CAM and RAM segment writes except the last use the LOAD instruction. The last segment of data uses the instruction for the desired operation. Depending on the operation, unloads either start from the right aligned, least significant word of CAM followed by the right aligned, least significant word of RAM or just from the right aligned, least significant word of RAM. For instance, a QUEUE read returns CAM then RAM, whereas a search just returns RAM. Where the CAM/RAM partition does not lie on a port width boundary the last word of the read may contain undefined data in the most significant bits. The number of unload cycles actually completed is optional. The DOUT register stores the results of operations from the asynchronous processor port. Search results are obtained by repeated reads of DOUT until all RAM data is read. When performed from the processor port, READ LQUEUE and READ AQUEUE return the first segment of CAM data on the cycle that requests the operation; additional CAM and RAM segments are obtained by repeated reads of the DOUT register. Loading is flow controlled on the synchronous DIN port with the DINREADY signal, which is HIGH when data is accepted by the DIN port. On the Processor port the PROCREADY signal is HIGH when the current write cycle may complete. 8 Rev. 5 Operational Characteristics MUAA Routing CoProcessor (RCP) Family Operations On the synchronous port, operations are started on the CLK cycle in which the requested Op-Code is written. On the processor port operations are started when the chosen operation register is written. The user should use the flow control mechanisms to determine when results are available. On the synchronous port the /DOUTVALID signal is asserted for one CLK cycle when new data is written to the DOUT port. The processor port will assert its PROCREADY signal on the CLK edge that data is available. Note that there is no internal flow control from the sync DOUT port back to the sync DIN port. The DOUT data is overwritten if it is not unloaded. Table 2: 32-Bit Bus Mode CAM/RAM Cycles by Partition Configuration Cycle 1 2 3 No RAM 79:0 CAM CAM[31:0] CAM[63:32] CAM[79:64]* 79:64 RAM 63:0 CAM CAM[31:0] CAM[63:32] RAM[79:64]* 79:48 RAM 47:0 CAM CAM[31:0] CAM[47:32]* RAM[79:48] 79:32 RAM 31:0 CAM CAM[31:0] RAM[63:32] RAM[79:64]* Note: *Bus bits [15:0] contain data. Bus bits [31:16] are undefined. Table 3: 16-Bit Bus Mode CAM/RAM Cycles by Partition Configuration Cycle 1 2 3 4 5 No RAM 79:0 CAM CAM[15:0] CAM[31:16] CAM[47:32] CAM[63:48] CAM[79:64] 79:64 RAM 63:0 CAM CAM[15:0] CAM[31:16] CAM[47:32] CAM[63:48] RAM[79:64] 79:48 RAM 47:0 CAM CAM[15:0] CAM[31:16] CAM[47:32] RAM[63:48] RAM[79:64] 79:32 RAM 31:0 CAM CAM[15:0] CAM[31:16] RAM[47:32] RAM[63:48] RAM[79:64] Table 4: Input and Output CAM/RAM Cycles by Operation Operation INSERT SEARCH SEARCHA LEARN DELETE READ LQUEUE READ AQUEUE DIN, PROCD (Write) CAM & RAM CAM only CAM only CAM & RAM CAM only N/A N/A DOUT, PROCD (Read) N/A RAM only RAM only N/A N/A CAM & RAM CAM & RAM Device Chaining Up to four MUAA 2K RCPs may be chained with no external logic. Figure 3 shows the interconnection. Unused CHAIN[3:0] pins should be left unconnected. The /MF, /FF, INT, DOUTVALID, DINREADY, and PROCREADY signals should only be used on the master device and left disconnected on the slave devices. The master device is the one with no connection to the CHAINUP pin. Where device pins are paralleled, attention should be paid to signal integrity, in particular to signals used for clocking, i.e., CLK, /PCS. PCB layout techniques such as daisy chaining and driver to track impedance matching should be observed. The scheme in Figure 3 allows devices to be designed in but not fitted. The fit order would be MASTER, SLAVE1, SLAVE2, SLAVE3. Rev. 5 9 MUAA Routing CoProcessor (RCP) Family Operational Characteristics DIN(31:0) DINE OP(3:0) DOUT(31:0) /OE /DOUTE PROCD(31:0) PROCA(5:0) R/W /PCS CLK /RESET DIN(31:0) DINE OP(3:0) DOUT(31:0) /OE /DOUTE PROCD(31:0) PROCA(5:0) R/W /PCS CLK /RESET DIN(31:0) DINE OP(3:0) DOUT(31:0) /OE /DOUTE PROCD(31:0) PROCA(5:0) R/W /PCS CLK /RESET DIN(31:0) DINE OP(3:0) DOUT(31:0) /OE /DOUTE PROCD(31:0) PROCA(5:0) R/W /PCS CLK /RESET SLAVE 3 SLAVE 2 SLAVE 1 DINREADY /DOUTVALID PROCREADY INT /FF /MF MASTER CHAIN(0) CHAIN(1) CHAIN(2) CHAIN(3) CHAINCS CHAINUP CHAINDN CHAIN(0) CHAIN(1) CHAIN(2) CHAIN(3) CHAINCS CHAINUP CHAINDN CHAIN(0) CHAIN(1) CHAIN(2) CHAIN(3) CHAINCS CHAINUP CHAINDN CHAIN(0) CHAIN(1) CHAIN(2) CHAIN(3) CHAINCS CHAINUP CHAINDN Figure 3: Device Chaining (2K only) 10 Rev. 5 Operational Characteristics MUAA Routing CoProcessor (RCP) Family Interrupts There are four sources of interrupts that will cause the INT pin to be asserted: AQUEUE, LQUEUE, SWEX, and PWEX. The appropriate enables must be set in the Configuration register to enable the interrupts. The interrupt service routine should read the appropriate flag registers to determine the interrupt cause. The flags are available individually or from the Address Index register. The appropriate individual flag register must be read in order to acknowledge the interrupt. LQUEUE and AQUEUE AQUEUE and LQUEUE interrupts are set by an entry being written into one or another of the queues. When the flag register is read the interrupt is acknowledged. The processor may read the LQUEUE and AQUEUE flags to determine when all the entries are read from the appropriate queue. The interrupt will not be reasserted until a queue has been emptied and then gets another entry. Note that it is possible for learned entries to be aged and aged entries to be learned. If this occurs the AQUEUE and LQUEUE flags may be set for an entry that has changed Table 5: JTAG Functions ID Binary HEX Description 0011 3 Version 1010 A MUAA 1010 A 0000 0 2K 0010 2 status. The user may qualify reads from AQUEUE and LQUEUE with the appropriate ports match flag that will be asserted if the data is valid. SWEX and PWEX SWEX and PWEX interrupts are set when a write exception condition occurs. This occurs when two Write cycles are pending in the device and there is only one space left. The SWEX and PWEX flags indicate which port caused the exception and which are available individually to the processor. Both processor write exceptions are available in the processor Address index port and the DOUT port Address index word. JTAG Please refer to IEEE Standard 1149.1 for information on using the JTAG functions. See Table 5 for JTAG functions. A BSDL file is available; check the MUSIC Semiconductors website or contact MUSIC Technical Support. JTAG Codes 0001 1 0011 3 MANUF ID 0011 3 EXT TEST BYPASS SAMPLE ID CODE CLAMP HIGH-Z 0000 1111 0001 0010 0100 0011 Typical Example This typical example shows the cycles that the MUAA RCP would perform in a multiport switch. The CAM/RAM partition is set to 48 bits CAM, 32 bits RAM. Both the processor port and the synchronous port are 32 bits wide. The index and flags are programmed to be the last word out of the DOUT port. The synchronous port has priority. The LQUEUE and AQUEUE are enabled. The CAM partition is used to store 48-bit MAC addresses and the RAM partition used to store associated data to the MAC address such as switch port and VLAN numbers. Sync Port Cycle 1 is a search to lookup the port associated with a frame DA (Destination address). At CLK1 the first word (32 bits) of CAM search word is loaded. At CLK2 the last 16 bits of CAM search word is loaded and the instruction “search” given. The most significant 16 bits of the second word are discarded as the CAM partition is 48 bits wide. The results from the DA search will not be available until CLK6 because the operation takes three Rev. 5 CLK periods to complete. Due to the internal design of the MUAA RCP, pipelining is possible; therefore, further operations can be performed while the DA search is being done internally. Sync Port cycle2 is a learn on a frame SA (Source address). At CLK3 the first word of CAM is loaded, at CLK4 the second word is loaded (most significant 16 bits discarded). At CLK5 the learn instruction is given along with the word of RAM data that would contain the port ID and other data associated with the SA. At CLK6 the results of the search instruction issued in cycle1 are available at the DOUT bus of the synchronous port, as indicated by /DOUTVALID going active for a CLK. The result of this cycle was a no-match condition as /MF was not asserted LOW. Because the cycle was a DA search and there was a no-match result, there will be no data available on the DOUT bus. Typically in this situation a switch would forward the frame to all ports or all ports on the same VLAN. 11 MUAA Routing CoProcessor (RCP) Family Operational Characteristics Sync Port cycle3 starts at CLK8, which is the DA search of the next frame. AT CLK 10 the results of the cycle2 learn operation are available. /MF was not asserted LOW; therefore the 48-bit CAM partition data was not found during the compare. The MUAA RCP automatically writes the 80-bit CAM/RAM word into the next free location of the memory array along with the most up to date time stamp or entry life. The address index is available from the DOUT bus to indicate where in the memory array the data was placed. This can be used to implement further associated data in software or hardware. Furthermore, the INT output is asserted to indicate that the “learned” word was entered into the LQUEUE. Sync Port cycle4, which is the SA learn of the same frame as Sync Port cycle3, is initiated at CLK10. The processor can also be used to access the MUAA RCP for general housekeeping duties. The LQUEUE contains the contents of the virtual learned queue. A processor cycle is started around CLK12 to read the LQUEUE register. This cycle is unable to be completed because the CAM core is busy servicing the synchronous port. PROCREADY remains inactive to inform the processor of the delay. The cycle is therefore extended and will complete when the MUAA RCP asserts PROCREADY HIGH. /MF is asserted LOW to indicate a match result on the CAM partition compare. At this point DOUT will be used to transfer the associated data and the address index of the matching condition. The associated data is available first (RAM partition) and would normally contain the port ID in a typical switch. The RAM partition is configured as 32 bits wide and can therefore be transferred in one CLK period. /DOUTE is asserted by the user to transfer the next word of data on the next clock period. As the RAM takes only one cycle, the address index is available after the associated data. The result of cycle4, which was a SA learn, is available at CLK17. The learn instruction produced a match result. There was no need to overwrite the CAM/RAM partitions, but the MUAA RCP automatically updated the time stamp or entry life of the matching entry. The address index of the entry becomes available at the DOUT port. The processor cycle data requested earlier, can now become available at CLK21. PROCREADY is asserted HIGH by the device to indicate that the cycle may be completed. The first 32-bit word is available on the PROCD bus and can be read by the processor. The two remaining 32-bit words that complete the LQUEUE entry are read by the subsequent processor cycles. These cycles do not require access to the CAM core, hence the 12 PROCREADY signal is asserted immediately once the cycle is initiated. The processor may use the LQUEUE data to maintain a management database of MAC addresses and associated port IDs. Back to back DA searches are shown from CLK25 onward. This is to demonstrate how the synchronous port handshaking works using the /DINREADY output. Sync port cycle5 and cycle6 are completed normally but at CLK29 /DINREADY goes LOW to indicate that the MUAA RCP cannot accept the load operation of sync cycle7. Therefore the host must hold the DIN, OP, and DINE signals active until /DINREADY goes HIGH. At this point the MUAA RCP will return /DINREADY to HIGH to indicate that it has accepted the DIN and OP information. Rev. 5 Rev. 5 1 2 3 15 16 17 18 22 24 25 26 4 5 6 7 8 9 10 11 12 13 14 20 21 23 27 28 29 30 32 33 31 34 35 36 37 cam1 cam1 cam2 cam2 ram2 cam3 cam3 cam4 cam4 cam4 cam5 cam5 cam6 cam6 cam7 cam7 cam8 cam8 load1 search1 load2 load2 learn2 load3 search3 load4 load4 learn4 load5 search 5 load6 search 6 load7 search 7 load8 search 8 no match 6 no match 1 match 3 match 4 no match 2 match 5 no match 7 index2 ram3 index3 index4 ram5 index5 valid1 valid2 valid3 valid4 valid5 valid6 valid7 learn 2 in queue cam2 lqueue lqueue cam2 lqueue ram2 lqueue addr lqueue addr lqueue addr Operational Characteristics CLK /DINE DIN(31:0) OP(3:0) DINREADY /MF DOUT(31:0) /DOUTVALID Figure 4: Example Sequence 13 /DOUTE /OE INT /PCS PROCD(31:0) PROCA(5:1) R/W MUAA Routing CoProcessor (RCP) Family PROCREADY MUAA Routing CoProcessor (RCP) Family Instruction Set Descriptions INSTRUCTION SET DESCRIPTIONS Mnemonic: NOOP Binary Op-Code: 0 CLKS: 3 Function: No operation. Mnemonic: load Binary Op-Code: 1 CLKS: 1 Function: Load a word of the DIN data, starting with the least significant word. This instruction is applied to all words loaded into the DIN port except the last word. The last word is loaded with the Op-Code of the operation to be performed. Refer to the Loading and Unloading section. Mnemonic: insert Binary Op-Code: 2 CLKS: 4 Function: Write DIN into the CAM/RAM. If data exists in the CAM partition already, the RAM partition will be overwritten with the new RAM partition data. The entry will be marked as permanent. The address index may be read from the output ports. See Note 1 regarding write exception. Mnemonic: search Binary Op-Code: 3 CLKS: 3 Function: Search for data in the CAM partition of DIN. If data is found the match flag is asserted and RAM data will appear at DOUT. The address index and flags may also be read. Mnemonic: searcha Binary Op-Code: 4 CLKS: 4 Function: Search for data in the CAM partition of DIN. If data is found the match flag is asserted and RAM data will appear at DOUT and the age of the entry is updated. The address index and flags may also be read. Mnemonic: learn Binary Op-Code: 5 CLKS: 4 Function: Search for data in the CAM partition of DIN. If data is found, the match flag is asserted and the RAM partition written. The address index may be read. Update the age. If data is not found, write the CAM and RAM partitions to the next free address. The address index may be read. See Note 1 regarding write exception. Mnemonic: delete Binary Op-Code: 6 CLKS: 3 Function: Search for data on the CAM partition of DIN. If data is found delete the data. The address index may be read. Mnemonic: age Binary Op-Code: 7 CLKS: 3 Function: If the aged virtual queue is disabled: This instruction will remove all entries whose life has expired and are not marked as permanent. Removed entries will not participate in future searches. If the aged virtual queue is enabled: This instruction will move all entries whose life has expired to the aged virtual queue. If a learn instruction matches the CAM partition of an entry in the aged virtual queue, the entry is moved to the learned virtual queue and the new RAM data written. Mnemonic: clear Binary Op-Code: 8 CLKS: 3 Function: Reset array to empty. Mnemonic: clear LQUEUE Binary Op-Code: 9 CLKS: 3 Function: Delete the contents of the learned virtual queue. The entry will not generate a match on a SEARCH or SEARCHA operation. Mnemonic: clear AQUEUE Binary Op-Code: 10 CLKS: 3 Function: Delete the contents of the aged virtual queue, if enabled. Mnemonic: read LQUEUE Binary Op-Code: 11 CLKS: 3 Function: Read the next learned queue entry. Entries are returned in internal priority order, lowest address first, not in the order they were written. The address index may be read. Note that entries do not have to be read from the LQUEUE if deemed unnecessary. The device treats learned entries as if they are valid entries. Mnemonic: read AQUEUE Binary Op-Code: 12 CLKS: 4 Function: This instruction is available only if the AQUEUE is enabled. Read the next aged queue entry. Entries are returned in internal priority order, lowest address first, not in the order they were written. The address index may be read. Notes: 1. Due to the pipelined nature of the device, it is possible for a write cycle to be pending (learn or insert) when the device is full. A write exception interrupt will indicate when this occurs if enabled. See Interrupt section. There is one CLK of latency to start the pipe on the synchronous port. The number of CLKs per instruction assumes the pipe is kept full and indicates throughput. 2. 14 Rev. 5 Instruction Set Descriptions MUAA Routing CoProcessor (RCP) Family Processor Port Registers Table 6: Processor Port Registers Register/Instruction NOOP load insert search searcha learn delete age clear clear LQUEUE clear AQUEUE read LQUEUE read AQUEUE DOUT PROCA[5:0] 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A Bit(s) 31:0 W 31:0 W 31:0 W 31:0 W 31:0 W 31:0 W 31:0 W N/A W N/A W N/A W N/A W 31:0 R 31:0 R 31:0 R Function NOOP operation Perform load operation. Perform insert operation. Perform search operation. Perform searcha operation. Perform learn operation. Perform delete operation. Age MUAA RCP contents. Perform clear operation. Perform clear LQUEUE operation. Perform clear AQUEUE operation. Read LQUEUE data. Read AQUEUE data. After an operation has been performed on the processor port the output data may be read and unloaded from this port. Data is read right aligned least significant word first. Processor port width. If set to 16-bit mode the most significant 16 bits of each register are addressed by bit 0 of the address pins. After reset, the Configuration register must be written before any other, 0 = 32-bit, 1 = 16-bit. Resets to 0. Sync port input width. 0 = 32-bit; 1 = 16-bit. Resets to 0. Sync port output width. 0 = 32-bit; 1 = 16-bit. Resets to 0. CAM/associated data partition point 0 = 79:0 CAM 1 = 79:64 RAM 63:0 CAM 2 = 79:48 RAM 47:0 CAM 3 = 79:32 RAM 31:0 CAM Resets to 0 DOUTVALID Timing. 0 = Same CLK as Data; 1 = 1 CLK before Data. Resets to 0. Reserved. Write 0. INT active HIGH or active LOW. 0 = LOW; 1 = HIGH. Resets to 1. Enable LQUEUE interrupt. 0 = Disable; 1 = Enable. Resets to 0. Enable AQUEUE interrupt. 0 = Disable; 1 = Enable. Resets to 0. Enable PWEX interrupt. 0 = Disable; 1 = Enable. Resets to 0. Enable SWEX interrupt. 0 = Disable; 1 = Enable. Resets to 0. Enable auto-aging function. 0 = Disable; 1 = Enable. Resets to 0. Enable AQUEUE queue. 0 = Disable; 1 = Enable; Resets to 0. Note that LQUEUE is always enabled. Set port priority. 0 = Sync port; 1 = Processor port. Resets to 0. Reserved. Write 0. Set Sync DOUT port address index first read or last read. 0 = Last, 1 = First. Resets to 0. 1 = Auto age highest-priority; 0 = lowest-priority. Resets to 0. Only if auto-aging is on. Reserved. Write 0. Indicates the Processor port got a match on the last operation. 1 = Match, 0 = No Match. Full flag. Indicates when the device has one or zero free entries left. 1 = Full, 0 = Not Full. CONFIGURATION 0x20 0 R/W 1 R/W 2 R/W 4:3 R/W 5 R/W 6:7 R/W 8 R/W 9 R/W 10 R/W 11 R/W 12 R/W 13 R/W 14 R/W 15 R/W 16 R/W 17 R/W 18 R/W 31:19 R/W MF FF 0x22 0x24 0R 0R Rev. 5 15 MUAA Routing CoProcessor (RCP) Family Instruction Set Descriptions Table 6: Processor Port Registers (continued) Register/Instruction Address Index PROCA[5:0] 0x26 Bit(s) 25:0 R Function Once an operation has been performed on the Processor port the address index is available here. Useful as an index for associated tables in software. SWEX flag PWEX flag LQUEUE flag AQUEUE flag Processor Port Match flag; 1 = Match Full flag; 1 = Full Indicates the LQUEUE has at least one entry. Note this bit is available even if the INT pin is disabled. A read clears the interrupt. Indicates the AQUEUE has at least one entry. Note this bit is available even if the INT pin is disabled. A read clears the interrupt. Indicates a write exception condition has occurred on the processor port. A read clears the interrupt. Indicates a write exception condition has occurred on the syncport. A read clears the interrupt. When auto-aging is enabled the CLK is divided by the value in this register to provide the auto-age interval. Resets to 02FAF080h = 1 second with 50 MHz CLK. This register sets the life of a learned entry in units of the auto-age Interval register. Resets to 012Ch = 300. Number of cascaded devices Read 0 Device ID. 1 = MUAA RCP . Chain size. Multiples of 0.25K Master Device Rev. Slave 1 Rev. Slave 2 Rev. Slave 3 Rev. Read 0 26 R 27 R 28 R 29 R 30 R 31 R LQUEUE Flag AQUEUE Flag PWEX Flag SWEX Flag Auto-Age Interval 0x28 0x2A 0x2C 0x2E 0x30 0R 0R 0R 0R 31:0 R/W Learned Entry Life Info 0x32 0x34 8:0 R/W 1:0 R 2R 31:3 R Size Revision 0x36 0x38 31:0 R 3:0 R 7:4 R 11:8 R 15:12 R 31:16 R 16 Rev. 5 Electrical MUAA Routing CoProcessor (RCP) Family ELECTRICAL Absolute Maximum Ratings Supply Voltage Voltage on All Other Pins Temperature Storage Temperature DC Output Current -0.5 to 4.6 Volts -0.5 to VCC+0.5 Volts (-2.0 Volts for 10 ns, measured at the 50% point) -40°C to 85°C -55°C to 125°C 20 mA (per output, one at a time, one second duration) Stresses exceeding those listed under Absolute Maximum Ratings may induce failure. Exposure to absolute maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied. All voltages referenced to GND. Operating Conditions Symbol VCC VIH Parameter Operating supply voltage Input voltage logic 1 Min. 3.0 2.0 2.4 VIL TA Input voltage logic 0 Ambient operating temperature -0.3 0 Typical 3.3 Max. 3.6 5.5 VDD + 0.3 0.8 70 Units Volts Volts Volts Volts °C Still air All other pins CLK Notes Electrical Characteristics Symbol ICC Parameter Average power supply current Min. Typical 310 1.25 ICC(SB) VOH VOL IIZ IOZ IRP Stand-by power supply current Output voltage logic 1 Output voltage logic 0 Input leakage current Output leakage current Input pull-up resistors MUAA2K MUAA8K -2 -10 25 6.25 2.4 0.4 2 10 2 Max. 400 1.6 7 Units mA A mA Volts Volts µA µA KΩ KΩ IOH = -8.0 mA IOL = 8.0 mA VSS ≤ VIN ≤ VCC VSS ≤ VOUT ≤ VCC /TRST, TMS, TDI Notes MUAA2K MUAA8K Capacitance Symbol CIN Parameter Input capacitance MUAA2K MUAA8K COUT Output capacitance MUAA2K MUAA8K Max. 6 45 7 45 Units pF pF pF pF f = 1 MHz, VOUT = 0V Notes f = 1 MHz, VIN = 0V Rev. 5 17 MUAA Routing CoProcessor (RCP) Family Timing Diagrams TIMING DIAGRAMS t16A t2 t1 t16B t12 t16 t13 t8 t9 CLK /DINE DIN(31:0) OP(3:0) Data Data Data Data load op t3 load t3 op DINREADY t14 /FF t4 /MF t6 t7 t10 t11 t5 read1 t15 t5 readn t15 DOUT(31:0) /DOUTVALID /DOUTE /OE Figure 5: Sync Port Cycle Table 7: Sync Port Cycle - 20 No. t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t16A t16B Name tDVCH tCHDX tCHDRV tCHMV tCHQV tCHQZ tCHQX tQEVCH tCHQEX tGHQZ tGLQX tDEVCH tCHDEX tCHFV tCHQVV tCHCH tCHCL tCLCH 20 8 8 0.5 3 5 3 0.5 3 5 3 10 10 30 12 12 3 Min. 5 3 16 10 15 2.5 0.5 4 7 4 0.5 4 7 4 12 12 4 Max. Min. 7 4 18 12 18 4 - 30 Max. Comment DIN(31:0), OP(3:0) setup to CLK HIGH CLK HIGH to DIN(31:0), OP(3:0) hold CLK HIGH to DINREADY valid CLK HIGH to /MF valid CLK HIGH to DO valid CLK HIGH to DO Hi-Z CLK HIGH to DO active /DOUTE setup to CLK HIGH CLK HIGH to /DOUTE hold /OE to DO Hi-Z /OE to DO active /DINE setup to CLK HIGH CLK HIGH to DINE hold CLK HIGH to /FF valid CLK HIGH to /DOUTVALID CLK period CLK HIGH time CLK LOW time 18 Rev. 5 Timing Diagrams MUAA Routing CoProcessor (RCP) Family t20 t26 t21 t27 t28 t23 t29 t24 /PCS t18 t22 t19 PROCD(31:0) (read) PROCA(5:0) R/W (read) t25 PROCREADY PROCD(31:0) (write) R/W (write) CLK Figure 6: Processor Port Cycle Table 8: Processor Port Cycle - 20 No. t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 Name tSLDQX tSHDQZ tRWVSL tSLRWX tCHDQV tDQVSH tSHDQX tCHPRH tAVSL tSLAX tSLPRH tSHPRL tCHIV 5 3 Nxt16* 4xt16* 10 5 3 10 7 4 Nxt16* 4xt16* 12 3 3 15 8 5 12 Min. t16 8 4 4 18 Max. Min. t16 12 - 30 Max. Comment /PCS LOW to PROCD active /PCS HIGH to PROCD HI-Z R/W setup to /PCS LOW /PCS LOW to R/W hold CLK to PROCD valid (read) PROCD setup to /PCS HIGH (write) /PCS HIGH to PROCD hold (write) CLK HIGH to PROCREADY valid PROCA setup to /PCS LOW /PCS LOW to PROCA hold /PCS LOW to PROCREADY HIGH /PCS HIGH to PROCREADY LOW CLK HIGH to INT valid Notes: * N = 3 for all write operations N = 6 for all register read operations N = 10 for read LQUEUE operations N = 11 for read AQUEUE operations Assumes no Sync port activity to core on previous processor port core operation pending completion. Depending on Sync port activity (auto-age events and processor port priority setting), processor port operations may be extended. Rev. 5 19 MUAA Routing CoProcessor (RCP) Family Notes NOTES 20 Rev. 5 Notes MUAA Routing CoProcessor (RCP) Family NOTES Rev. 5 21 MUAA Routing CoProcessor (RCP) Family Packages PACKAGES 388-Pin PBGA 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M F N P R T U V W Y AA AB AC AD AE AF e Pin # 1 Corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF E1 E 4.00 * 45 o (4x) D1 D A L1 L A1 Seating Plane b 388-Pin PBGA Dimensions Dim. A Min. Nom. Max. 1.17 1.73 O.70 Dim. A1 Dim. b 0.50 Dim. D 34.80 35.00 35.20 30.00 D1 Dim. E 34.80 35.00 35.20 32.00 1.27 31.75 E1 Dim. e Dim. F Dim. L 2.20 2.33 2.46 30° L1 22 Rev. 5 Packages MUAA Routing CoProcessor (RCP) Family 160-Pin PQFP D D1 D2 A A2 A2 E E1 E2 160-Pin PQFP c L e b 160-Pin PQFP Dimensions Dim. A Min. Nom. Max. 4.10 Dim. A1 0.25 Dim. A2 3.20 3.32 3.60 Dim. b 0.22 0.30 0.38 c 0.11 0.15 0.23 31.20 28.00 25.35 31.20 28.00 25.35 0.65 1.60 Dim. D D1 D2 Dim. E E1 E2 Dim. e Dim. L Rev. 5 23 MUAA Routing CoProcessor (RCP) Family Ordering Information ORDERING INFORMATION Part Number MUAA2K80-20QGC MUAA2K80-30QGI MUAA8K80M-20B388C Cycle Time 20 ns 30 ns 20 ns Package 160-Pin PQFP 160-Pin PQFP 388-Pin PBGA Temperature 0–70° C -40–85° C 0–70° C Voltage 3.3 ± 0.3 3.3 ± 0.3 3.3 ± 0.3 MUSIC Semiconductors’ agent or distributor: MUSIC Semiconductors reserves the right to make changes to its products and specifications at any time in order to improve on performance, manufacturability or reliability. Information furnished by MUSIC is believed to be accurate, but no responsibility is assumed by MUSIC Semiconductors for the use of said information, nor for any infringements of patents or of other third-party rights which may result from said use. No license is granted by implication or otherwise under any patent or patent rights of any MUSIC company. © Copyright 2000 and 2002, MUSIC Semiconductors Worldwide Headquarters MUSIC Semiconductors 5850 T.G. Lee Blvd, Suite 345 Orlando, FL 32822 USA Tel: 407 850-1035 Fax: 407 850-1063 North American Sales MUSIC Semiconductors 495 Union Ave. , Suite 1B Middlesex, NJ 08846 USA Tel: 732 469-1886 Fax: 732 469-2397 USA Only: 800 933-1550 Tech Support 888 226-6874 Product Info Asian Headquarters MUSIC Semiconductors 110 Excellence Ave., SEPZ 1 Carmelray Industrial Park Canlubang, Laguna Philippines 4028 Tel: +63 49 549-1480 Fax: +63 49 549-1024 Sales Tel/Fax: +632 723-6215 European Headquarters MUSIC Semiconductors P. O. Box 1 84 6470 ED Eygelshoven The Netherlands Tel: +31 43 455-2675 Fax: +31 43 455-1573 http: //www.musicsemi.com 24 email: info@musicsemi.com Rev. 5