AN32058A-VB

Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A http://www.semicon.panasonic.co.jp/en/ 7 x 7 Dots Matrix LED Driver LSI FEATURES DESCRIPTION  7 x 7 LED Matrix Driver (Total LED that can be driven = 49) AN32058A is 49 Dots Matrix LED Driver. It can drive up to 16 RGB LEDs.  Built-in memory (ROM and RAM)  LDO : 2-ch APPLICATIONS  SPI Interface : 1-ch  Mobile Phone  Driver for RGB color unit : 1-ch  Smart Phone  44 pin Plastic Quad Flat Non-leaded package  PCs (QFN Type)  Game Consoles  Home Appliances etc. TYPICAL APPLICATION Battery VB VLED1 VLED2 R G B LED LDOCNT LEDCTL INT CPU I/F Y0~Y6 7 CE CLK DI DO 7 1.0 F LDO2 LDO1 1.0 F 1.0 F VREFD IREF X0~X6 27 k  RGBGND PGND AGND RSTB Note) The application circuit is an example. The operation of the mass production set is not guaranteed. Sufficient evaluation and verification is required in the design of the mass production set. The Customer is fully responsible for the incorporation of the above illustrated application circuit in the design of the equipment. Page 1 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A CONTENTS  FEATURES ………………………………………………………………………………… 1  DESCRIPTION ……..……………………………………………………………………… 1  APPLICATIONS …………………………………………………………………………… 1  TYPICAL APPLICATION ………………………………………………………………… 1  CONTENTS ………………………………………………………………………………… 2  ABSOLUTE MAXIMUM RATINGS ……………………………………………………… 3  POWER DISSIPATION RATING ………………………………………………………… 3  RECOMMENDED OPERATING CONDITIONS ……………………………………….. 4  ELECTRICAL CHARACTERISTICS .…………………………………………………… 5  PIN CONFIGURATION ……………………………………………………………………13  PIN FUNCTIONS ..………………………………………………………………………… 14  FUNCTIONAL BLOCK DIAGRAM ………………………………………………………16  OPERATION ….…………………………………………………………………………… 17  PACKAGE INFORMATION ……………………………………………………………… 63  IMPORTANT NOTICE .…………………………………………………………………… 64 Page 2 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Note VBMAX 6.0 V *1 VLEDMAX 6.5 V *1 Topr – 30 to + 85 C *2 Tj – 30 to + 125 C *2 Storage temperature Tstg – 55 to + 125 C *2 Input Voltage Range LEDCTL, RSTB, CE, CLK, DI – 0.3 to 3.4 V — LDOCNT – 0.3 to 6.0 V — INT, DO – 0.3 to 3.4 V — R, G, B, LDO1, LDO2, X0, X1, X2, X3, X4, X5, X6, Y0, Y1, Y2, Y3, Y4, Y5, Y6 – 0.3 to 6.5 V — HBM (Human Body Model) 2.0 kV — Supply voltage Operating ambience temperature Operating junction temperature Output Voltage Range ESD Note) This product may sustain permanent damage if subjected to conditions higher than the above stated absolute maximum rating. This rating is the maximum rating and device operating at this range is not guaranteeable as it is higher than our stated recommended operating range. When subjected under the absolute maximum rating for a long time, the reliability of the product may be affected. *1 VBMAX = VB, VLEDMAX = VLED1 = VLED2. The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2 Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25C. POWER DISSIPATION RATING PACKAGE  JA PD (Ta=25 C) PD (Ta=85 C) 44 pin Plastic Quad Flat Non-leaded package (QFN Type) 71.8 C /W 1.392 W 0.557 W Note) For the actual usage, please refer to the PD-Ta characteristics diagram in the package specification, follow the power supply voltage, load and ambient temperature conditions to ensure that there is enough margin and the thermal design does not exceed the allowable value. CAUTION Although this IC has built-in ESD protection circuit, it may still sustain permanent damage if not handled properly. Therefore, proper ESD precautions are recommended to avoid electrostatic damage to the MOS gates Page 3 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A RECOMMENDED OPERATING CONDITIONS Parameter Supply voltage range Input Voltage Range Output Voltage Range Symbol Min. Typ. Max. Unit Note VB 3.1 3.7 4.6 V *1 VLED 3.1 5.0 5.6 V *1 LEDCTL, RSTB, CE, CLK, DI – 0.3 — 3.0 V — LDOCNT – 0.3 — VB + 0.3 V *2 INT, DO – 0.3 — 3.0 V — R, G, B, LDO1, LDO2, X0, X1, X2, X3, X4, X5, X6, Y0, Y1, Y2, Y3, Y4, Y5, Y6 – 0.3 — VLED + 0.3 V *2 Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. Do not apply external currents and voltages to any pin not specifically mentioned. Voltage values, unless otherwise specified, are with respect to GND. GND is voltage for AGND, RGBGND and PGND. VB is voltage for VB. VLED is voltage for VLED1 and VLED2. *2: ( VB + 0.3 ) V must not exceed 6 V. ( VLED + 0.3 ) V must not exceed 6.5 V. Page 4 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A ELECTRICAL CHARACTERISTICS VB = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C  2 C unless otherwise specified. Parameter Symbol Condition Min Limits Typ Max Unit Note Current consumption Current consumption (1) ICC1 At OFF mode LDOCNT = Low — 0 1 A — Current consumption (2) ICC2 At Standby mode LDOCNT = Low LDO2 is active. — 8 12 A — Current consumption (3) ICC3 LDOCNT = High LDO1 and LDO2 are active. — 18 24 A — VREF IVREF = 0 A 1.21 1.24 1.27 V — VIREF IIREF = 0 A 0.44 0.54 0.64 V — VL1 ILDO1 = – 30 mA 1.79 1.85 1.91 V — IPT1 LDOCNT = High REG18 = High VLDO1 = 0 V, IPT1 = ILDO1 50 100 200 mA — PSL11 VB = 3.6 V + 0.2 V[p-p] f = 1 kHz ILDO1 = – 15 mA PSL11 = 20log (acVLDO1 / 0.2) — – 45 – 40 dB — PSL12 VB = 3.6 V + 0.2 V[p-p] f = 10 kHz ILDO1 = – 15 mA PSL12 = 20log (acVLDO1 / 0.2) — – 35 – 25 dB — Reference voltage Output voltage Reference current Output voltage Voltage regulator (LDO1) Output voltage Short circuit protection current Ripple rejection (1) Ripple rejection (2) Page 5 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A ELECTRICAL CHARACTERISTICS (continued) VB = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C  2 C unless otherwise specified. Parameter Symbol Condition Min Limits Typ Max Unit Note Voltage regulator (LDO2) Output voltage Short circuit protection current Ripple rejection (1) Ripple rejection (2) VL2 ILDO2 = – 30 mA 2.76 2.85 2.94 V — IPT2 LDOCNT = High VLDO2 = 0V IPT2 = ILDO2 50 100 300 mA — PSL21 VB = 3.6 V + 0.2 V[p-p] f = 1 kHz ILDO2 = – 15 mA PSL21 = 20log (acVLDO2 / 0.2) — – 35 – 30 dB — PSL22 VB = 3.6 V + 0.2 V[p-p] f = 10 kHz ILDO2 = – 15 mA PSL22 = 20log (acVLDO2 / 0.2) — – 25 – 15 dB — 0.96 1.20 1.44 MHz — — 2 4.8  — Oscillator Oscillation frequency FDC — SCAN Switch Resistance at the Switch ON RSCAN IY0, Y1, Y2, Y3, Y4, Y5, Y6 = 5 mA RSCAN = VY0, Y1, Y2, Y3, Y4, Y5, Y6 / 5 mA Page 6 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A ELECTRICAL CHARACTERISTICS (continued) VB = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C  2 C unless otherwise specified. Parameter Symbol Condition Limits Unit Note Min Typ Max 0.950 1.033 1.116 mA *1 Current generator (For 7  7 dots matrix LED) Output current (1) IMX1 At 1mA setup VX0, X1, X2, X3, X4, X5, X6 = 1 V IMX1 = IX0, X1, X2, X3, X4, X5, X6 Output current (2) IMX2 At 2 mA setup VX0, X1, X2, X3, X4, X5, X6 = 1 V IMX2 = IX0, X1, X2, X3, X4, X5, X6 1.907 2.073 2.239 mA *1 IMX4 At 4 mA setup VX0, X1, X2, X3, X4, X5, X6 = 1 V IMX4 = IX0, X1, X2, X3, X4, X5, X6 3.824 4.157 4.490 mA *1 Output current (4) IMX8 At 8 mA setup VX0, X1, X2, X3, X4, X5, X6 = 1 V IMX8 = IX0, X1, X2, X3, X4, X5, X6 7.660 8.326 8.992 mA *1 Output current (5) IMX15 At 15 mA setup VX0, X1, X2, X3, X4, X5, X6 = 1 V IMX15 = IX0, X1, X2, X3, X4, X5, X6 14.408 15.661 16.914 mA *1 Output current (3) Leakage Current when matrix LED turns off Current OFF setup IMXOFF VX0, X1, X2, X3, X4, X5, X6 = 4.75 V IMXOFF = IX0, X1, X2, X3, X4, X5, X6 The error between channels IMXCH The average value of all channels, and the current error of each channel — — 1 A — –5 — 5 % — *1 : Values when recommended parts (ERJ2RHD273X) are used for IREF terminal. The other current settings are combination of above items. Page 7 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A ELECTRICAL CHARACTERISTICS (continued) VB = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C  2 C unless otherwise specified. Parameter Symbol Condition Limits Min Typ Max Unit Note Current generator (For RGB color unit) Output current (1) IRGB1 At 1mA setup VR, G, B = 1 V 0.949 1.031 1.113 mA *1 Output current (2) IRGB2 At 2 mA setup VR, G, B = 1 V 1.892 2.056 2.220 mA *1 Output current (3) IRGB4 At 4 mA setup VR, G, B = 1 V 3.764 4.091 4.418 mA *1 Output current (4) IRGB8 At 8 mA setup VR, G, B = 1 V 7.510 8.163 8.816 mA *1 — — 1 A — –5 — 5 % — Leakage Current when RGB turn off Current OFF setup IRGBOFF VR, G, B = 4.75 V IRGBOFF = IR, G, B The error between channels IRGBCH The average value of all channels, and the current error of each channel *1 : Values when recommended parts (ERJ2RHD273X) are used for IREF terminal. The other current settings are combination of above items. Page 8 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A ELECTRICAL CHARACTERISTICS (continued) VB = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C  2 C unless otherwise specified. Parameter Symbol Condition Limits Min Typ Max Unit Note SPI I/F，LEDCTL，RSTB Input voltage range of Highlevel VIH High-level recognition voltage LDO1  0.8 — LDO2 + 0.3 V — Input voltage range of Lowlevel VIL Low-level recognition voltage – 0.3 — 0.4 V — Input current of High-level IIH VLEDCTL, RSTB, CE, CLK, DI = 1.85 V IIH = ILEDCTL, RSTB, CE, CLK, DI — 0 1 A — Input current of Low-level IIL VLEDCTL, RSTB, CSB, CLK, DI = 0 V IIL = ILEDCTL, RSTB, CE, CLK, DI — 0 1 A — INT Output voltage of High-level (1) VOH1 IINT = – 2 mA VDDSEL = LDO2 LDO2  0.8 — — V — Output voltage of Low-level (1) VOL1 IINT = 2 mA VDDSEL = LDO2 (IINT = 0.5 mA ) — — LDO2 0.2 (0.15) V — Output voltage of High-level (2) VOH2 IINT = – 2 mA VDDSEL = LDO1 LDO1  0.8 — — V — VOL2 IINT = 2 mA VDDSEL = LDO1 (IINT = 0.5 mA ) — LDO1 0.3 (0.15) V — Output voltage of Low-level (2) — Page 9 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A ELECTRICAL CHARACTERISTICS (continued) VB = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C  2 C unless otherwise specified. Parameter Symbol Condition Input voltage range of High-level VIH Input voltage range of Low-level Limits Unit Note Min Typ Max High-level recognition voltage VB  0.7 — VB + 0.3 V — VIL Low-level recognition voltage – 0.3 — 0.4 V — Input current of High-level IIH VLDOCNT = 3.6 V IIH = ILDOCNT — 0 1 A — Input current of Low-level IIL VLDOCNT = 0 V IIL = ILDOCNT — 0 1 A — Output voltage of High-level VOH IDO = – 2 mA LDO1  0.8 — — V — Output voltage of Low-level VOL IDO = 2 mA — — LDO1  0.2 V — LDOCNT DO Page 10 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A ELECTRICAL CHARACTERISTICS (continued) VB = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C  2 C unless otherwise specified. Parameter Symbol Limits Condition Min Typ Max Unit Note Voltage regulator (LDO1) Output capacitor 1 F, Output capacitor’s ESR less than 0.1  Rise time Tsu1 Time until output voltage reaches to 0 V to 90% — 0.25 — ms *2 *3 Fall time Tsd1 Time until output voltage reaches to 10% — 5 — ms *2 *3 — 15 — mA *3 Maximum load current — IOMAX1 Load transient response (1) Vtr11 ILDO1 = – 50 A  – 15 mA (1 s) — 70 — mV *3 Load transient response (2) Vtr12 ILDO1 = – 15 mA  – 50 A (1 s) — 70 — mV *3 Voltage regulator (LDO2) Output capacitor 1 F, Output capacitor’s ESR less than 0.1  Rise time Tsu2 Time until output voltage reaches to 0 V to 90% — 0.25 — ms *2 *3 Fall time Tsd2 Time until output voltage reaches to 10% — 5 — ms *2 *3 — 15 — mA *3 Maximum load current IOMAX2 — Load transient response (1) Vtr21 ILDO2 = – 50 A  – 15 mA (1 s) — 70 — mV *3 Load transient response (2) Vtr22 ILDO2 = – 15 mA  – 50 A (1 s) — 70 — mV *3 Tdet Temperature which LDO1, LDO2, Constant current circuit, Matrix SW and RGB turns off. — 160 — C *3 *4 Returning temperature — 110 — C *3 *5 TSD (Thermal shutdown circuit) Detection temperature Return temperature Note) Tsd11 *2 : Rise time and Fall time are defined as below. Actual evaluation result of rise time : LDO1 : 290 to 400 s, LDO2 : 220 to 310 s Actual evaluation result of fall time : LDO1 : 6.2 to 8.5 ms, LDO2 : 5.8 to 7.9 ms *3 : Typical Design Value *4 : LDO1, LDO2, Constant current circuit, and Matrix SW and RGB are turned off when TSD is High. When TSD is High, the register is set as 14hD1 = 1. However, data can be read only when the register is read immediately after INT occurs since internal regulator is turned off. *5 : Only LDO1 and LDO2 return after ON state of TSD. A logic part will be in Reset state. LDOCNT Serial LDO1 90% Tsu1 LDO2 10% Tsd1 90% Tsu2 10% Tsd2 Page 11 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A ELECTRICAL CHARACTERISTICS (continued) VB = 3.6 V, VLED1 = VLED2 = 4.9 V Note) Ta = 25 C  2 C unless otherwise specified. Parameter Symbol Limits Condition Min Typ Max Unit Note Microcomputer interface characteristic (Vdd = 1.85 V  3 %) Write access Timing CLK cycle time tscyc1 — — 125 — ns *3 CLK cycle time High period twhc1 — — 60 — ns *3 CLK cycle time Low period twlc1 — — 60 — ns *3 Serial-data setup time tss1 — — 62 — ns *3 Serial-data hold time tsh1 — — 62 — ns *3 Transceiver interval tcsw1 — — 62 — ns *3 Chip enable setup time tcss1 — — 5 — ns *3 Chip enable hold time tcgh1 — — 5 — ns *3 Microcomputer interface characteristic (Vdd = 1.85 V  3 %) Read access Timing CLK cycle time tscyc1 — — 125 — ns *3 CLK cycle time High period twhc1 — — 60 — ns *3 CLK cycle time Low period twlc1 — — 60 — ns *3 Serial-data setup time tss1 — — 62 — ns *3 Serial-data hold time tsh1 — — 62 — ns *3 Transceiver interval tcsw1 — — 62 — ns *3 Chip enable setup time tcss1 — — 5 — ns *3 Chip enable hold time tcgh1 — — 5 — ns *3 tdodly1 Only read mode — 25 — ns *3 DC delay time Note) *3 : Typical Design Value Timing chart tcgh1 CE tscyc1 tcss1 twhc1 twlc1 tcsw1 CLK DI tss1 tsh1 DO tdodly1 Page 12 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A PIN CONFIGURATION 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 N.C. LEDCTL Y0 Y1 VLED1 Y2 Y3 Y4 Y5 VLED2 N.C. N.C. VB LDO1 RSTB IREF LDOCNT VREFD AGND Y6 N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 R RGBGND G B DO DI CLK CE INT LDO2 N.C. 33 32 31 30 29 28 27 26 25 24 23 N.C. N.C. X6 X5 X4 PGND X3 X2 X1 X0 N.C. Top View Page 13 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A PIN FUNCTIONS Pin No. Pin name Type Description 1 10 11 12 22 23 32 33 44 N.C. — 2 VB 3 LDO1 Output LDO1 ( 1.85 V ) output terminal. 4 RSTB Input Reset input terminal ("L" active ) 5 IREF Output 6 LDOCNT Input 7 VREFD Output BGR circuit output terminal. 8 AGND Ground The GND terminal for Analog circuitry. 9 Y6 Output The output terminal of matrix switching control. It connects with the G Column of matrix LED. 13 18 VLED2 VLED1 Power supply 14 Y5 Output The output terminal of matrix switching control. It connects with the F Column of matrix LED. 15 Y4 Output The output terminal of matrix switching control. It connects with the E Column of matrix LED. 16 Y3 Output The output terminal of matrix switching control. It connects with the D Column of matrix LED. 17 Y2 Output The output terminal of matrix switching control. It connects with the C Column of matrix LED. 19 Y1 Output The output terminal of matrix switching control. It connects with the B Column of matrix LED. 20 Y0 Output The output terminal of matrix switching control. It connects with the A Column of matrix LED. 21 LEDCTL Input No Connection Power supply The power supply's connect terminal for BGR circuit and LDO circuit. The resistance connect terminal for constant current value setup. ON/OFF control terminal of LDO1 and LDO2. The power supply's connect terminal for matrix LED. Connect with the output of battery or step-up DC/DC converter LED's lighting ON/OFF control terminal. ( It is based on register 0Ah.) Page 14 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A PIN FUNCTIONS (continued) Pin No. Pin name Type Description 24 X0 Output Constant current circuit. The output terminal of PWM control. It connects with the 1st Row of matrix LED. 25 X1 Output Constant current circuit. The output terminal of PWM control. It connects with the 2nd Row of matrix LED. 26 X2 Output Constant current circuit. The output terminal of PWM control. It connects with the 3rd Row of matrix LED. 27 X3 Output Constant current circuit. The output terminal of PWM control. It connects with the 4th Row of matrix LED. 28 PGND Ground The GND terminal for matrix LED 29 X4 Output Constant current circuit. The output terminal of PWM control. It connects with the 5th Row of matrix LED. 30 X5 Output Constant current circuit. The output terminal of PWM control. It connects with the 6th Row of matrix LED. 31 X6 Output Constant current circuit. The output terminal of PWM control. It connects with the 7th Row of matrix LED. 34 R Output LED contact terminal. 35 RGBGND Ground The GND terminal for RGB terminal. 36 G Output LED contact terminal. 37 B Output LED contact terminal. 38 DO Output Data output terminal for SPI interface. 39 DI Input Data input terminal for SPI interface. 40 CLK Input Clock input terminal for SPI interface. 41 CE Input Chip-enable terminal for SPI1 interface. ("H" active ) 42 INT Output Interrupt output terminal. 43 LDO2 Output LDO2 ( 2.85 V ) output terminal. Page 15 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A 23 N.C. 24 XO 25 X1 26 X2 27 X3 28 PGND 29 X4 30 X5 31 X6 32 N.C. 33 N.C. FUNCTIONAL BLOCK DIAGRAM Constant current control (7-ch) 22 N.C. R 34 RGBGND 35 G 36 20 Y0 19 Y1 B 37 Fixed pattern ROM Register DO 38 DI 39 Level shift CLK 40 21 LEDCTL PWM control (7-ch) RGB Color Unit control SPI 18 VLED1 Pattern register RAM SCAN switch (7-ch) Command decoding 17 Y2 16 Y3 15 Y4 CE 41 14 Y5 Level shift ON/OFF STANDBY ON/OFF N.C. 44 12 N.C. BGR TSD 1 2 3 4 5 6 7 8 9 10 11 VB LDO1 RSTB IREF LDOCNT VREFD AGND Y6 N.C. N.C. IREF N.C. LDO1 1.85 V/30 mA 13 VLED2 ON/OFF HTSD ON/OFF 1 LDO2 43 LDO2 2.85 V/30 mA INT 42 Notes: This block diagram is for explaining functions. Part of the block diagram may be omitted, or it may be simplified. Page 16 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A OPERATION 1. Explanation in each mode (Power supply starting sequence) Mode LDOCNT REG18 REG28 OFF Low 0 0 "L" → "H" 0/1 0/1 "H" 0/1 0/1 OFF → Normal mode Normal mode → OFF 0 0 0 1 "H" → "L" Normal mode → Standby mode Note • It is necessary to make it LDOCNT = High for the return from OFF-mode. • The signal from serial interface is not received in LDOCNT = Low and the state of REG28 = Low or REG18 = Low. • It shifts to standby mode with LDOCNT = Low and REG28 = High. • The signal from serial interface is not received at Standby-mode. (Power supply for Logic is LDO1 and LDO2.) Therefore, standby release by the signal from serial interface cannot be performed. • In Standby-mode, if LDOCNT is switched to High from Low, it will return to the normal mode. • It cannot shift to OFF-mode from Standby-mode. Once returning to the normal mode, please shift to OFF-mode. • Regardless of the value of REG18, LDO1 turns on at LDOCNT = High. • Regardless of the value of REG28, LDO2 turns on at LDOCNT = High. • Serial interface signal is not received at RSTB = Low • 5 ms after being set to LDOCNT = High, the receptionist of serial interface signal is attained. • RSTB terminal prohibits the input signal of those other than a rectangle wave. • All register setting become default setting if RSTB = Low • (The default setting of REG18 and REG28 are [1] • If RSTB = Low before LDOCNT = Low, LDO1 and LDO2 can’t turn off. ) • All register setting become default setting when LDO2 turn off. • The setting order to change off mode is as following. • REG18, 28 = [0] → LDOCNT = "L" → RSTB = "L" Page 17 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A OPERATION (continued) 1. Explanation in each mode (Power supply starting sequence) (continued) • Shift to the Normal mode from OFF-mode LDOCNT REG18 [Address : 02h] REG28 [Address : 02h] LDO1 LDO2 RSTB Over 3 ms Over 5 ms A register input is possible. • Shift to the Normal mode from Standby mode LDOCNT REG18 [Address : 02h] REG28 [Address : 02h] LDO1 LDO2 Low power mode RSTB* over 3 ms Over 5 ms A register input is possible. * It is a waveform in the case of applying reset to register setup at Standby mode. * Maintain the state of RSTB = High to hold the register setup. Page 18 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A OPERATION (continued) 1. Explanation in each mode (Power supply starting sequence) (continued) • Shift to the OFF-mode from Normal mode Over 1 ms LDOCNT REG18 [Address : 02h] REG28 [Address : 02h] Set REG18 and REG28 to Low before LDOCNT. LDO1 LDO2 RSTB Over 3ms A register input is possible. • Shift to the Standby mode from Normal mode Over 1 ms LDOCNT REG18 [Address : 02h] Set REG18 to Low before LDOCNT. REG28 [Address : 02h] LDO1 LDO2 Low power mode RSTB A register input is possible. Page 19 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A OPERATION (continued) 1. Explanation in each mode (Power supply starting sequence) (continued) • Shift to the OFF-mode from Normal mode VBAT LDOCNT MODE "L" "L" OFF "L" "H" Prohibition "H" "L" OFF "H" "H" ON Note) "L" in column of VBAT and LDOCNT means 0 V, "H" means 3.1 to 4.6 V ( operating supply voltage range ). • Logic pin condition The following setting is common for OFF, Standby and Normal mode. The pin setting when RSTB = Low, under Normal mode is as follows. Pin name Pin state Logic* INT Output "L" CE Input "L" CLK Input "L" DI Input "L" DO Output "L" LEDCTL Input "L" LDOCNT Input Depends on each mode Note)*: Logic state for pins indicated as “Output” under Pin state shows the output level. Logic state for pins indicated as “Input” under Pin state shows the input level to be set to the pins. Page 20 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A OPERATION (continued) 2. Explanation of operation • Matrix part operation waveform • The following waveform is an internal signal. In following Yx = Xx = Low, the waveform of actual Yx terminal is set to Hi-Z. • It is controlled by internal 1.2 MHz clock in default condition. • Y side switches from Y0 to Y6 in that order. The turning on term of each pin is constant 945clock (787.5 s) and each turning on term includes 8clock (6.67 s) interval. • "*" mark shows the turning on term and D3, D6 is the turning off term in the following figure. • 77 matrix display is controlled by X0 to X6 with Yx switching timing. 945clk (787.5 s) 8clk (6.67 s) Y0 Y1 Y2 Y3 Y4 Y5 Y6 X0 to X6 * * D0 * * D1 D2 D3 * * D4 D5 D6 D0 PWM Minimum width 63clk (52.5 s) 6671clk (About 180.83 Hz) Page 21 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A OPERATION (continued) 3. Block configuration • RESET part block configuration VB VBATT VREFD ON/OFF BGR TSD HTSD 1 F LDOCNT LDO2 LDO2 2.85 V 1 F LDO1 LDO1 1.85 V ON/OFF STANDBY ON/OFF ON/OFF 1 F LDO1 LDO2 CE CLK DI LEVEL SHIFT LDO2 VB Register REG18 DO RST REG28 LEVEL SHIFT LDO1 LDO2 RSTB LEVEL SHIFT LDO2 All the logic portions to which the power supply is not connected are connected to VB as power supplies. Page 22 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A OPERATION (continued) 3. Block configuration (continued) • Explanation of matrix LED part, matrix LED’s number • • • • LED matrix driver circuit can display character and pattern by controlling the 77 matrix LED individually. In this specification, LED’s number controlled by each terminal can be matched off against the following figure. It is controlled by internal 1.2 MHz clock in default condition. In the scroll mode, LED matrix can move the display of character from right to left as the following arrangement. The connected terminal name X0 1 X1 2 X2 3 X3 4 X4 5 X5 6 X6 7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 A B C D E F G LED’s number LED‘s number Page 23 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A OPERATION (continued) 3. Block configuration (continued) • Equivalent circuit of matrix LED driver X0 terminal case LDO2 VLED VB 20 A 1.24 V BGR Ibl1 245 k 187 k IREF X0 V(IREF) = 0.54 V R(IREF) = 27 k Control Logic DAC Q1 Q2 Panasonic ERJ2RHD273X • The reference current for constant current driver is calculated by the following formula. V(IREF) / R(IREF) = 0.54 V / 27 k = 20 A • The LED driver current can be set from 0 mA to 30 mA by register setting via serial interface. • The constant current value can be changed by the external resistor value of IREF terminal, but the accuracy in case of that setting is not guaranteed. • ERJ2RHD273X is recommended for the external resistor of IREF terminal to keep the constant current accuracy. Page 24 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A OPERATION (continued) 4. Register and Address • Register Map Sub address R/W Data name 01h W 02h W Data D7 D6 D5 D4 D3 D2 D1 D0 POWERCNT — — — — — OSCEN — — LDOCNT — — — — — — REG18 REG28 — DISMTX DISRGB — 03h For test 04h For test 05h For test 06h For test 07h For test 08h For test 09h For test 0Ah W LEDCTL LEDACT — — — 10h For test 11h For test 12h For test 13h For test 14h R IOFACTOR FACGD1 — — — 15h For test 16h For test 17h For test 18h For test 19h For test 1Ah W/R VDDSEL INTVSEL — — — RAM ACT — FRMINT CPUWRER — — TSD — Page 25 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A OPERATION (continued) 4. Register and Address (continued) • Register Map (continued) DATA Sub Address R/W Data Name 20h R/W MTXON 21h R/W MTXDATA 22h R/W FFROM 23h R/W ROMSEL 24h R/W RAMCOPY 25h R/W SETFROM SETFROM[7:0] 26h R/W SETTO SETTO[7:0] 27h R/W REPON       28h R/W SETTIME       29h R/W RAMRST       RAM1 RAM2 2Ah R/W SCROLL        SCLON    RGBON  RAMNUM D7 D6 D5 D4 D3 D2 D1 D0        MTXON MTXDATA[7:0]      ROM77[1:0] SELROM[7:0]    2Bh    SELRAM COPYSTART  REPON SETTIME[1:0] For test 2Ch R/W RGBON   2Dh R/W RGBDATA     RGBDATA[5:0] 2Eh 30h  For test R/W RAMNUM     6Bh For test 6Dh For test 6Fh For test 70h For test 71h For test 72h For test 73h For test 74h For test 75h For test 76h For test 77h For test   * Access the address from 6Bh to 77h is prohibited. Page 26 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A OPERATION (continued) 4. Register and Address (continued) RAM address map DATA Sub Address Data Name 31h A1 BLA1[3:0] FRA1[1:0] DLA1[1:0] 32h A2 BLA2[3:0] FRA2[1:0] DLA2[1:0] 33h A3 BLA3[3:0] FRA3[1:0] DLA3[1:0] 34h A4 BLA4[3:0] FRA4[1:0] DLA4[1:0] 35h A5 BLA5[3:0] FRA5[1:0] DLA5[1:0] 36h A6 BLA6[3:0] FRA6[1:0] DLA6[1:0] 37h A7 BLA7[3:0] FRA7[1:0] DLA7[1:0] 38h B1 BLB1[3:0] FRB1[1:0] DLB1[1:0] 39h B2 BLB2[3:0] FRB2[1:0] DLB2[1:0] 3Ah B3 BLB3[3:0] FRB3[1:0] DLB3[1:0] 3Bh B4 BLB4[3:0] FRB4[1:0] DLB4[1:0] 3Ch B5 BLB5[3:0] FRB5[1:0] DLB5[1:0] 3Dh B6 BLB6[3:0] FRB6[1:0] DLB6[1:0] 3Eh B7 BLB7[3:0] FRB7[1:0] DLB7[1:0] 3Fh C1 BLC1[3:0] FRC1[1:0] DLC1[1:0] 40h C2 BLC2[3:0] FRC2[1:0] DLC2[1:0] 41h C3 BLC3[3:0] FRC3[1:0] DLC3[1:0] 42h C4 BLC4[3:0] FRC4[1:0] DLC4[1:0] 43h C5 BLC5[3:0] FRC5[1:0] DLC5[1:0] 44h C6 BLC6[3:0] FRC6[1:0] DLC6[1:0] 45h C7 BLC7[3:0] FRC7[1:0] DLC7[1:0] 46h D1 BLD1[3:0] FRD1[1:0] DLD1[1:0] 47h D2 BLD2[3:0] FRD2[1:0] DLD2[1:0] 48h D3 BLD3[3:0] FRD3[1:0] DLD3[1:0] 49h D4 BLD4[3:0] FRD4[1:0] DLD4[1:0] 4Ah D5 BLD5[3:0] FRD5[1:0] DLD5[1:0] 4Bh D6 BLD6[3:0] FRD6[1:0] DLD6[1:0] 4Ch D7 BLD7[3:0] FRD7[1:0] DLD7[1:0] D7 D6 D5 D4 D3 D2 D1 D0 Page 27 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A OPERATION (continued) 4. Register and Address (continued) RAM address map (continued) DATA Sub Address Data Name 4Dh E1 BLE1[3:0] FRE1[1:0] DLE1[1:0] 4Eh E2 BLE2[3:0] FRE2[1:0] DLE2[1:0] 4Fh E3 BLE3[3:0] FRE3[1:0] DLE3[1:0] 50h E4 BLE4[3:0] FRE4[1:0] DLE4[1:0] 51h E5 BLE5[3:0] FRE5[1:0] DLE5[1:0] 52h E6 BLE6[3:0] FRE6[1:0] DLE6[1:0] 53h E7 BLE7[3:0] FRE7[1:0] DLE7[1:0] 54h F1 BLF1[3:0] FRF1[1:0] DLF1[1:0] 55h F2 BLF2[3:0] FRF2[1:0] DLF2[1:0] 56h F3 BLF3[3:0] FRF3[1:0] DLF3[1:0] 57h F4 BLF4[3:0] FRF4[1:0] DLF4[1:0] 58h F5 BLF5[3:0] FRF5[1:0] DLF5[1:0] 59h F6 BLF6[3:0] FRF6[1:0] DLF6[1:0] 5Ah F7 BLF7[3:0] FRF7[1:0] DLF7[1:0] 5Bh G1 BLG1[3:0] FRG1[1:0] DLG1[1:0] 5Ch G2 BLG2[3:0] FRG2[1:0] DLG2[1:0] 5Dh G3 BLG3[3:0] FRG3[1:0] DLG3[1:0] 5Eh G4 BLG4[3:0] FRG4[1:0] DLG4[1:0] 5Fh G5 BLG5[3:0] FRG5[1:0] DLG5[1:0] 60h G6 BLG6[3:0] FRG6[1:0] DLG6[1:0] 61h G7 BLG7[3:0] FRG7[1:0] DLG7[1:0] 62h LEDR BLLEDR[3:0] FRLEDR[1:0] DLLEDR[1:0] 63h LEDG BLLEDG[3:0] FRLEDG[1:0] DLLEDG[1:0] 64h LEDB BLLEDB[3:0] FRLEDB[1:0] DLLEDB[1:0] D7 D6 D5 D4 D3 D2 D1 D0 Page 28 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A OPERATION (continued) 4. Register and Address (continued) • ROM Address Map [00000000] - [10010101] : ROM(Only luminosity) 7  7 Pattern No.0 (default) to Pattern No.149 Pattern No. Contents of the pattern Display Pattern No. Contents of the pattern Display 0 All putting out lights Nothing 31 Alphabetic character U 1 Number 0 32 Alphabetic character V 2 Number 1 33 Alphabetic character W 3 Number 2 34 Alphabetic character X 4 Number 3 35 Alphabetic character Y 5 Number 4 36 Alphabetic character Z 6 Number 5 37 Alphabetic character a 7 Number 6 38 Alphabetic character b 8 Number 7 39 Alphabetic character c 9 Number 8 40 Alphabetic character d 10 Number 9 41 Alphabetic character e 11 Alphabetic character A 42 Alphabetic character f 12 Alphabetic character B 43 Alphabetic character g 13 Alphabetic character C 44 Alphabetic character h 14 Alphabetic character D 45 Alphabetic character i 15 Alphabetic character E 46 Alphabetic character j 16 Alphabetic character F 47 Alphabetic character k 17 Alphabetic character G 48 Alphabetic character l 18 Alphabetic character H 49 Alphabetic character m 19 Alphabetic character I 50 Alphabetic character n 20 Alphabetic character J 51 Alphabetic character o 21 Alphabetic character K 52 Alphabetic character p 22 Alphabetic character L 53 Alphabetic character q 23 Alphabetic character M 54 Alphabetic character r 24 Alphabetic character N 55 Alphabetic character s 25 Alphabetic character O 56 Alphabetic character t 26 Alphabetic character P 57 Alphabetic character u 27 Alphabetic character Q 58 Alphabetic character v 28 Alphabetic character R 59 Alphabetic character w 29 Alphabetic character S 60 Alphabetic character x 30 Alphabetic character T 61 Alphabetic character y Page 29 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A OPERATION (continued) 4. Register and Address (continued) • ROM Address Map (continued) [00000000] - [10010101] : ROM(Only luminosity) 77 Pattern No.0 (default) to Pattern No.149 Pattern No. Contents of the pattern Display Pattern No. Contents of the pattern Display 62 Alphabetic character z 93 Number 30 63 Number 00 94 Number 31 64 Number 01 95 Number 32 65 Number 02 96 Number 33 66 Number 03 97 Number 34 67 Number 04 98 Number 35 68 Number 05 99 Number 36 69 Number 06 100 Number 37 70 Number 07 101 Number 38 71 Number 08 102 Number 39 72 Number 09 103 Number 40 73 Number 10 104 Number 41 74 Number 11 105 Number 42 75 Number 12 106 Number 43 76 Number 13 107 Number 44 77 Number 14 108 Number 45 78 Number 15 109 Number 46 79 Number 16 110 Number 47 80 Number 17 111 Number 48 81 Number 18 112 Number 49 82 Number 19 113 Number 50 83 Number 20 114 Number 51 84 Number 21 115 Number 52 85 Number 22 116 Number 53 86 Number 23 117 Number 54 87 Number 24 118 Number 55 88 Number 25 119 Number 56 89 Number 26 120 Number 57 90 Number 27 121 Number 58 91 Number 28 122 Number 59 92 Number 29 123 Number 60 Page 30 of 64 Established : 2007-05-24 Revised : 2013-04-15 Doc No. TA4-EA-04725 Revision. 3 Product Standards AN32058A OPERATION (continued) 4. Register and Address (continued) • ROM Address Map (continued) [00000000] - [10010101] : ROM(Only luminosity) 77 Pattern No.0 (default) to Pattern No.149 Pattern No. Contents of the pattern Display Pattern No. Contents of the pattern 124 Symbol Zero antenna 144 Symbol 125 Symbol One antenna 126 Symbol Two antenna 145 Symbol 127 Symbol Three antenna 128 Symbol 146 Symbol 129 Symbol  130 Symbol || 147 Symbol 131 Symbol >> 132 Symbol