CLASSIFICATION
SUBJECT
No.
151S-ECJ-KBS39E
PAGE
1 of 1
DATE Aug 28, 2008
SPECIFACATION
Multilayer Ceramic Chip Capacitors (EIA 0805)
High Capacitance (P/N:ECJ2F60J226M) Individual Specification
1. Scope
This specification applies to High Capacitance Multilayer Ceramic Chip Capacitors (EIA 0805), Temp. Char:X6S, Rated
voltage DC6.3 V , Nominal Capacitance 22 µF.
2. Style and Dimensions
W
Table 1
T
Symbol
Dimensions(mm)
L
2.0 +/- 0.2
W
1.25 +/- 0.20
T
1.25 +/- 0.20
L1,L2
0.50 +/- 0.25
L1
L
L2
3. Operating Temperature Range / Storage Temperature Range
Table 2
Temperature Characteristics
X6S
Class2
Operating Temp. Range.
-55 to 105 °C
Storage Temperature Range
-55 to 105 °C
4. Individual Specification
Table 3
Part Number
Rated
Voltage
Temp. Char.
Nominal
Capacitance
Cap. Tolerance
ECJ2F60J226M
DC 6.3 V
X6S
22 µF
+/-20 %
5. Explanation of Part Numbers
ECJ
2
Common Code
Size Code
Code
Size
2
EIA 0805
F
6
Temp. Char.
Code
Show in
Table 4
0
J
2
2
6
Nominal Cap.
Rated Voltage
Code
Voltage
0J
DC 6.3 V
Packaging Style
Code
Packaging Style
F φ180Reel Embossed Taping 3,000 pcs./reel
M
Cap.
Tolerance
Code
Show in
Table 3
6. Temperature Characteristics
Table 4
Temp. Char.
Code
6
Capacitance Change rate from Temperature
Temp. Char.
Without voltage application
X6S
+/-22 %
Measurement
Temperature Range
Reference
Temperature
-55 to 105 °C
25 °C
7. Soldering method
Flow soldering shall not be applied.
Note ;
APPROVAL
Panasonic Electronic Devices Co., Ltd.
T.Kawamura
CHECK
T.Shinriki
DESIGN
A.Konishi
CLASSIFICATION
SPECIFICATION
SUBJECT
Multilayer Ceramic Chip Capacitors (EIA 0805)
High Capacitance (P/N : ECJ2F60J226M) Common Specification
No.
151S-ECJ-KGS39E
PAGE
1 of 7
DATE
Aug 28, 2008
1. Information
1- 1.Applicable laws and regulations
(1) Any ozone-depleting substances listed in the Montreal Protocol are not used in the manufacturing processes for
parts and materials used in this product.
(2) PBB and PBDE are intentionally excluded from materials used in this product.
(3) All the materials used in this product are registered materials under the Law Concerning Examination and
Regulation of Manufacture and Handling of Chemical Substances.
(4) This product complies with the RoHS, DIRECTIVE 2002/95/EC on the Restriction of the use of certain Hazardous Substances in electrical and electronic equipment.
(5) This product is exported with export procedures under export related laws and regulations such as the Foreign
Exchange and Foreign Trade Law.
1- 2.Limitation in Applications
This product was designed and manufactured for general-purpose electronic equipment such as household, office,
information & communication equipment. When the following applications, which are required higher reliability and
safety because the trouble or malfunction of this product may threaten the lives and/or properties, are examined,
separate specifications suitable for the application should be exchanged.
・Aerospace / Aircraft equipment, Warning / Antitheft equipment, Medical equipment, Transport equipment (Motor
vehicles, Trains, Ship and Vessel ), Highly public information processing equipment, Others equivalent to the
above.
1- 3.Production factory
(1) Panasonic Electronic Devices Japan Co., Ltd.
(2) Panasonic Electronic Devices (Tianjin) Co., Ltd. (PEDTJ)
2. Scope
2- 1.This specification applies to High Capacitance Multilayer Ceramic Chip Capacitors (P/N : ECJ2F60J226M).
If there is a difference between this common specification and any individual specifications, priority shall be given to
the individual specifications.
2- 2.This product shall be used for general-purpose electronic equipment such as audiovisual, household, office, information & communication equipment.
Unreasonable applications may accelerate performance deterioration or short/open circuits as failure modes affecting the life end.
Adequate safety shall be ensured especially for product design required a high level of safety with the following
considerations.
1)Previously examine how a single trouble in this product affects the end product.
2)Design a protection circuit as Failsafe-design to avoid unsafe system resulting from a single trouble with this
product.
Whenever a doubt about safety arises from this product, immediately inform us for technical consultation without fail,
please.
2- 3.This specification is a part of contract documents pertaining to the trade made by and between your company and
Matsushita Electric Industrial Co., Ltd.
3. Part Number Code
ECJ
(1)
2
(2)
F
(3)
6
(4)
0J
(5)
226
(6)
M
(7)
3- 1.Common Code (1)
ECJ : Multilayer Ceramic Chip Capacitors
3- 2.Size (2), Packaging Styles (3), Temperature Characteristic (4), Rated Voltage (5), Capacitance Tolerance (7) :
Shown in Individual Specification.
Note ;
APPROVAL
Panasonic Electronic Devices Co., Ltd.
T.Kawamura
CHECK
T.Shinriki
DESIGN
A.Konishi
CLASSIFICATION
No.
151S-ECJ-KGS39E
PAGE
SPECIFICATION
SUBJECT
Multilayer Ceramic Chip Capacitors (EIA 0805)
High Capacitance (P/N : ECJ2F60J226M) Common Specification
3- 3.Nominal Capacitance (6)
The Nominal Capacitance value is expressed in pico farads(pF) and
is identified by a three-digit number ; the first two digit
represent significant figures and the last digit specifies the number of
zero to follow.
2 of 7
DATE
Symbol (Ex.)
105
475
106
Aug 28, 2008
Nominal Cap.
1000000pF (1 µF)
4700000pF (4.7 µF)
10000000pF (10 µF)
4. Operating Temperature Range
Shown in Individual Specification.
5. Performance
The performance of the capacitor and its test condition shall be specified in Table 2.
5- 1.Pretreatment
Before test and measurements, the following pretreatment shall be applied when necessary.
5-1-1. Heat Treatment
The capacitors shall be kept in a temperature of 150+0/-10°C for 1 hour and then shall be stored in a room temperature for 48±4 hours, before initial measurement.
5-1-2. Voltage Treatment
D.C. voltage shall be applied for 1 hour in the specified test condition and then shall be stored in a room temperature for 48 +/- 4 hours, before initial measurement.
6. Test
Unless otherwise specified, all test and measurements shall be made at a temperature of 15 to 35°C and at a relative
humidity of 45 to 75%.
If results obtained are doubted a further test should be carried out at a temperature of 20±2℃ and a relative humidity
of 60 to 70%.
7. Structure
The structure shall be in a monolithic form as shown in Fig. 1.
Fig. 1
Table 1
No.
①
②
③
④
⑤
.
Note ;
Name
Dielectric
Inner electrode
Substrate electrode
Intermediate electrode
External electrode
CLASSIFICATION
SPECIFICATION
SUBJECT
Multilayer Ceramic Chip Capacitors (EIA 0805)
High Capacitance (P/N : ECJ2F60J226M) Common Specification
No.
151S-ECJ-KGS39E
PAGE
3 of 7
DATE
Aug 28, 2008
Table 2
No
Contents
Performance
Test Method
1
Appearance
There shall be no defects which affect
the life and use.
With a magnifying glass (3 times).
2
Dimensions
Shown in Individual Specification.
With slide calipers and a micrometer.
3
Dielectric Withstanding voltage
There shall be no dielectric breakdown or damage.
4
Insulation
Resistance(I.R.)
100/C MΩ min.
(C : Nominal Cap. in µF)
Test voltage : 250 % of rated voltage
Apply a DC voltage of the above value for 1 to
5 seconds.
Charge/discharge current shall be within
50mA.
Measuring voltage : Rated voltage
Measuring voltage time : 60+/-5s
Charge/discharge current shall be within
50mA.
5
Capacitance
Shall be within the specified tolerance.
6
Dissipation Factor
(tan δ)
0.15 max.
Measuring
Frequency
120Hz+/-20%
Measuring
Voltage
0.5+/-0.2Vrms
For the class2 Capacitors, perform the heat
treatment in par. 5-1-1.
Our Measurement instrument is shown in the
Table 3.
7
Temperature
Coefficient
Without
Voltage
Application
Temp. Char.
X6S : Within +/- 22 %
Measure the capacitance at each stage by
changing the temperature in the order of step 1
to 4 shown in the table below. Calculate the
rate of change regarding the capacitance at
stage 3 as the reference.
(Unit : °C)
Temp.
Stage
Char.
1
2
3
4
5
X6S
25+/-2 -55+/-3 25+/-2 105+/-2 25+/-2
Measuring
Frequency
120Hz+/-20%
8
Adhesion
The terminal electrode shall be free
from peeling or signs of peeling.
Measuring
Voltage
0.5+/-0.2Vrms
Solder the specimen to the testing jig shown in
the figure., and apply a 5N force in the arrow
direction for 10 seconds.
Material : Alumina board (95% min.) or glass
epoxy board.
Thickness : 1.0mm min.
(continue)
Note ;
CLASSIFICATION
No.
151S-ECJ-KGS39E
PAGE
SPECIFICATION
SUBJECT
Multilayer Ceramic Chip Capacitors (EIA 0805)
High Capacitance (P/N : ECJ2F60J226M) Common Specification
4 of 7
DATE
Aug 28, 2008
Table 2
No
Performance
Test Method
9
Bending
Strength
Appearance
Capacitance
There shall be no cracks and other
mechanical damage.
Temp. Change from the value
Char.
before test.
X6S
Within +/- 12.5 %
After soldering capacitor on the substrate 1
mm of bending shall be applied for 5 seconds.
Bending speed : 1mm/s
(shown in Fig. 3)
10
Vibration
Proof
Appearance
Capacitance
There shall be no cracks and other
mechanical damage.
Shall be within the specified tolerance.
tan δ
Shall meet the specified initial value.
Solder the specimen to the testing jig shown
in Fig. 2. Apply a variable vibration of 1.5 mm
total amplitude in the 10 to 55 to10Hz vibration
frequency range swept in 1 min. in 3 mutually
perpendicular directions for 2 hours each, a
total of 6 hours.
Appearance
Capacitance
There shall be no cracks and other
mechanical damage.
Temp. Change from the value
Char.
before test.
X6S
Within +/- 7.5 %
tan δ
Shall meet the specified initial value.
I.R.
Shall meet the specified initial value.
With-stand
voltage
There shall be no dielectric breakdown or damage.
11
12
Contents
Resistance to
Solder
Heat
Solderability
More than 95% of the soldered area
of both terminal electrodes shall be
covered with fresh solder.
(continue)
Note ;
Solder both method
Preconditioning : Heat Temperature
(See 5.1.1)/Class2
Solder temperature : 270+/-5 °C
Dipping period : 3+/-0.5 s
Preheat condition :
Order
1
2
Temp.(°C)
80 to 100
150 to 200
Period(s)
120 to 180
120 to 180
Use solder H63A(JIS-Z-3282).For the flux,
use rosin (JIS-K-5902) ethanol solution of a
concentration of about 25% by weight. Use
tweezers for the holder to dip the specimen.
Recovery : 48+/-4 hours
Solder temperature : 230+/-5 °C
Dipping period : 4+/-1 s
Dip the specimen in solder so that both
terminal electrodes are completely submerged.
Use solder H63A(JIS-Z-3282). For the flux use
rosin (JIS-K-5902) of ethanol solution of a
concentration of about 25 % by weight.
Use tweezers for the holder to dip the
specimen.
CLASSIFICATION
SPECIFICATION
SUBJECT
Multilayer Ceramic Chip Capacitors (EIA 0805)
High Capacitance (P/N : ECJ2F60J226M) Common Specification
No.
151S-ECJ-KGS39E
PAGE
5 of 7
DATE
Aug 28, 2008
Table 2
No
13
Contents
Temperature
cycle
Performance
Appearance
There shall be no cracks and other
mechanical damage.
Capacitance
Temp.
Char.
X6S
tan δ
I.R.
Shall meet the specified initial value.
Withstand
voltage
Change from the value
before test.
Within +/- 7.5 %
Shall meet the specified initial value.
There shall be no dielectric breakdown or damage.
Test Method
Solder the specimen to the testing jig shown
in Fig. 2. Condition the specimen to each
temperature from step 1 to 4 in this order for
the period shown in the table below. Regarding this conditioning as one cycle, perform
5 cycles continuously.
Step
1
2
3
4
14
Moisture
Resistance
Appearance
There shall be no cracks and other
mechanical damage.
Capacitance
Temp. Change from the value
Char.
before test.
X6S
Within +/- 20 %
0.25 max.
tan δ
15
Moisture
Resistant
Loading
I.R.
10/C MΩ min.
(C : Nominal Cap. in µF)
Appearance
There shall be no cracks and other
Mechanical damage.
Capacitance
Temp. Change from the value
Char.
before test.
X6S
Within +/- 20 %
0.25 max.
tan δ
I.R.
5/C MΩ min.
(C : Nominal Cap. in µF)
Temperature
(°C)
Minimum operation
temperature +/- 3
Room temperature
Maximum operation
temperature +/-5
Room temperature
Period
(min.)
30+/-3
3 max.
30+/-3
3 max.
For the class2 capacitors, perform the heat
treatment in par. 5-1-1.
Before the measurement after test, the
specimen shall be left to stand at room
temperature for the following period :
48+/-4 h
For the class2 capacitors, perform the heat
treatment in par. 5-1-1.
Solder the specimen to the testing jig shown
in Fig. 2.
Test temperature : 40+/-2 °C
Relative humidity : 90 to 95 %
Test period : 500+24/0 h
Before the measurement after test, the specimen shall be left to stand at room temperature for the following period :
48+/-4 h
For the class2 capacitors, perform the heat
treatment in par. 5-1-2.
Solder the specimen to the testing jig shown
in Fig. 2.
Test temperature : 40+/-2 °C
Relative humidity : 90 to 95 %
Applied voltage : Rated voltage
(DC Voltage)
Charge/discharge current : within 50 mA.
Test period : 500+24/0 h
Before the measurement after test, the specimen shall be left to stand at room temperature for the following period :
48+/-4 h
(continue)
Note ;
CLASSIFICATION
SPECIFICATION
SUBJECT
Multilayer Ceramic Chip Capacitors (EIA 0805)
High Capacitance (P/N : ECJ2F60J226M) Common Specification
No.
151S-ECJ-KGS39E
PAGE
6 of 7
DATE
Aug 28, 2008
Table 2
No
16
Contents
High
Temperature Resistant
Loading
Performance
Appearance
There shall be no cracks and other
mechanical damage.
Capacitance
Temp.
Char.
X6S
tan δ
0.25 max.
I.R.
10/C MΩ min.
(C : Nominal Cap. in µF)
Change from the value before test.
Within +/- 20 %
Test Method
For the class2 capacitors, perform the voltage
treatment in par. 5-1-2.
Solder the specimen to the testing jig shown
in Fig. 2.
Test temperature :
Max. Rated temp. +/-3°C
Applied voltage : Rated voltage
(DC Voltage)
Charge/discharge current : within 50 mA.
Test period : 1000+48/0 h
Before the measurement after test, the specimen shall be left to stand at room temperature for the following period : 48+/-4 h
When uncertainty occurs in the weather resistance characteristic tests (temperature cycle, moisture resistance,
moisture resistant loading, high temperature resistant loading), the same tests shall be performed for the capacitor itself.
Table 3
Our Standard Measuring Instrument
Measuring Instrument
4284A Precision LCR Meter (Agilent Technologies)
Measuring Mode
Parallel Mode
Recommended
Measuring Jig
16034E Test Fixture (Agilent Technologies)
For High Cap Type, signal voltage may be unable to be applied to depending on conditions of measuring instruments.
We would appreciate it if you would confirm whether High Cap Type is under the measurable environment or not by
checking that the fixed signal voltage is applied or not. (For example, ALC function is ON, HPA is expanded.)
Note ;
CLASSIFICATION
No.
151S-ECJ-KGS39E
PAGE
SPECIFICATION
SUBJECT
Multilayer Ceramic Chip Capacitors (EIA 0805)
High Capacitance (P/N : ECJ2F60J226M) Common Specification
Fig. 2
7 of 7
DATE
Aug 28, 2008
Testing jig
Table 4
Size(EIA)
A
B
C
0805
1.2
4.0
1.65
Unit : mm
Material : Glass epoxy board
Thickness : 1.6 mm
:Copper foil (0.035 mm thick)
:Solder resist
Fig. 3
Testing jig
Table 5
Size(EIA)
A
B
C
0805
1.2
4.0
1.65
Unit : mm
Material : Glass epoxy board
Thickness : 1.6 mm
:Copper foil (0.035 mm thick)
:Solder resist
Note ;
CLASSIFICATION
SUBJECT
No.
151S-ECJ-SS018E
PAGE
SPECIFICATIONS
Multilayer Ceramic Chip Capacitor
Common Specification ( Precautions for Use)
1 of 9
DATE
Apr. 1, 2008
1. Precautions for Use
！
The Multilayer Ceramic Chip Capacitors (hereafter referred to as “Capacitors”) may fail in a short circuit mode in
an open-circuit mode when subjected to severe conditions of electrical, environmental and/or mechanical stress
beyond the specified “Rating and specified “Conditions” in the Specifications, resulting in burn out, flaming or
glowing in the worst case. The following “Precautions for Safety” and “Application Notes” shall be taken in your
major consideration for use.
2. Operating Conditions and Circuit Design
2- 1.Circuit Design
2-1-1. Operating Temperature and Storage Temperature
The specified “Operating Temperature Range” in the Specifications is the absolute maximum and minimum
temperature rating. Every circuit mounting a Capacitor shall be operated within the specified “Operating
Temperature Range”. The Capacitors mounted on PCB shall be stored without operating within the specified
“Storage Temperature Range” in the Specifications.
2-1-2. Design of Voltage application
The Capacitors shall not be operated exceeding the specified “Rated Voltage” in the Specification.
If voltage ratings are exceeded, the Capacitors could result in failure or damage. In case of application of DC
and AC voltages to the Capacitors, the designed peak voltage shall be within the specified “Rated Voltage”.
In case of AC of pulse voltage, the peak voltage shall be within the specified “Rated Voltage”. If high frequency
voltage or fast rising pulse voltage is applied continuously even within the “Rated Voltage”, contact our
engineering section before use. Such continuous application affects the life of the Capacitors.
2-1-3. Working Current
It is recommended to equip the Capacitors with protection circuits for safety reasons, as should the Capacitors
short circuit with voltages such as secondary voltage, there will be a serious risk that the Capacitors might
self-heat or circuit boards might burn out.
2-1-4. Self-Heating of Capacitors
When the Capacitors self-heat as a result of using AC or pulse voltage circuits and operate at room
temperatures (25deg.C max.), make sure that the Capacitors’ surface temperature does not exceed the ambient
temperature plus 20 deg.C (max.), or the maximum operating temperature specified in product specification for
approval. Also, the temperature of the Capacitors’ surface which varies with circuit types used should be
measured under the operational mode of devices mounted on by the Capacitors.
2-1-5. Restriction on Environmental Conditions
The Capacitors shall not be operated and / or stored under the following environmental conditions.
(1) Environmental conditions
(a) To be exposed directly to water or salt water
(b) To be dew formation
(c) Under conditions of corrosive gases such as hydrogen sulfide, sulfurous acid, chlorine and ammonia
(2) Under severe conditions of vibration or impact beyond the specified conditions in the Specifications
2-1-6. DC voltage characteristics
The capacitance of Class 2 Capacitors has voltage dependency, contributing to big capacitance fluctuations in
high DC voltage application. To secure specified capacitance, the following should be confirmed.
(1) That the capacitance fluctuations caused by voltage application are within the capacitance range of a circuit
used, or if the capacitance range of a circuit used is broad enough to maintain the Capacitors’ functions.
(2) DC voltage characteristics demonstrate, even if applied voltage is under the rated voltage, capacitance
change rate increases with higher voltage (Capacitance down). Accordingly, when the Capacitors are used
for circuits with narrow capacitance allowable range such as time constant circuits, we recommend to apply
lower voltage upon due consideration on capacitance aging in addition to the above.
Note ;
APPROVAL
Panasonic Electronic Devices Co., Ltd.
T.Kawamura
CHECK
T.Shinriki
DESIGN
A.Konishi
CLASSIFICATION
SUBJECT
SPECIFICATIONS
Multilayer Ceramic Chip Capacitor
Common Specification ( Precautions for Use)
No.
151S-ECJ-SS018E
PAGE
2 of 9
DATE
Apr. 1, 2008
Capacitance change vs. DC voltage
DC voltage (V)
2-1-7. Capacitance aging
The ceramic dielectrics of the Capacitors (Class 2) have capacitance aging. Accordingly, when the Capacitors
are used for the circuits, which require a narrow capacitance allowable range, such as time constant circuits,
pay due consideration to capacitance aging for use.
Under Ordinary Temperature
Before and After Heat treatment
Heat treatment
Time (h)
Time (h)
2-1-8. Piezoelectricity
Dielectrics used for the Capacitors (Class 2) may cause the following Piezoelectricity (or Electrostriction).
(1) If the signal of a specific frequency is applied to the Capacitors, electric and acoustic noise may be
generated by resonating the characteristic frequency which is determined by the dimensions of the
Capacitor.
As a measure to prevent this phenomenon, changing the size of the Capacitor is effective to change its
resonance frequency.
Also there is another measure changing the materials of the Capacitors to the Low-loss type, which has no
(or less) piezoelectricity, or to Class1.
which has no (or less) piezoelectricity, or to Class1 is also available.
(2) Vibration or impact applied to the Capacitors may cause noise because mechanical force is converted to
electrical signals (Especially, application to around the amplifier unit) .
As a measure to prevent this phenomenon, changing the materials of the Capacitor to the Low-loss type,
which has no (or less) piezoelectricity, or to Class1 is also available.
(3) Even if a whining sound is generated, there is no problem in product performance and reliability, however,
check the worrisome phenomenon which may generate noise in your equipment.
As a measure to prevent this phenomenon, changing to the Capacitor different in characteristics, size and
shape as shown in the (1), (2) above is effective.
As the other measures, changing the mounting direction of the Capacitors to bring under control the
resonance with equipment bodies such as printed circuit board, or the Capacitors are fixed with equipment
bodies such as printed circuit board by adhesive may be effective.
2- 2.Design of Printed Circuit Board
2-2-1. Selection of Printed Circuit Board
When the Capacitors are mounted and soldered on an Aluminum Substrate, the substrate has influences on
Capacitor’s reliabilities against “Temperature Cycles” and “Heat shock” because of difference in thermal
expansion coefficient between them.
It shall be carefully confirmed that the actual board applied does not deteriorate the characteristics of the
Capacitors.
Note ;
CLASSIFICATION
No.
151S-ECJ-SS018E
PAGE
SPECIFICATIONS
SUBJECT
Multilayer Ceramic Chip Capacitor
Common Specification ( Precautions for Use)
3 of 9
DATE
Apr. 1, 2008
2-2-2. Design of Land Pattern
(1) Recommended land dimensions are shown below for proper amount of solder to prevent cracking at the
time of excessive stress to the Capacitors due to increased amount of solder.
{ Recommended land dimensions (Ex.) }
[ For High Capacitance, General Electronic Equipment, Low ProfileType, 100V･200V series,
630V series, High-Q Capacitors ]
Unit in mm
SMD
c
Land
b
Solder
resist
a
Size
(EIA)
0201
0402
0603
0805
1206
1210
Component Dimension
L
W
T
0.6
0.3
0.3
1.0
0.5
0.5
1.6
0.8
0.8
2.0 1.25 0.6 to 1.25
3.2
1.6
0.6 to 1.6
3.2
2.5
0.8 to 2.5
Size
(EIA)
0508
0612
Component Dimension
Ｌ
Ｗ
Ｔ
1.25
2.0
0.85
1.6
3.2
0.85
a
b
c
0.2 to 0.3
0.4 to 0.5
0.8 to 1.0
0.8 to 1.2
1.8 to 2.2
1.8 to 2.2
0.25 to0.30
0.4 to 0.5
0.6 to 0.8
0.8 to 1.0
1.0 to 1.2
1.0 to 1.2
0.2 to 0.3
0.4 to 0.5
0.6 to 0.8
0.8 to 1.0
1.0 to 1.3
1.8 to 2.3
[ Wide-width Type ]
Land
SMD
c
Unit in mm
ｂ
ｃ
0.5 to 0.7
0.8 to 1.0
0.5 to 0.6
0.6 to 0.7
1.4 to 1.9
2.5 to 3.0
Solder
resist
a
b
ａ
[ Array Type ]
4 Array type
c
Unit in mm
P/2 P
a
b
Size
(EIA)
0805
4 Array
1206
4 Array
SMD
Component Dimension
L
W
T
2.0
1.25
0.85
3.2
1.6
0.85
a
b
c
P
0.55
to 0.75
0.9
to 1.1
0.5
to 0.6
0.7
to 0.9
0.2
to 0.3
0.35
to 0.45
0.4
to 0.6
0.7
to 0.9
Land
2 Array type
Unit in mm
a
b
c
P
SMD
Size
(EIA)
Land
0504
2 Array
Component
Dimension
L
W
T
0.6
1.37
1.0
0.8
a
b
c
P
0.3
to 0.4
0.3
to 0.6
0.45
to 0.55
0.4
to 0.7
0.3
to 0.4
0.46
to 0.56
0.54
to 0.74
0.71
to 0.91
(2) The size of lands shall be designed to be equal between the right and left sides. If the amount of solder on
the right land is different from that on the left land, the component may be cracked by stress to one side of
the component since the side with a larger amount of solder solidifies later at the time of cooling.
Recommended Amount of Solder
(a) Excessive amount
of solder
(b) Proper amount
of solder
←solder
Note ;
(c)Insufficient amount
of solder
←solder
←solder
↑
↑
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PC
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CLASSIFICATION
SUBJECT
No.
151S-ECJ-SS018E
PAGE
SPECIFICATIONS
Multilayer Ceramic Chip Capacitor
Common Specification ( Precautions for Use)
4 of 9
DATE
Apr. 1, 2008
2-2-3. Utilization of Solder Resist
The application of solder resist is effective in preventing solder bridges and controlling the amount of solder on
PC boards.
(1)Solder resist shall be utilized to equalize the amounts of solder on both sides.
(2)Solder resist shall be used to divide the pattern for the following cases;
･Components are arranged closely.
･The Capacitor is mounted near a component with lead wires.
･The Capacitor is placed near a chassis.
See the table below.
Mixed mounting
with a component with
lead wires
Arrangement
near chassis
Prohibited Applications and Recommended Applications
Prohibited applications
Improved applications by pattern division
The lead wire of
Solder resist
a component with
lead wires
Sectional view
Chassis
Solder (ground solder)
Retrofitting of
Component with lead
wires
Soldering iron
Lateral arrangement
Land
Sectional view
Lead wire of
Retrofitted
component
Sectional view
Solder resist
Sectional view
Solder resist
Sectional view
Portion to be
excessively
soldered
Sectional view
Solder resist
2-2-4. Component Layout
The Capacitors / components shall be placed on the PC board such that both electrodes are subjected to
uniform stresses, or to position the component electrodes at right angles to the grid glove or bending line. This
should be done to avoid cracking the Capacitors from bending the PC board after or during placing/mounting on
the PC board.
(1) To minimize mechanical stress caused by warp or bending of a PC board, please follow the recommended
Capacitor layout below.
Prohibited layout
Recommended layout
Lay out the Capacitor
sideways against the
stressing direction
Warp of
Circuit board
(2) The following drawing is for your reference since
mechanical stress near the dividing/breaking
position of a PC board varies depending on the
mounting position of the Capacitors.
(3) The magnitude of mechanical stress applied to
the Capacitors when the circuit board is divided is
in the order of push back < slit < V-groove <
perforation.
Also take into account the layout of the
Capacitors and the dividing/breaking method.
E
D
Perforation
C
A
B
Slit
Magnitude of stress A＞B＝C＞D＞E
Note ;
CLASSIFICATION
SUBJECT
No.
151S-ECJ-SS018E
PAGE
SPECIFICATIONS
Multilayer Ceramic Chip Capacitor
Common Specification ( Precautions for Use)
5 of 9
DATE
Apr. 1, 2008
2-2-5. Mounting Density and Spaces
If components are arranged in too narrow spaces, the
components are affected by Solder bridges and
Solder balls. Each space between components
should be carefully determined.
3. Precautions for Assembly
3- 1.Storage
(1) The Capacitors before mounting on PCB shall be stored between 5 - 40°C and 20 - 70% RH, not under severe
conditions of high temperature and humidity.
(2) If stored in a place that is humid, dusty, or contains corrosive gasses (hydrogen sulfide, sulfurous acid,
hydrogen chloride and ammonia, etc.), the solderability of terminal electrodes may deteriorate.
In addition, storage in a place subjected to heating and/or exposed to direct sunlight will cause deformed tapes
and reels. and component sticking to tapes, both of which can result in mounting problems.
(3) Do not store components longer than 6 months. Check the solderability of products that have been stored for
more than 6 months before use.
(4) The Capacitors of high dielectric constant series (Class 2, Characteristic B,X7R,X5R and F,Y5V) change in
capacitance with the passage of time, “Capacitance aging”, due to the inherent characteristics of ceramic
dielectric materials. The changed capacitance can be recovered by heat treatment to each initial value at the
time of shipping. (See 2. Operating Condition and Circuit Design, 2-1-7. Capacitance aging)
(5) When the initial capacitance is measured, the Capacitors shall be heat-treated at 150+0/-10℃ for 1 hour and
then subjected to ordinary temperature and humidity for 48±4 hours before measuring the initial value.
3- 2.Chip Mounting Consideration
(1) When mounting the Capacitors/components on a PC board, the capacitor bodies shall be free from excessive
impact loads such as mechanical impact or stress in the positioning, pushing force and displacement of vacuum
nozzles at the time of mounting.
(2) Maintenance and inspections for Chip Mounter must be performed regularly.
(3) If the bottom dead center of the vacuum nozzle is too low, the Capacitor is cracked by an excessive force at the
time of mounting.
The following precautions and recommendations are for your reference in use.
(a) Set and adjust the bottom dead center of the vacuum nozzles to the upper surface of the PC board after
correcting the warp of the PC board.
(b) Set the pushing force of the vacuum nozzle at the time of mounting to 1 to 3 N in static load.
(c) For double surface mounting, apply a supporting pin on the rear surface of the PC board to suppress the
bending of the PC board in order to minimize the impact of the vacuum nozzles. The typical examples are
shown in the table below.
(d) Adjust the vacuum nozzles so that their bottom dead center at the time of mounting is not too low.
(4) The closing dimensions of positioning chucks shall be controlled and the maintenance, checks and replacement
of positioning chucks shall be regularly performed to prevent chipping or cracking of the Capacitors caused by
mechanical impact at the time of positioning due to worn positioning chucks.
(5) Maximum stroke of the nozzle shall be adjusted so that the maximum bending of PC board does not exceed
0.5mm at 90mm span. The PC board shall be supported by means of adequate supporting pins.
Prohibited mounting
Recommended mounting
Crack
Single surface
mounting
Supporting
pin
Double surface
mounting
Separation
of solder
Note ;
Crack
Supporting
pin
The supporting pin must not
be necessarily positioned
beneath the capacitor.
CLASSIFICATION
SUBJECT
SPECIFICATIONS
Multilayer Ceramic Chip Capacitor
Common Specification ( Precautions for Use)
No.
151S-ECJ-SS018E
PAGE
6 of 9
DATE
Apr. 1, 2008
3- 3.Selection of Soldering Flux
Soldering flux may seriously affect the performance of the Capacitors. The following shall be confirmed before use.
(1) The soldering flux should have a halogen based content of 0.1 wt. % (converted to chlorine) or below.
Do not use soldering flux with strong acid.
(2) When applying water-soluble soldering flux, wash the Capacitors sufficiently because the soldering flux residue
on the surface of PC boards may deteriorate the insulation resistance on the Capacitor’s surface.
3- 4.Soldering
3-4-1. Reflow soldering
The reflow soldering temperature conditions are each temperature curves of Preheating, Temp. rise, Heating,
Peak and Gradual cooling. Large temperature difference caused by rapid heat application to the Capacitors
may lead to excessive thermal stresses, contributing to the thermal cracks. The Preheating temperature
requires controlling with great care so that tombstone phenomenon may be prevented.
Temperature
140 to 180 ℃
Preheating temp. to Peak temp.
220 ℃ min.
260 ℃ max.
Peak temp. to 140 ℃
①Preheating
②Temp. rise
③Heating
④Peak
⑤Gradual cooling
Period or Speed
60 to 120 s
2 to 5 ℃/s
60 s max.
10 s max.
1 to 4 ℃/s
The rapid cooling (forced cooling) during Gradual cooling part should be avoided, because this may cause
defects such as the thermal cracks, etc.
When the Capacitors are immersed into a cleaning solvent, confirm that the surface temperature of the devices
does not exceed 100℃.
Performing reflow soldering twice under the conditions shown in the figure above [Recommended profile of
Reflow soldering (EX)] will not cause any problems. However, pay attention to the possible warp and bending
of the PC board.
Recommended profile of Reflow soldering (Ex.)
④Peak
220
ΔT
Temperature (℃)
260
②Temp. rise
⑤Gradual
cooling
180
140
①Preheating
③Heating
60 to 120 s
60 s max.
Time
Note ;
〈 Allowable temperature difference ∆T〉
Size
Temp. Tol.
0201 to 1206
∆T≦ 150 °C
0508, 0612, 0504
1210
∆T≦ 130 °C
CLASSIFICATION
SUBJECT
SPECIFICATIONS
Multilayer Ceramic Chip Capacitor
Common Specification ( Precautions for Use)
No.
151S-ECJ-SS018E
PAGE
7 of 9
DATE
Apr. 1, 2008
3-4-2. Hand soldering
Hand soldering typically causes significant temperature change, which may induce excessive thermal stresses
inside the Capacitors, resulting in the thermal cracks, etc.
In order to prevent any defects, the following should be observed;
・The temperature of the soldering tips should be controlled with special care.
・The direct contact of soldering tips with the Capacitors and/or terminal electrodes should be avoided.
・Dismounted Capacitors shall not be reused.
(1) Condition 1 (with preheating)
(a) Soldering :
φ1.0mm or below Thread eutectic solder with soldering flux* in the core.
*Rosin-based and non-activated flux is recommended.
(b) Preheating:
The Capacitors shall be preheated so that the “Temperature Gradient” between the devices and the tip
of soldering iron is 150℃ or below.
(c) Temperature of Iron tip: 300℃ max.
(The required amount of solder shall be melted in advance on the soldering tip.)
(d) Gradual Cooling:
After soldering, the Capacitors shall be cooled gradually at room ambient temperature.
Recommended profile of Hand Soldering [Ex.]
Soldering
Gradual
cooling
∆T
〈Allowable temperature difference ∆T〉
Size
Temp. Tol.
0201 to 1206
∆T≦ 150 °C
0508, 0612, 0504
1210
∆T≦ 130 °C
Preheating
60 to 120 s
3 s max.
(2) Condition 2 (without preheating)
Hand soldering can be performed without preheating, by following the conditions below:
(a) Soldering iron tip shall never directly touch the ceramic dielectrics and terminal electrodes of the
Capacitors.
(b) The lands are sufficiently preheated with a soldering iron tip before sliding the soldering iron tip to the
terminal electrodes of the Capacitor for soldering.
Conditions of Hand soldering without preheating
Condition
Chip size
0201 to 0805, 0508, 0504
1206 to 1210 , 0612
Temperature of soldering iron
270 °C max.
250 °C max.
Wattage
20W max.
Shape of soldering iron tip
φ3mm max.
Soldering time with soldering iron
3s max.
3- 5.Post Soldering Cleaning
3-5-1. Cleaning solvent
Soldering flux residue may remain on the PC board if cleaned with an inappropriate solvent. This may deteriorate
the electrical characteristics and reliability of the Capacitors.
3-5-2. Cleaning conditions
Inappropriate cleaning conditions such as insufficient cleaning or excessive cleaning may impair the electrical
characteristics and reliability of the Capacitors.
(1) Insufficient cleaning can lead to:
(a) The halogen substance in the residues of the soldering flux to cause the metal of terminal electrodes to
corrode.
(b) The halogen substance in the residue of the soldering flux on the surface of the Capacitors may change
resistance values.
Note ;
CLASSIFICATION
SUBJECT
No.
151S-ECJ-SS018E
PAGE
SPECIFICATIONS
Multilayer Ceramic Chip Capacitor
Common Specification ( Precautions for Use)
8 of 9
DATE
Apr. 1, 2008
(c) Water-soluble soldering flux may have more remarkable tendencies of (a) and (b) above compared to
those of rosin soldering flux.
(2) Excessive cleaning can lead to:
(a) Overuse of ultrasonic cleaning may deteriorate the strength of the terminal electrodes or cause cracking
in the solder and/or ceramic bodies of the Capacitors due to vibration of the PC boards.
Please follow these conditions for Ultrasonic cleaning:
Ultrasonic wave output
: 20 W/L max.
Ultrasonic wave frequency
: 40 kHz max.
Ultrasonic wave cleaning time : 5 minutes max.
3-5-3. Contamination of Cleaning solvent
Cleaning with contaminated cleaning solvent may cause the same results as insufficient cleaning due to the high
density of liberated halogen.
3- 6.Inspection Process
When mounted PC boards are inspected with measuring terminal pins, abnormal and excess mechanical stress
shall not be applied to the PC board or mounted components, to prevent failure or damage to the devices.
(1) Mounted PC boards shall be supported by an adequate number of supporting pins with bend settings of 90 mm
span 0.5mm max.
(2) Confirm that the measuring pins have the right tip shape, are equal in height and are set in the correct positions.
The following figures are for your reference to avoid bending the PC board.
Prohibited setting
Recommended setting
Check pin
Check pin
Bending of PC board
Supporting
pin
Separated
3- 7.Protective Coating
When the surface of a PC board on which the Capacitors have been mounted is coated with resin to protect against
moisture and dust, it shall be confirmed that the protective coating which is corrosive or chemically active is not
used, in order that the reliability of the Capacitors in the actual equipment may not be influenced. Coating materials
that expand or shrink also may lead to damage to the Capacitor during the curing process.
Bending
3- 8.Dividing/Breaking of PC Boards
(1) Abnormal and excessive mechanical stress such as bending or torsion
shown below can cause cracking in the Capacitors.
Torsion
(2) Dividing/Breaking of the PC boards shall be done carefully at moderate
speed by using a jig or apparatus to prevent the Capacitors on the boards
from mechanical damage.
(3) Examples of PCB dividing/breaking jigs:
When PC boards are broken or divided, loading points should be close to the jig to minimize the extent of
the bending
Also, planes with no parts mounted on should be used as plane of loading, which generates a compressive
stress on the mounted plane, in order to prevent tensile stress induced by the bending, which may cause cracks
of the Capacitors or other parts mounted on the PC boards.
Outline of Jig
PC board
Prohibited dividing
V-groove
Recommended dividing
Load direction
Load position
V-groove
PC board
PC board
PC board
splitting jig
Note ;
Chip component
V-groove
Load position
Load direction
CLASSIFICATION
SUBJECT
No.
151S-ECJ-SS018E
PAGE
SPECIFICATIONS
Multilayer Ceramic Chip Capacitor
Common Specification ( Precautions for Use)
9 of 9
DATE
Apr. 1, 2008
3- 9.Mechanical Impact
(1) The Capacitors shall be free from any excessive mechanical impact.
The Capacitor body is made of ceramics and may be damaged or cracked
if dropped.
Never use a Capacitor which has been dropped; their quality may be
impaired and failure rate increased.
Crack
Floor
(2) When handling PC boards with Capacitors mounted on them, do not allow
the Capacitors to collide with another PC board.
When mounted PC boards are handled or stored in a stacked state, impact
between the corner of a PC board and the Capacitor may cause damage or
cracking and can deteriorate the withstand voltage and insulation
resistance of the Capacitor.
Crack
4. Other
For special mounting conditions, please contact us.
Precautions for Use above are from
The Technical Report EIAJ RCR-2335 Caution Guide Line for Operation of Fixed Multilayer
Ceramic Capacitors for Electronic Equipment by Japan Electronics and Information Technology
Industries Association (March 2002 issued)
Please refer to above technical report for details.
Note ;
Mounted PCB
CLASSFICATION
SUBJECT
No.
151S-ECJ-SV045E
PAGE
SPECIFICATIONS
Multilayer Ceramic Chip Capacitor (Size:0201 to 1812)
Packaging Specifications
1 of 6
DATE
Sep. 13, 2006
1. Scope
This specification applies to taped and reeled packing for Multilayer ceramic chip capacitors Size: EIA 0201, EIA 0402,
EIA 0603,EIA 0805, EIA 1206, EIA 1210 and EIA 1812.
2. Applicable Standards
EIAJ (Electric Industries Association of Japan) Standard EIAJ RC-1009B
JIS (Japanese Industrial Standard) Standard JIS C 0806
3. Packing Specification
3- 1.Structure and Dimensions
Paper taping packaging is carried out according the following diagram
1) Carrier tape
: Shown in Fig. 6.
2) Reel
: Shown in Fig. 7.
3) Packaging
: We shall pack suitably in order prevent damage during transportation or storage.
3- 2.Packing Quantity
Carrier-Tape
Size
Thickness of
Capacitor(mm)
0201
0.30 +/- 0.03
0402
0.50 +/- 0.05
0.8 +/- 0.1
0.80 +/- 0.15
0.6 +/- 0.1
0.85 +/- 0.10
1.25 +/- 0.10
1.25 +/- 0.15
1.25 +/- 0.20
0.6 +/- 0.1
0.85 +/- 0.10
1.15 +/- 0.10
1.6 +/- 0.2
2.0 +/- 0.2
2.5 +/- 0.3
2.5 +/- 0.3
0603
0805
1206
1210
1812
Quantity (pcs./reel)
φ330mm Reel
Packaging
Packaging
Quantity
Quantity
Code
Code
φ180mm Reel
Material
Taping
Pitch
Paper Tape
(Press Carrier Tape)
2mm
E
15000
---
---
2mm
E
10000
W
50000
4mm
V
4000
Z
10000
4mm
4mm
V
V
5000
4000
Z
Z
20000
10000
Embossed Tape
4mm
F
3000
---
---
Paper Tape
(Punch Carrier Tape)
4mm
4mm
4mm
4mm
4mm
4mm
8mm
V
V
F
Y
Y
Y
Y
5000
4000
3000
2000
2000
1000
500
Z
Z
-----------
20000
10000
-----------
APPROVAL
CHECK
Paper Tape
(Punch Carrier Tape)
Embossed Tape
Explanation of Part Numbers (Example)
ECJ
1
V
B
1C
104
K
Packaging Code
3- 3.Marking on the Reel
The following items are described in the side of a reel in English at least.
1) Part Number
2) Quantity
3) Lot Number
4) Place of origin
Note ;
Panasonic Electronic Devices Co., Ltd.
Y.Sakaguchi T.Kawamura
DESIGN
A.Konishi
CLASSFICATION
SUBJECT
No.
151S-ECJ-SV045E
PAGE
SPECIFICATIONS
Multilayer Ceramic Chip Capacitor (Size:0201 to 1812)
Packaging Specifications
2 of 6
DATE
Sep. 13, 2006
3- 4.Structure of Taping
1) The direction of winding of taping on the reel shall be in accordance with the following diagram.
Fig. 1 Paper Tape
Press Carrier Tape
Punch Carrier Tape
Top cover tape (thickness : 0.1mm max.)
(antistatic finished polyester)
Top cover tape (thickness : 0.1mm max.)
(antistatic finished polyester)
Press Carrier Tape (paper)
Polystyrene reel
(mixed with antistatic agent)
Punch Carrier Tape (paper)
Bottom tape
Bottom tape
(thickness : 0.1mm max.)
(thickness : 0.1mm max.)
Polystyrene reel
(mixed with antistatic agent)
Fig. 2 Embossed Tape
2) The specification of the leader and empty portion shall be in accordance with the following diagram.
Fig. 3 Leader Part and Taped End
100mm min.
160mm min.
Note ;
400mm min.
CLASSFICATION
SUBJECT
No.
151S-ECJ-SV045E
PAGE
SPECIFICATIONS
Multilayer Ceramic Chip Capacitor (Size:0201 to 1812)
Packaging Specifications
3 of 6
DATE
Sep. 13, 2006
4. Efficiency
4- 1.Breakage strength of the tape : 10N or more.
4- 2.Peel strength of the cover tape (refer to the Fig.4, 5).
1) Peel angle : 165 to 180 degree from the tape adhesive face.
2) Peel velocity : 300mm per min.
3) Peel strength : 0.1 to 0.7N
Fig. 4 Paper Tape
Press Carrier Tape
Punch Carrier Tape
Fig. 5 Embossed Tape
4- 3.Barrs on tape
There shall be no barrs preventing suction when products are taken out.
4- 4.Missing of products
The missing of products shall be 0.1% or less per reel and there shall be no continuous missing of products.
4- 5.Adherence to the tape
Products shall not be stuck to the cover tape or bottom tape.
Fig. 6 Carrier Tape Dimension
(a) Size 0201 : 2mm pitch for Paper tape (Press Carrier Tape)
Code
W
F
E
P1
P2
P0
φ D0
t
K0
K0
Size
Code
A
B
Note ;
0201
0.36 +/- 0.03
0.66 +/- 0.03
Dimension
8.0 ± 0.2
3.50 ± 0.05
1.75 ± 0.10
2.00 ± 0.05
2.00 ± 0.05
4.0 ± 0.1
1.5 +0.1/0
0.55 max.
0.36 ± 0.03
Unit : mm
CLASSFICATION
SUBJECT
SPECIFICATIONS
Multilayer Ceramic Chip Capacitor (Size:0201 to 1812)
Packaging Specifications
No.
151S-ECJ-SV045E
PAGE
4 of 6
DATE
Sep. 13, 2006
(b) Size 0402 : 2mm pitch for Paper tape (Punch Carrier Tape)
Code
W
F
E
P1
P2
P0
φ D0
t1
t2
Size
Code
A
B
Dimension
8.0 +/- 0.2
3.50 +/- 0.05
1.75 +/- 0.10
2.00 +/- 0.05
2.00 +/- 0.05
4.0 +/- 0.1
1.5 +0.1/0
0.7 max.
1.0 max.
Unit : mm
0402
0.62 +/- 0.05
1.12 +/- 0.05
(c) Size 0603, 0805 and 1206 : 4mm pitch for Paper tape (Punch Carrier Tape)
Code
W
F
E
P1
P2
P0
φ D0
t1
t2
Size
Code
A
B
Note ;
0603
0805
1206
1.05 +/- 0.10
1.85 +/- 0.10
1.65 +/- 0.20
2.4 +/- 0.2
2.0 +/- 0.2
3.6 +/- 0.2
Dimension
8.0 +/- 0.2
3.50 +/- 0.05
1.75 +/- 0.10
4.0 +/- 0.1
2.00 +/- 0.05
4.0 +/- 0.1
1.5 +0.1/0
1.2 max.
1.5 max.
Unit : mm
CLASSFICATION
SUBJECT
No.
151S-ECJ-SV045E
PAGE
SPECIFICATIONS
Multilayer Ceramic Chip Capacitor (Size:0201 to 1812)
Packaging Specifications
5 of 6
DATE
Sep. 13, 2006
(d) Size 0805 , 1206 and 1210 : 4mm pitch for Embossed tape
Code
W
F
E
P1
P2
P0
φ D0
φ D1
t1
t2
Size
Code
A
B
0805
1206
1210
1.55 +/- 0.20
2.35 +/- 0.20
1.9 +/- 0.2
3.5 +/- 0.2
2.8 +/- 0.2
3.5 +/- 0.2
Dimension
8.0 +/- 0.2
3.50 +/- 0.05
1.75 +/- 0.10
4.0 +/- 0.1
2.00 +/- 0.05
4.0 +/- 0.1
1.5 +0.1/0
1.1+/- 0.1
0.6 max.
Size0805 2.5
Size1206 max.
3.5
Size1210
max.
Unit : mm
(e) Size: 1812 : 8mm pitch for Embossed tape
Code
W
F
E
P1
P2
P0
φ D0
φ D1
t1
Dimension
12.0 +/- 0.3
5.50 +/- 0.05
1.75 +/- 0.10
8.0 +/- 0.1
2.00 +/- 0.05
4.0 +/- 0.1
1.5 +0.1/0
1.6 +/- 0.2
0.6 max.
t2
4.0max.
Unit : mm
Size
Code
A
B
Note ;
1812
3.6 +/- 0.3
4.9 +/- 0.3
CLASSFICATION
SUBJECT
No.
151S-ECJ-SV045E
PAGE
SPECIFICATIONS
Multilayer Ceramic Chip Capacitor (Size:0201 to 1812)
Packaging Specifications
6 of 6
DATE
Sep. 13, 2006
Fig. 7 Reel Dimension
(a) φ180mm Reel (Standard Reel)
Code
A
B
C
D
E
W
W1
Dimension
φ180+0/-3.0
φ60 +/- 0.5
13.0 +/- 0.5
21.0 +/- 0.8
2.0 +/- 0.5
Tape width
9.0
: 8 mm
+/- 0.3
Tape width
13.0
: 12 mm
+/- 0.3
Tape width
11.4
: 8 mm
+/- 1.0
Tape width
15.4
: 12 mm
+/- 1.0
Unit : mm
(b) φ330mm Reel (Large size Reel)
Code
A
B
C
D
E
W
W1
Note ;
Dimension
φ330 +/- 5
φ50 min.
13.0 +/- 0.5
20 min.
2.0 +/- 0.5
9.5 +/- 1.0
2.0 +/- 0.5
Unit : mm
