Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
http://www.semicon.panasonic.co.jp/en/
8A Synchronous DC-DC Step down Regulator
(VIN = 4.75 V to 24 V, VOUT = 0.75 V to 3.6 V)
FEATURES
DESCRIPTION
High-Speed Response DC-DC Step Down Regulator
Circuit that employs Hysteretic Control System
Skip (discontinuous) mode for Light Load Efficiency
Up to 8 A Output Current
Input VoltageRange : AVIN : 4.75 V to 24 V
PVIN : 4.75 V to 24 V
VREG : 4.5 V to 5.5 V
Output Voltage Range : 0.75 V to 3.6 V
Selectable Switching Frequency
: 220 kHz, 410 kHz, 580 kHz
Adjustable Soft Start
Low Operating and Standby Quiescent Current
Power Good Indication for Output
Over and Under Voltage
Built-in Under Voltage Lockout (UVLO),
Thermal Shut Down (TSD),
Over Voltage Detection (OVD),
Under Voltage Detection (UVD),
Over Current Protection (OCP),
Short Circuit Protection (SCP)
24pin Plastic Quad Flat Non-leaded Package Heat
Slug Down (QFN Type)
( Size : 4 mm 4 mm 0.7 mm, 0.5 mm pitch )
NN30421A is a synchronous DC-DC Step down
Regulator (1-ch) comprising of a Controller IC and two
power MOSFETs employing hysteretic control
system.
By this system, when load current changes suddenly, it
responds at high speed and minimizes the changes of
output voltage.
Since it is possible to use capacitors with small
capacitance and it is unnecessary to add external parts
for system phase compensation, this IC realizes
downsizing of set and reducing in the number of
external parts. Output voltage is adjustable by user.
Maximum current is 8 A.
APPLICATIONS
High Current Distributed Power Systems such as
・HDDs (Hard Disk Drives)
・SSDs (Solid State Drives)
・PCs
・Game consoles
・Servers
・Security Cameras
・Network TVs
・Home Appliances
・OA Equipment etc.
TYPICAL APPLICATION EXAMPLE
EFFICIENCY CURVE
Frequency = 410 kHz
VREG
VREG
1uF
100
VREG
PVIN
80
70
PGOOD
NN30421A
VOUT
0.1uF
LX
DCDCOUT
1.05 V
1uH
22uF x 5
VFB
SS
FCCM/ Vo= 1.05V
FCCM/ Vo= 1.2V
FCCM/ Vo= 1.8V
FCCM/ Vo= 3.3V
SKIP/ Vo= 1.05V
SKIP/ Vo= 1.2V
SKIP/ Vo= 1.8V
SKIP/ Vo= 3.3V
60
AGND PGND
50
40
30
20
10
Notes) The application circuit is an example. The operation of
the mass production set is not guaranteed. Sufficient
evaluation and verification is required in the design of
the mass production set. The Customer is fully
responsible for the incorporation of the above illustrated
application circuit in the design of the equipment.
10.000
1.000
0.100
0.010
0
10nF
0.001
1k
750
AVIN
12nF
100k Ω
BST
AVIN
4.7uF
90
EN
Efficiency (%)
0.1uF
22uF
PVIN
IOUT (A)
Condition :
VIN = 12V, VREG = 5V, VOUT Setting = 1.05V, 1.2 V, 1.8 V, 3.3 V,
Switching Frequency = 410kHz, FCCM / Skip mode,
LO = 1 µH, CO = 110 µF ( 22 µF x 5 )
Page 1 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
ORDERING INFORMATION
Order Number
Feature
Package
Output Supply
NN30421A-VB
Maximum Output Current : 8A
24 pin HQFN
Emboss Taping
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Notes
VIN
30
V
*1
VREG
6
V
*1
Operating free-air temperature
Topr
– 40 to + 85
C
*2
Operating junction temperature
Tj
– 40 to + 150
C
*2
Storage temperature
Tstg
– 55 to + 150
C
*2
Input Voltage Range
VMODE,VFSEL,VOUT,VFB, VEN
– 0.3 to 6.0
V
*1
VPGOOD
– 0.3 to 6.0
V
*1
VLX
– 0.3 to ( VIN + 0.3 )
V
*1
*3
HBM
2
kV
—
Supply voltage
Output Voltage Range
ESD
Notes) This product may sustain permanent damage if subjected to conditions higher than the above stated absolute
maximum rating. This rating is the maximum rating and device operating at this range is not guaranteed as it
is higher than our stated recommended operating range.
When subjected under the absolute maximum rating for a long time, the reliability of the product may be affected.
VIN is voltage for AVIN, PVIN. AVIN = PVIN. VREG is voltage for VREG.
Do not apply external currents and voltages to any pin not specifically mentioned.
*1 : The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
*2 : Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25 C.
*3 : ( VIN + 0.3 ) V must not exceed 30 V.
Page 2 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
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NN30421A
POWER DISSIPATION RATING
Package
24pin Plastic Quad Flat Non-leaded
Package Heat Slug Down (QFN Type)
j-a
j-C
PD
(Ta = 25 C)
PD
(Ta = 85 C)
Notes
58.0 C /W
7.2 C / W
2.155 W
1.120 W
*1
35.7 C /W
4.7 C / W
3.501 W
1.820 W
*2
Notes) For the actual usage, please refer to the PD-Ta characteristics diagram in the package specification, follow the power supply
voltage, load and ambient temperature conditions to ensure that there is enough margin and the thermal design does not
exceed the allowable value.
*1:Glass Epoxy Substrate ( 4 Layers ) [ Glass-Epoxy: 50 X 50 X 0.8 t ( mm ) ]
*2:Glass Epoxy Substrate ( 4 Layers ) [ Glass-Epoxy: 50 X 50 X 1.57 t ( mm ) ]
CAUTION
Although this IC has built-in ESD protection circuit, it may still sustain permanent damage if not handled
properly. Therefore, proper ESD precautions are recommended to avoid electrostatic damage to the
MOS gates.
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply voltage range
Input Voltage Range
Output Voltage Range
Pin Name
Min.
Typ.
Max.
Unit
Notes
AVIN
4.75
12
24
V
—
PVIN
4.75
12
24
V
—
VREG
4.5
5.0
5.5
V
—
VMODE
– 0.3
—
6.0
V
—
VFSEL
– 0.3
—
6.0
V
—
VEN
– 0.3
—
5.0
V
—
VPGOOD
– 0.3
—
6.0
V
—
VLX
– 0.3
—
VIN + 0.3
V
*1
Note) Voltage values, unless otherwise specified, are with respect to GND.
GND is voltage for AGND, PGND. AGND = PGND
VIN is voltage for AVIN, PVIN. VIN = AVIN = PVIN.
Do not apply external currents and voltages to any pin not specifically mentioned.
*1 : ( VIN + 0.3 ) V must not exceed 30 V.
Page 3 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
ELECTRICAL CHARACTERISTICS
Co = 22 µF x 5, Lo= 1 µH, VOUT Setting = 1.05 V, VIN = AVIN = PVIN = 12 V, VREG = 5 V,
Switching Frequency = 410 kHz, VMODE = VREG (FCCM), Ta = 25 C 2 C unless otherwise noted.
Parameter
Symbol
Condition
Limits
Unit Note
Min
Typ
Max
IVDDACT
VEN= 5 V, IOUT = 0 A
VRFB1 = 750 Ω
VRFB2 = 1k Ω
VMODE = GND
( Skip mode )
—
220
300
µA
—
VREG consumption current at active
IVREGACT
VEN= 5 V, IOUT = 0 A
VRFB1 = 750 Ω
VRFB2 = 1k Ω
VMODE = GND
( Skip mode )
—
430
550
µA
—
VIN consumption current at standby
IVDDSTB
VEN = 0 V
—
2
4
µA
—
VREG consumption current at
standby
IVREGSTB
VEN = 0 V
–1
—
1
µA
—
Current Consumption
VIN consumption current at active
Logic Pin
EN pin Low-level input voltage
VENL
—
—
—
0.3
V
—
EN pin High-level input voltage
VENH
—
1.5
—
5.0
V
—
—
6.25
12.5
µA
—
EN pin leak current
ILEAKEN
MODE pin Low-level input voltage
VMODEL
—
—
—
VREG
x 0.3
V
—
MODE pin High-level input voltage
VMODEH
—
VREG
x 0.7
—
VREG
V
—
—
3.25
6.5
µA
—
MODE pin leak current
ILEAKMODE
VEN = 5 V
VMODE = 5 V
FSEL pin Low-level input voltage
VFSELL
—
—
—
0.3
V
—
FSEL pin High-level input voltage
VFSELH
—
—
VREG
– 0.1
—
V
*1
—
15.0
25.0
µA
—
FSEL pin leak current
ILEAKFSEL
VFSEL = 5 V
*1 ： Typical design value.
Page 4 of 32
Established : 2012-12-18
Revised
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Revision. 2
Under
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NN30421A
ELECTRICAL CHARACTERISTICS ( Continued )
Co = 22 µF x 5, Lo= 1 µH, VOUT Setting = 1.05 V, VIN = AVIN = PVIN = 12 V, VREG = 5 V,
Switching Frequency = 410 kHz, VMODE = VREG (FCCM), Ta = 25 C 2 C unless otherwise noted.
Parameter
Symbol
Condition
VFBTH
—
Limits
Unit Note
Min
Typ
Max
0.594
0.600
0.606
V
—
VFB Characteristics
VFB comparator threshold
VFB pin leak current 1
ILEAKFB1
VFB = 0 V
–1
—
1
µA
—
VFB pin leak current 2
ILEAKFB2
VFB = 6 V
–1
—
1
µA
—
Under Voltage Lock Out
VIN UVLO start voltage
VIUVLODET
VIN = 5 V to 0 V
3.05
3.75
4.45
V
—
VIN UVLO recover voltage
VIUVLORMV VIN = 0 V to 5 V
3.2
3.9
4.6
V
—
VREG UVLO start voltage
VRUVLODET VIN = 5 V to 0 V
3.5
3.8
4.1
V
—
VREG UVLO recover voltage
VRUVLORMV VIN = 0 V to 5 V
3.9
4.2
4.5
V
—
PGOOD
PGOOD Threshold 1
(VFB ratio for UVD detect)
PGOOD Hysteresis 1
(VFB ratio for UVD release)
PGOOD Threshold 2
(VFB ratio for OVP detect)
PGOOD Hysteresis 2
(VFB ratio for OVP release)
PGOOD ON resistance
VTHPG1
VPGOOD : High to Low
77
85
93
%
—
VHYSPG1
VPGOOD : Low to High
3.5
5.0
6.5
%
—
VTHPG2
VPGOOD : High to Low
107
115
123
%
—
VHYSPG2
VPGOOD : Low to High
3.5
5.0
6.5
%
—
—
10
15
Ω
—
RPGOOD
—
Page 5 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
ELECTRICAL CHARACTERISTICS ( Continued )
Co = 22 µF x 5, Lo= 1 µH, VOUT Setting = 1.05 V, VIN = AVIN = PVIN = 12 V, VREG = 5 V,
Switching Frequency = 410 kHz, VMODE = VREG (FCCM), Ta = 25 C 2 C unless otherwise noted.
Parameter
Symbol
Condition
Limits
Min
Typ
Max
Unit
Note
DC-DC
Line regulation
DDREGIN
PVIN = 6 V to 20 V
IOUT = 4 A
—
0.25
0.75
%/V
—
Load regulation
DDREGLD
IOUT = 10 mA to 4 A
—
3.5
—
%
*1
DDEFF1
IOUT = 100 mA
VMODE=GND
(Skip mode)
Measure VIN Current.
—
81
—
%
*1
Efficiency 2
DDEFF2
IOUT = 4 A
VMODE=GND
(Skip mode)
Measure VIN Current.
—
84
—
%
*1
Output ripple voltage 1
DDVRPL1
IOUT = 100 mA
—
20
—
mV
[p-p]
*1
Output ripple voltage 2
DDVRPL2
IOUT = 4 A
—
20
—
mV
[p-p]
*1
Load transient response
DDDVAC
IOUT = 100 mA to 4 A
t = 0.5 A / µs
—
20
—
mV
*1
DV = PVIN – VOUT
—
2.5
—
V
*1
Efficiency 1
MIN Input and output voltage
difference
DV
*1 ： Typical design value.
Page 6 of 32
Established : 2012-12-18
Revised
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Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
ELECTRICAL CHARACTERISTICS ( Continued )
Co = 22 µF x 5, Lo= 1 µH, VOUT Setting = 1.05 V, VIN = AVIN = PVIN = 12 V, VREG = 5 V,
Switching Frequency = 410 kHz, VMODE = VREG (FCCM), Ta = 25 C 2 C unless otherwise noted.
Parameter
Symbol
Condition
DC-DC output current limit
DDILMT
—
DC-DC Output GND Short
Protection Threshold
DDSHPTH
Limits
Unit
Note
—
A
*1
60
70
%
—
—
2
4
µA
—
VEN = 0 V
—
5
10
kΩ
—
DDFSW1
IOUT = 4 A
—
220
—
kHz
*1
DC-DC Switching Frequency 2
DDFSW2
IOUT = 4 A
—
410
—
kHz
*1
DC-DC Switching Frequency 3
DDFSW3
IOUT = 4 A
—
580
—
kHz
*1
Min
Typ
Max
—
11
VFB = 0.6 V to 0.0 V
50
ISSCHG
VSS = 0.3 V
RSSDIS
DC-DC Switching Frequency 1
PROTECTION
Soft-Start Timing
SS Charge Current
SS Discharge Resistance (Shutdown)
Switching Frequency Adjustment
*1 ： Typical design value.
Page 7 of 32
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: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
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NN30421A
FSEL
EN
VREG
VFB
SS
Top View
VOUT
PIN CONFIGURATION
18 17 16 15 14 13
PGOOD 19
12 AVIN
25
AGND
AGND 20
11 AGND
BST 21
22
PVIN
23
10 MODE
27
LX
26
PVIN
24
9
8
PGND
7
2
3 4
5 6
LX
1
PIN FUNCTIONS
Pin No.
1
2
3
4
5
Pin name
Type
LX
Output
7
8
9
PGND
Ground
10
MODE
Input
AGND
Ground
Ground pin
12
AVIN
Power
supply
Power supply pin
Recommended rise time ( time to reach 90 % of set value ) setting is
greater than or equal to 10 µs and less than or equal to 1 s.
13
FSEL
Input
14
EN
Input
6
11
20
Description
Power MOSFET output pin
An inductor is connected and switching operation is carried out
between VIN and GND.
Due to high current and large amplitude at this terminal,
the parasitic inductance and impedance of the routing path
can cause an increase in noise and a degradation in the efficiency.
Routing path should be kept as short as possible.
Ground pin for Power MOSFET
Skip (discontinuous) mode / FCCM (Forced Continuous Conduction Mode )
select pin
Skip mode is set at Low level input, FCCM is set at High level input.
Frequency selection pin
This is set to 410 kHz at Low level input, 220 kHz at High level input,
and 580 kHz at open.
ON/OFF control pin
DC-DC is stopped at Low level input, and it is started at High level input.
Note : Detailed pin descriptions are provided in the OPERATION and APPLICATION INFORMATION section.
Page 8 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
PIN FUNCTIONS
Pin No.
Pin name
Type
15
VREG
Power supply
Description
Power supply pin
Recommended rise time ( time to reach 90 % of set value ) setting is
greater than or equal to 10 µs and less than or equal to 1 s.
Comparator negative input pin
VFB terminal voltage is regulated to REF output (internal reference voltage).
Since VFB is a high impedance terminal, it should not be routed near
other noisy path (LX, BST, etc.) or an inductor
Routing path should be kept as short as possible.
Output voltage sense pin
Switching frequency is controlled by monitoring output voltage.
Soft start capacitor connect pin
The output voltage at a start up is smoothly controlled
by adjusting Soft Start time.
Please connect capacitor between SS and GND.
Power good open drain pin
A pull up resistor between PGOOD and VREG terminal is necessary.
Output is low during Over or Under Voltage Detection conditions.
16
VFB
Input
17
VOUT
Input
18
SS
Output
19
PGOOD
Output
20
AGND
Ground
Ground pin
BST
Output
Supply input pin for high side MOSFET gate driver
Bootstrap operation is carried out in order to drive the gate voltage of High
side Power MOSFET. Please connect a capacitor between BST and LX.
Routing path should be kept as short as possible to minimize noise.
PVIN
Power supply
25
AGND
Ground
26
PVIN
27
LX
21
22
23
24
Power supply pin for Power MOSFET
Recommended rise time ( time to reach 90 % of set value ) setting is
greater than or equal to 10 µs and less than or equal to 1 s.
Ground pin for radiation of heat
Power supply Power supply pin for radiation of heat
Output
Power MOSFET output pin for radiation of heat
Note : Detailed pin descriptions are provided in the OPERATION and APPLICATION INFORMATION section.
Page 9 of 32
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: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
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NN30421A
FUNCTIONAL BLOCK DIAGRAM
AVIN
SS
18
EN
14
VREF
BGR
VINT
12
Soft-Start
SS
19
PGOOD
VREG
VREG
15
BS_SW
21
17
UVLO
OCP
SCP
TSD
22,23,24,26
BST
PVIN
0.6 V + 15 %
VOUT
Fault
0.6 V – 15 %
HPD
VFB
16
Soft-Start
Aux VREF
Timer
FSEL
HGATE
13
AVIN
REF
Ton
Timer + Comp
HGO
Toff
Timer + Comp
Control
Logic
ON
CMP
10
LX
LGATE
LPD
Coast
MODE
1,2,3,4,5,6,27
0.6 V
PGND
LGO
7,8,9
FCCM
/ Skip
11,20,25
AGND
Notes) This block diagram is for explaining functions. Part of the block diagram may be omitted, or it may be simplified.
Page 10 of 32
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Product Standards
NN30421A
OPERATION
1. Protection
(1) Over Current Protection (OCP) and
Short Circuit Protection (SCP)
(2) Over Voltage Detection (OVD)
1) The Over Current Protection is activated at about 11 A
If the VFB pin voltage exceeds 115 % of the set
(Typ.) This device uses pulse–by–pulse valley
voltage (0.6 V) and lasts more than 10 ns, Over
current protection method. When the low side
Voltage Detection will be triggered and PGOOD pin will
MOSFET is turned on, the voltage across the drain
be pulled down. Furthermore, in an over voltage
and source is monitored which is proportional to the
condition, high side power MOSFET is turned off to
inductor current. The high side MOSFET is only
stop PWM operation, and low side power MOSFET is
allowed to turn on when the current flowing in the low
turned on and held on until the inductor current starts to
side MOSFET falls below the OCP level.
flow back to the device (for both Skip mode and FCCM
Hence, during the OCP, the output voltage continues
settings). If the VFB pin voltage drops below 110 % of
to drop at the specified current. OCP is a non–latch
the set voltage within 30 µs after Over Voltage
type protection.
Detection triggers, PGOOD pin will be pulled up again
2) The Short-Circuit Protection function is implemented
and PWM operation will resume. Otherwise, both high
when the output voltage decreases and the VFB pin
side and low side MOSFET will be latched off and the
reaches to about 60 % of the set voltage (0.6 V).
output will be discharged by internal MOSFET.
If the VFB voltage stays below 60 % of the set
Power reset or EN pin reset is necessary to activate
voltage over 250 µs after SCP triggers, both
the device again.
high side and low side MOSFET will be latched
off and the output will be discharged by internal
MOSFET. Power reset or EN pin reset is necessary to
115 %
activate the device again.
110 % 0.6 V
0.6 V
VFB
90 %
85 %
Output Voltage [V]
Over Current Protection ( typ : 11 A )
8.25 A to 13.75 A
1)
2)
(Ground short
protection Detection
about 60% of Vout )
30us
(typ)
PGOOD
Note: PGOOD Pin is pulled up to VREG pin
Figure : OVD Operation
(3) Output discharging function
Output current [A]
Figure : OCP and SCP Operation
When EN is low, the output is discharged by an internal
MOSFET. When EN is high, if the controller is turned off
by under-voltage-lock-out (UVLO), or the controller is
latched off by over-voltage-protection (OVP) or shortcircuit protection (SCP), the output is discharged by the
above said internal MOSFET.
The on resistance of the internal MOSFET is about 50 Ω.
Page 11 of 32
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Product Standards
NN30421A
OPERATION (Continued)
1. Protection (Continued)
2. Pin Setting
(4) Under voltage detection (UVD)
(1).Operating Mode Setting
During the operation, if output voltage drops and
the VFB pin voltage reaches 85 % of its set
voltage ( 0.6 V ), the MOSFET, the drain of which is
connected to PGOOD pin, will turn on and pull the
voltage of PGOOD to be low.
If the output voltage continues to drop and VFB pin
voltage reaches 60 % of its set value ( 0.6 V ),
Short Circuit Protection (SCP) will be triggered.
If the output voltage returns to 90 % of its set
value ( 0.6 V ) before triggering Short Circuit
Protection, the MOSFET that is connected to PGOOD
pin will turn off after 1 ms and PGOOD voltage will
become logic high.
VFB
The IC can operate at two different modes :
Skip (discontinuous) mode and
Forced Continuous Conduction Mode (FCCM).
In Skip mode, the IC is working under pulse skipping
mechanism to improve efficiency at light load condition.
In FCCM, the IC is working at fixed frequency to
avoid EMI issues.
The Operating Mode can be set by MODE pin
as follows.
MODE pin
Mode
Low
Skip
High
FCCM
0.6 V
90 %
85 %
(2).Switching Frequency Setting
60 %
1 ms
PGOOD
The IC can operate at three different frequency :
580kHz, 410 kHz and 220 kHz.
The Switching Frequency can be set by FSEL pin
as follows.
Note: PGOOD Pin is pulled up to VREG pin
Figure : UVD Operation
(5) Thermal Shut Down (TSD)
FSEL pin
Frequency [kHz]
Low
410
High
220
Open
580
When the IC internal temperature becomes more
than about 140C, TSD operates and DC-DC turns off.
Page 12 of 32
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Revision. 2
Under
Development
Product Standards
NN30421A
OPERATION (Continued)
3.Output Voltage Setting
4. Soft Start Setting
The Output Voltage can be set by external resistance of
FB pin, and its calculation is as follows.
Soft Start function maintains the smooth control of the
output voltage during start up by adjusting soft start
time. When the EN pin becomes High, the current
( 2 µA ) begin to charge toward the external capacitor
(Css) of SS pin, and the voltage of SS pin increases
linearly.
Because the voltage of VFB pin is controlled by the
voltage of SS pin during start up, the voltage of VFB
increase linearly to the regulation voltage ( 0.6 V )
together with the voltage of SS pin and keep the
regulation voltage after that. On the other hand, the
voltage of SS pin increases to about 2.8 V and keep the
voltage. The calculation of Soft Start Time is as follows.
VOUT
VOUT = ( 1 +
RFB1
RFB2
) 0.6
RFB1
VFB ( 0.6 V )
RFB2
Below resistors are recommended for following typical
output voltages
VOUT [V]
RFB1 []
RFB2 []
3.3
4.5 k
1.0 k
1.8
2.0 k
1.0 k
1.2
1.5 k
1.5 k
1.05
750
1.0 k
Note: RFB2 can be set to a maximum value of 10 kΩ.
A larger RFB2 value will be more susceptible to noise.
VFB comparator threshold is adjusted to 1 %, but
the actual output voltage accuracy becomes more
than 1 % due to the influence from the circuits other
than VFB comparator.
Soft Start Time(sec)
0.6
Css
2
CSS : External capacitor value of SS pin
EN
VREG
UVLO
Soft Start Time (sec)
SS
0.6 V
VFB
VOUT
Figure : Soft Start Operation
Page 13 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
OPERATION (Continued)
5. Start-up / Shut-down Settings
The Start-up / Shut-down is enabled by the EN pin.
The EN pin can be set by either applying voltage from
an external voltage source or through a resistor
connected to the AVIN pin.
Case 1: Setting up the EN pin using an external
voltage source. When an external voltage
source is used, the EN pin input voltage
(VENH, VENL) should satisfy the conditions as
defined in the electrical characteristics
AVIN
VREG
AVIN
VREG
AVIN
REN1
EN
14
500
REN2 : 800 kΩ 50 %
Vd : 5.7 V 0.3 V
Id : more than 100 µA
5 V (Max.)
Figure : Internal circuit with EN pin
EN
14
0V
Figure : Internal circuit with EN pin
Case 2: Setting up the EN pin through a resistor
connected to AVIN pin. When setting up the
EN pin through a resistor connected to the
AVIN pin, refer to equations (1) and (2) to
calculate the optimal resistor settings.
[Equation]
(1) : REN1 >
AVIN – Vd
Id
(2) : REN1 <
(AVIN – VENH) REN2
VENH
[Example]
(1) : REN1 >
12 V – 6 V
100 µA
(2) : REN1 <
(12 V – 5 V) 400 kΩ
= 560 kΩ
5V
= 60 kΩ
Page 14 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
OPERATION (Continued)
6. Power ON / OFF sequence
(1) When the EN pin is set to High after the VIN
and VREG settle, the BGR starts up. (Recommended
VIN rise time setting and VREG rise time setting are
greater than or equal to 10 µs and less than or equal
to 1 s.)
(2) When the VREG pin exceeds its threshold value,
the UVLO is released and the SOFT START sequence
is enabled.
The capacitor connected to the SS pin begins to
charge and the SS pin voltage increases linearly.
(3) The VOUT pin (DC-DC Output) voltage increases at
the same rate as the SS pin.
Normal operation begins after the VOUT pin
reaches the set voltage.
(4) When the EN pin is set to Low, the BGR and UVLO
stop operation. The VOUT pin / SS pin Voltage starts
to drop and the VOUT pin discharge time depends on
the value of the Feedback resistors and the output load
current.
Note: The SS pin capacitor should be discharged
completely before restarting the startup
sequence.
An incomplete discharge process might result
in an overshoot of the output voltage.
greater than or equal to 10 µs and less than or equal to 1 s.
VIN
90%
EN
VREG
90%
greater than or equal to 10 µs and less than or equal to 1 s.
UVLO
Soft Start Time (s) =
SS
0.6
Css
2µ
0.6 V
VFB
VOUT
Delay Time (s) =
0.09
Css + 1 m
2µ
PGOOD
(1) (2) (3)
(4)
Figure : Power ON/OFF sequence
Page 15 of 32
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Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
OPERATION (Continued)
7. Inductor and Output Capacitor Setting
IL
Io
Highest efficiency operation is obtained at low
frequency with small ripple current. However,
achieving this requires a large inductor. There is a
trade off among component size, efficiency and
operating frequency. A reasonable starting point is to
choose a ripple current that is about 40 % of
IO (Max). The largest ripple current occurs at the
Highest Ei. To guarantee that ripple current does not
exceed a specified maximum, the inductance should be
chosen according to:
0
⊿IL/2
0
Ic
⊿IL/2
Lo
Vo
Eo
Vrpl
Ton
Eo Ei Eo
@ Ei Ei_max
2 Ei Iox f
And its maximum current rating is
IL_max Io_max
T=1/f
Vo(Eo)
Q1
IL
Ei
Lo
Q2
Ic
Io
Co
Rc
Given the desired input and output voltages,
the inductor value and operating frequency determine
the ripple current.
IL
Eo Ei Eo
Ei Lo f
Iox
IL
(@ Ei Ei_max)
2
The selection of CO is primarily determined by the
ESR (Rc) required to minimize voltage ripple and load
transients. The output ripple VRPL is approximately
bounded by:
Vrpl Vop Vob Ei
Ei
IL
Co Rc 2
2 Lo
8Co f
Co Rc 2
Eo Ei Eo
2 Lo
8Ei Lo Co f 2
From the above equation, to achieve desired output
ripple, low ESR ceramic capacitors are recommended,
and its required RMS current rating is:
Ic(rms)_max
IL
(@ Ei Ei_max)
2 3
IL
2
Page 16 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
TYPICAL CHARACTERISTICS CURVES
1. Output Ripple Voltage
Condition : VIN = 12 V, VREG=5V, VOUT Setting = 1.05 V, Switching Frequency = 410 kHz, Skip mode,
LO = 1 µH, CO = 110uF (22 µF x 5)
IOUT = 0A
IOUT = 1A
VOUT
VOUT
LX
LX
IOUT = 4A
IOUT = 8A
VOUT
VOUT
LX
LX
Page 17 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
TYPICAL CHARACTERISTICS CURVES ( Continued )
1. Output Ripple Voltage (Continued)
Condition : VIN = 12 V, VREG=5V, VOUT Setting = 1.05 V, Switching Frequency = 410 kHz, FCCM,
LO = 1 µH, CO = 110uF (22 µF x 5)
IOUT = 0A
IOUT = 1A
VOUT
VOUT
LX
LX
IOUT = 4A
IOUT = 8A
VOUT
VOUT
LX
LX
Page 18 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
TYPICAL CHARACTERISTICS CURVES ( Continued )
2. Load transient response
Condition : VIN = 12 V, VREG = 5V, VOUT Setting = 1.05 V, Switching Frequency = 410 kHz,
IOUT = 100 mA to 4 A (0.5 A / µs), LO = 1 µH, CO = 110uF (22 µF x 5)
Skip mode
FCCM
38.61mV
VOUT (50 mV/div)
36.25mV
23.5mV
VOUT (50 mV/div)
21.03mV
IOUT (2 A/div)
IOUT (2 A/div)
Time (100 us/div)
Time (100 us/div)
Condition : VIN = 12 V, VREG = 5V, VOUT = 1.05 V, Switching Frequency = 410 kHz,
IOUT = 2 A to 6 A (0.15 A / µs), LO = 1 µH, CO = 110uF (22 µF x 5)
Skip mode
FCCM
14.69mV
VOUT (50 mV/div)
14.69mV
VOUT (50 mV/div)
13.54mV
13.78mV
IOUT (2 A/div)
Time (100 us/div)
IOUT (2 A/div)
Time (100 us/div)
Page 19 of 32
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: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
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Development
Product Standards
NN30421A
TYPICAL CHARACTERISTICS CURVES ( Continued )
3. Efficiency
Condition : VIN = 12 V, VREG = 5V, VOUT Setting = 1.05 V / 1.2 V / 1.8 V / 3.3 V,
Switching Frequency = 220 kHz, LO = 3.3 µH, CO = 110 µF (22 µF x 5)
Frequency y= 220kHz
100
90
80
Efficiency (%)
70
60
FCCM/ Vo= 1.05V
FCCM/ Vo= 1.2V
FCCM/ Vo= 1.8V
FCCM/ Vo= 3.3V
SKIP/ Vo= 1.05V
SKIP/ Vo= 1.2V
SKIP/ Vo= 1.8V
SKIP/ Vo= 3.3V
50
40
30
20
10
10.000
1.000
0.100
0.010
0.001
0
IOUT (A)
Condition : VIN = 12 V, VREG = 5V, VOUT Setting = 1.05 V / 1.2 V / 1.8 V / 3.3 V,
Switching Frequency = 410 kHz, LO = 1 µH, CO = 110 µF (22 µF x 5)
Frequency = 410kHz
100
90
80
70
Efficiency (%)
60
50
FCCM/ Vo= 1.05V
FCCM/ Vo= 1.2V
FCCM/ Vo= 1.8V
FCCM/ Vo= 3.3V
SKIP/ Vo= 1.05V
SKIP/ Vo= 1.2V
SKIP/ Vo= 1.8V
SKIP/ Vo= 3.3V
40
30
20
10
10.000
1.000
0.100
0.010
0.001
0
IOUT (A)
Page 20 of 32
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: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
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Development
Product Standards
NN30421A
TYPICAL CHARACTERISTICS CURVES ( Continued )
4. Load Regulation
Condition : VIN = 12 V, VREG = 5V, VOUT Setting = 1.05 V, Switching Frequency = 220 kHz,
LO = 3.3 µH, CO = 110uF (22 µF x 5)
Skip mode
1.13
1.13
1.11
1.11
1.09
1.09
1.05
1.03
1.01
1.01
0.99
0.99
0.97
0.97
8
9
9
7
7
8
6
6
5
0
IOUT (A)
4
0.95
9
8
7
6
5
4
3
2
1
0.95
3
1.03
1.07
2
1.05
1
1.07
0
FCCM
1.15
VOUT (V)
VOUT (V)
1.15
IOUT (A)
Condition : VIN = 12 V, VREG = 5V, VOUT Setting = 1.05 V, Switching Frequency = 410 kHz,
LO = 1 µH, CO = 110 µF (22 µF x 5)
FCCM
1.15
1.13
1.13
1.11
1.11
1.09
1.09
1.07
1.07
VOUT (V)
1.05
1.03
1.01
1.05
1.03
1.01
0.99
0.99
0.97
0.97
5
4
3
2
9
8
7
0.95
1
IOUT (A)
6
5
4
3
2
1
0
0.95
0
VOUT (V)
Skip mode
1.15
IOUT (A)
Page 21 of 32
Established : 2012-12-18
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: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
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Development
Product Standards
NN30421A
TYPICAL CHARACTERISTICS CURVES ( Continued )
5. Line Regulation
Condition : VOUT Setting = 1.05 V, Switching Frequency = 410 kHz, IOUT = 1.5 A,
LO = 1 µH, CO = 110 µF (22 µF x 5)
Line Regulation_f = 410kHz (FCCM mode)
1.15
1.15
1.13
1.13
1.11
1.11
1.09
1.09
1.07
VOUT (V)
1.05
1.03
1.01
1.07
1.05
1.03
1.01
0.99
0.99
0.97
0.97
VIN (V)
24
18
12
0.95
6
24
18
12
6
0
0.95
0
VOUT (V)
Line Regulation_f = 410kHz (skip mode)
VIN (V)
Page 22 of 32
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: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
TYPICAL CHARACTERISTICS CURVES ( Continued )
6. Start / Shut Down
Condition : VIN = 12 V, VREG = 5V, VOUT Setting = 1.05 V, Switching Frequency = 410 kHz, Skip mode, IOUT = 0 A,
LO = 1 µH, CO = 110 µF (22 µF x 5)
EN (2 V/div)
EN (2 V/div)
SS (2 V/div)
SS (2 V/div)
VOUT (0.5 V/div)
VOUT (0.5 V/div)
Time (10 ms/div)
Time (10 ms/div)
Condition : VIN = 12 V, VREG = 5V, VOUT Setting = 1.05 V, Switching Frequency = 410 kHz, FCCM, IOUT = 0 A,
LO = 1 µH, CO = 110 µF (22 µF x 5)
EN (2 V/div)
EN (2 V/div)
SS (2 V/div)
SS (2 V/div)
VOUT (0.5 V/div)
VOUT (0.5 V/div)
Time (10 ms/div)
Time (10 ms/div)
Page 23 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
TYPICAL CHARACTERISTICS CURVES ( Continued )
6. Start / Shut Down (Continued)
Condition : VIN = 12 V, VREG = 5V, VOUT Setting = 1.05 V, Switching Frequency = 410 kHz, Skip mode, RLOAD = 0.5 ,
LO = 1 µH, CO = 44 µF (22 µF x 2)
EN (2 V/div)
EN (2 V/div)
SS (2 V/div)
SS (2 V/div)
VOUT (0.5 V/div)
VOUT (0.5 V/div)
Time (10 ms/div)
Time (10 ms/div)
Condition : VIN = 12 V, VREG = 5V, VOUT Setting = 1.05 V, Switching Frequency = 410 kHz, FCCM, RLOAD = 0.5 ,
LO = 1 µH, CO = 110 µF (22 µF x 5)
EN (2 V/div)
EN (2 V/div)
SS (2 V/div)
SS (2 V/div)
VOUT (0.5 V/div)
VOUT (0.5 V/div)
Time (10 ms/div)
Time (10 ms/div)
Page 24 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
TYPICAL CHARACTERISTICS CURVES ( Continued )
7. Short Circuit Protection
Condition : VIN = 12 V, VREG = 5V, VOUT Setting = 1.05 V, Switching Frequency = 410 kHz,
LO = 1 µH, CO = 110 µF (22 µF x 5)
Skip mode
FCCM
LX (10 V/div)
LX (10 V/div)
SS (2 V/div)
SS (2 V/div)
VOUT (1 V/div)
VOUT (1 V/div)
IOUT (10 A/div)
IOUT (10 A/div)
Time (10 ms/div)
Time (10 ms/div)
Page 25 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
TYPICAL CHARACTERISTICS CURVES ( Continued )
8. Switching Frequency
Condition : VIN = 12 V, VREG = 5V, VOUT Setting = 1.05 V, Switching Frequency = 410 kHz, IOUT = 10 mA to 8 A,
LO = 1 µH, CO = 110 µF (22 µF x 5)
LX Average Frequency (MHz) FCCM Mode
0.50
0.45
0.45
LX Average Frequency (MHz)
LX Average Frequency (MHz)
LX Average Frequency (MHz) Skip Mode
0.50
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.01
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.1
1
10
0.01
ILOAD (A)
0.1
1
10
ILOAD (A)
Condition : VOUT Setting = 1.05 V, Switching Frequency = 410 kHz, IOUT = 4 A, LO = 1 µH, CO = 110 µF (22 µF x 5)
LX Average Frequency (MHz) FCCM Mode
0.50
0.50
0.45
0.45
LX Average Frequency (MHz)
LX Average Frequency (MHz)
LX Average Frequency (MHz) Skip Mode
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
4
6
8
10
12
14
VIN(V)
16
18
20
22
24
4
6
8
10
12
14
16
18
20
22
24
VIN(V)
Page 26 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
TYPICAL CHARACTERISTICS CURVES ( Continued )
9. Thermal Performance
Condition : VIN = 12 V, VREG = 5V, VOUT Setting = 1.05 V, Switching Frequency = 410 kHz, Skip mode, IOUT = 8 A,
LO = 1 µH, CO = 110 µF (22 µF x 5)
Page 27 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
APPLICATIONS INFORMATION
1. Evaluation Board Information
Condition : VOUT Setting = 1.05 V, Switching Frequency = 410 kHz, Skip mode
PGOOD
SS
C-BST
C-SS
21
22
23
24
18
PVIN
SS
VOUT
R-FB2 R-FB1
2
17
VOUT
12
C-AVIN1
C-AVIN2
C-PVIN5
C-PVIN6
VOUT
L-LX
Application circuit
Figure : Top Layer with silk screen
( Top View ) with Evaluation board
SS
VOUT
L-LX
LX
R-FBX
VFB
R-FBX
C-VREG
C-DCDCOUT1
C-DCDCOUT2
C-DCDCOUT3
C-AVIN2
C-AVIN1
DCDCOUT
C-DCDCOUT1
C-DCDCOUT2
11
FSEL
AVIN
10
AGND
9
MODE
8
EN
R-FB4 R-FB3
6
7
VREG
C-VREG
15
5
13
4
14
3
16
VFB
C-FB
AGND
20
1
LX
BST
PVIN
R-PG
VREG
19
C-BST
C-PVIN5
C-PVIN6
PVIN
VREG
AVIN
PGND
Layout
Figure : Bottom Layer with silk screen
( Bottom View ) with Evaluation board
Notes: The application circuit diagram and layout diagram explained in this section, should be used as reference examples. The
operation of the mass production set is not guaranteed. Sufficient evaluation and verification is required in the design of the
mass production set. The Customer is fully responsible for the incorporation of the above illustrated application circuit and the
information attached with it, in the design of the equipment.
Page 28 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
APPLICATIONS INFORMATION (Continued)
2. Layout Recommendations
Board layout considerations are necessary for stable
operation of the DC-DC regulator. The following
precautions must be used when designing the board
layout.
(a) The Input capacitor CIN must be placed in such a way
that the distance between PVIN and PGND is
minimum, in order to suppress the switching noise.
Stray inductance and impedance should be reduced
as indicated by loop (1) in the figure below.
(b) A single point ground connection (2) must be used to
connect PGND and AGND to improve operation
stability.
(c) Output current line IOUT and the output sense line
VOUT must have small common impedance to
reduce output load variations. Output sense line
VOUT must be close to the output condenser CO as
indicated by (3) below.
(d) Power Loss and output ripple voltage can be reduced
by placing the inductor LO and output capacitor CO
such that the stray inductance and the impedance of
loop (4) is minimum. This is realized by :
i) Minimizing distance between inductor LO and LX
pin.
ii) Reducing distance between output capacitor CO
and (2) / (3)
(e) Thick lines in the application circuit example
represent lines with large current flow. These lines
should be designed as thick as possible.
(f) VFB / SS lines should be placed far away
from LX line, BST line and inductor LO to reduce the
effects of switching noise. These lines should be
designed as short as possible. This is especially true
for the VFB line, which is a high impedance line.
(g) RFB1 / RFB2 should also be placed as far away as
possible from LX line, BST line and inductor LO to
minimize the effects of switching noise. RFB1 / RFB2
should be placed close to the VFB pin.
(h) LX / BST lines are noisy lines. They should be
designed as short as possible.
AVIN
(1)
PVIN
VOUT
(3)
BST
RFB1
LO
VFB
IOUT
LX
RFB2
SS
AGND PGND
CIN
CO
(4)
(2)
Figure : Application circuit diagram
Note : The application circuit diagram and layout diagram
explained in this section, should be used as reference
examples. The operation of the mass production set is
not guaranteed. Sufficient evaluation and verification is
required in the design of the mass production set. The
Customer is fully responsible for the incorporation of
the above illustrated application circuit and the
information attached with it, in the design of the
equipment.
Page 29 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
APPLICATIONS INFORMATION (Continued)
3. Recommended component
Reference Designator
QTY
Value
Manufacturer
Part Number
Note
C-AVIN1
1
4.7 µF
Murata
GRM31CB31H475KA12L
—
C-AVIN2
1
0.1 µF
Murata
GRM188R72A104KA35L
Optional
C-BST
1
0.1 µF
Murata
GRM188R72A104KA35L
—
C-DCDCOUT
5
22 µF
Murata
GRM32ER71E226KE15L
—
C-PVIN5
2
10 µF
TAIYO
YUDEN
UMK325AB7106MM-T
—
C-PVIN6
1
0.1 µF
Murata
GRM188R72A104KA35L
—
C-SS
1
10 nF
Murata
GRM188R72A103KA01L
—
C-VREG
1
1.0 µF
Murata
GRM188R71E105KA12L
—
1.0 µH
Panasonic
ETQP3W1R0WFN
FSEL
GND ( 410 kHz )
OPEN ( 580 kHz )
3.3 µH
Panasonic
ETQP3W3R3WFN
FSEL
VREG ( 220 kHz )
L-LX
1
C-FB
1
12 nF
YAGEO
(PHYCOMP)
CC0603KRX7R9BB123
—
R-FB1
1
750
Panasonic
ERJ3GEYJ561Y
—
R-FB2
1
0
Panasonic
ERJ3GEY0R00V
—
R-RB3
1
0
Panasonic
ERJ3GEYJ510V
—
R-FB4
1
1 kΩ
Panasonic
ERJ3GEYJ681V
—
R-PG
1
100
kΩ
Panasonic
ERJ3EKF1003V
—
Special attention and precaution in using
VIN (V)
This IC is intended to be used for general electronic
equipment. Ensure that the IC is used within the
recommended safe operating region illustrated by the
reference graph below. Do take note that thermal
performance may varies with PCB design and PCB
materials. You are encourage to use the graph only as
a reference for your design and discuss further with our
application engineer.
It is to be understood that our company shall not be
held responsible for any damage incurred as a result of
application beyond the recommended safe operating
region.
VIN (V) V.S. ILOAD (A)
PKG Surface Temperature=80deg, Fsw=410kHz
28
26
24
22
20
18
16
14
12
10
8
6
4
VOUT=3.3V
VOUT=1.05V
VOUT=1.8V
7
7.5
8
8.5
9
9.5
10
ILOAD (A)
Page 30 of 32
Established : 2012-12-18
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: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
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Development
Product Standards
NN30421A
PACKAGE INFORMATION
Outline Drawing
Unit : mm
Package Code: HQFN024-A3-0404BZF
Body Material : Br/Sb Free Epoxy Resin
Lead Material : Cu Alloy
Lead Finish Method : Pd Plating
Page 31 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Doc No. TA4-EA-06152
Revision. 2
Under
Development
Product Standards
NN30421A
IMPORTANT NOTICE
1. When using the IC for new models, verify the safety including the long-term reliability for each product.
2. When the application system is designed by using this IC, please confirm the notes in this book.
Please read the notes to descriptions and the usage notes in the book.
3. This IC is intended to be used for general electronic equipment.
Consult our sales staff in advance for information on the following applications: Special applications in which exceptional
quality and reliability are required, or if the failure or malfunction of this IC may directly jeopardize life or harm the human body.
Any applications other than the standard applications intended.
(1) Space appliance (such as artificial satellite, and rocket)
(2) Traffic control equipment (such as for automotive, airplane, train, and ship)
(3) Medical equipment for life support
(4) Submarine transponder
(5) Control equipment for power plant
(6) Disaster prevention and security device
(7) Weapon
(8) Others : Applications of which reliability equivalent to (1) to (7) is required
Our company shall not be held responsible for any damage incurred as a result of or in connection with the IC being used for
any special application, unless our company agrees to the use of such special application.
However, for the IC which we designate as products for automotive use, it is possible to be used for automotive.
4. This IC is neither designed nor intended for use in automotive applications or environments unless the IC is designated by our
company to be used in automotive applications.
Our company shall not be held responsible for any damage incurred by customers or any third party as a result of or in
connection with the IC being used in automotive application, unless our company agrees to such application in this book.
5. Please use this IC in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled
substances, including without limitation, the EU RoHS Directive. Our company shall not be held responsible for any damage
incurred as a result of our IC being used by our customers, not complying with the applicable laws and regulations.
6. Pay attention to the direction of the IC. When mounting it in the wrong direction onto the PCB (printed-circuit-board),
it might be damaged.
7. Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins.
In addition, refer to the Pin Description for the pin configuration.
8. Perform visual inspection on the PCB before applying power, otherwise damage might happen due to problems such as
solder-bridge between the pins of the IC. Also, perform full technical verification on the assembly quality, because the same
damage possibly can happen due to conductive substances, such as solder ball, that adhere to the IC during transportation.
9. Take notice in the use of this IC that it might be damaged when an abnormal state occurs such as output pin-VCC short
(Power supply fault), output pin-GND short (Ground fault), or output-to-output-pin short (load short). Safety measures such as
installation of fuses are recommended because the extent of the above-mentioned damage will depend on the current
capability of the power supply.
10. The protection circuit is for maintaining safety against abnormal operation. Therefore, the protection circuit should not work
during normal operation.
Especially for the thermal protection circuit, if the area of safe operation or the absolute maximum rating is momentarily
exceeded due to output pin to VCC short (Power supply fault), or output pin to GND short (Ground fault), the IC might be
damaged before the thermal protection circuit could operate.
11. Unless specified in the product specifications, make sure that negative voltage or excessive voltage are not applied to the
pins because the IC might be damaged, which could happen due to negative voltage or excessive voltage generated during
the ON and OFF timing when the inductive load of a motor coil or actuator coils of optical pick-up is being driven.
12. Product which has specified ASO (Area of Safe Operation) should be operated in ASO
13. Verify the risks which might be caused by the malfunctions of external components.
14. Connect the metallic plates (fins) on the back side of the LSI with their respective potentials (AGND, PVIN, LX).
The thermal resistance and the electrical characteristics are guaranteed only when the metallic plates (fins) are
connected with their respective potentials.
Page 32 of 32
Established : 2012-12-18
Revised
: 2013-06-20
Request for your special attention and precautions in using the technical information and
semiconductors described in this book
(1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and
regulations of the exporting country, especially, those with regard to security export control, must be observed.
(2) The technical information described in this book is intended only to show the main characteristics and application circuit examples
of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any
other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any
other company which may arise as a result of the use of technical information described in this book.
(3) The products described in this book are intended to be used for general applications (such as office equipment, communications
equipment, measuring instruments and household appliances), or for specific applications as expressly stated in this book.
Consult our sales staff in advance for information on the following applications:
– Special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling equipment, combustion equipment,
life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of
the products may directly jeopardize life or harm the human body.
It is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with
your using the products described in this book for any special application, unless our company agrees to your using the products in
this book for any special application.
(4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product
Standards in advance to make sure that the latest specifications satisfy your requirements.
(5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions
(operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute
maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any
defect which may arise later in your equipment.
Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure
mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire
or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products.
(6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS,
thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which
damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages.
(7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company.
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