784216A

www.DataSheet4U.com DATA SHEET MOS INTEGRATED CIRCUIT µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 16-BIT SINGLE-CHIP MICROCONTROLLERS DESCRIPTION The µPD784214A, 784215A, 784216A, 784217A, and 784218A are products of the µPD784216A/784218A Subseries in the 78K/IV Series. Besides a high-speed and high performance CPU, these controllers have ROM, RAM, I/O ports, 8-bit resolution A/D and D/A converters, timers, serial interfaces, a real-time output port, interrupt functions, and various other peripheral hardware. The µPD784214AY, 784215AY, 784216AY, 784217AY, and 784218AY are based on the µPD784216Y/784218Y Subseries with the addition of a multimaster-supporting I2C bus interface. The µPD78F4218A and 78F4218AY, products with a flash memory instead of the internal ROM of mask ROM versions, and various development tools are also available. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. µPD784216A, 784216AY Subseries User’s Manual Hardware: U13570E µPD784218A, 784218AY Subseries User’s Manual Hardware: U12970E 78K/IV Series User’s Manual Instructions: U10905E FEATURES • 78K/IV Series • Inherits peripheral functions of µPD78078, 78078Y Subseries • Minimum instruction execution time 160 ns (@fXX = 12.5 MHz operation with main system clock) 61 µs (@fXT = 32.768 kHz operation with subsystem clock) • I/O port: 86 pins • Timer/event counter: • 16-bit timer/event counter × 1 unit • 8-bit timer/event counter × 6 units • Serial interface: 3 channels • UART/IOE (3-wire serial I/O): 2 channels • CSI (3-wire serial I/O, I2C bus supporting multimaster Note): 2 channels Note µPD784216AY/784218AY Subseries only • Supply voltage: VDD = 1.8 to 5.5 V • Standby function HALT/STOP/IDLE mode In low-power consumption mode: HALT/IDLE mode (with subsystem clock) • Clock division function • Watch timer: 1 channel • Watchdog timer: 1 channel • Clock output function Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT • Buzzer output function 10 11 12 13 Selectable from fXX/2 , fXX/2 , fXX/2 , fXX/2 • A/D converter: 8-bit resolution × 8 channels • D/A converter: 8-bit resolution × 2 channels APPLICATIONS Cellular phones, PHS, cordless telephones, CD-ROM, AV equipment Unless otherwise specified, references in this document to the µPD784218A, 784218AY refer to the µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, and 784218AY. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14121EJ2V0DS00 (2nd edition) Date Published August 2000 N CP(K) Printed in Japan The mark shows major revised points. 2000 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY ORDERING INFORMATION Part Number Package 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic QFP (14 × 20 mm) 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic QFP (14 × 20 mm) 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic QFP (14 × 20 mm) 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic QFP (14 × 20 mm) 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic QFP (14 × 20 mm) 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic QFP (14 × 20 mm) 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic QFP (14 × 20 mm) 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic QFP (14 × 20 mm) 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic QFP (14 × 20 mm) 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic QFP (14 × 20 mm) Internal ROM (Bytes) 96 K 96 K 128 K 128 K 128 K 128 K 192 K 192 K 256 K 256 K 96 K 96 K 128 K 128 K 128 K 128 K 192 K 192 K 256 K 256 K Internal RAM (Bytes) 3,584 3,584 5,120 5,120 8,192 8,192 12,800 12,800 12,800 12,800 3,584 3,584 5,120 5,120 8,192 8,192 12,800 12,800 12,800 12,800 µPD784214AGC-×××-8EU µPD784214AGF-×××-3BA µPD784215AGC-×××-8EU µPD784215AGF-×××-3BA µPD784216AGC-×××-8EU µPD784216AGF-×××-3BA µPD784217AGC-×××-8EU µPD784217AGF-×××-3BA µPD784218AGC-×××-8EU µPD784218AGF-×××-3BA µPD784214AYGC-×××-8EU µPD784214AYGF-×××-3BA µPD784215AYGC-×××-8EU µPD784215AYGF-×××-3BA µPD784216AYGC-×××-8EU µPD784216AYGF-×××-3BA µPD784217AYGC-×××-8EU µPD784217AYGF-×××-3BA µPD784218AYGC-×××-8EU µPD784218AYGF-×××-3BA Remark ××× indicates ROM code suffix. 2 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 78K/IV SERIES LINEUP : Products in mass-production : Products under development Supports I2C bus Supports multimaster I2C bus µ PD784038Y µ PD784038 µ PD784225Y µ PD784225 80-pin, ROM correction added Supports multimaster I2C bus Standard models µ PD784026 Enhanced A/D converter, 16-bit timer, and power management Enhanced internal memory capacity Pin-compatible with the µ PD784026 Supports multimaster I2C bus µPD784216AY µ PD784216A 100-pin, enhanced I/O and internal memory capacity µPD784218AY µ PD784218A Enhanced internal memory capacity, ROM correction added µ PD784054 µPD784046 ASSP models µ PD784956A For DC inverter control On-chip 10-bit A/D converter µ PD784967 Enhanced functions of the µ PD784938A, enhanced I/O and internal memory capacity. µ PD784938A Enhanced functions of the µ PD784908, enhanced internal memory capacity, ROM correction added. Supports multimaster I2C bus µ PD784908 On-chip IEBusTM controller µ PD784928Y µPD784915 Software servo control On-chip analog circuit for VCRs Enhanced timer µ PD784928 Enhanced functions of the µ PD784915 µ PD784976A On-chip VFD controller/driver Data Sheet U14121EJ2V0DS00 3 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY OVERVIEW OF FUNCTIONS (1/2) Part Number Item Number of basic instructions (mnemonics) General-purpose registers Minimum instruction execution time µPD784214A, µPD784214AY µPD784215A, µPD784215AY µPD784216A, µPD784216AY µPD784217A, µPD784217AY µPD784218A, µPD784218AY 113 8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping) • 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (@fXX = 12.5 MHz operation with main system clock) • 61 µs (@fXT = 32.768 kHz operation with subsystem clock) 96 KB 3,584 bytes 128 KB 5,120 bytes 8,192 bytes 192 KB 12,800 bytes 256 KB Internal memory Memory space I/O ports ROM RAM 1 MB with program and data spaces combined Total CMOS input CMOS I/O N-ch open-drain I/O 86 8 72 6 70 22 6 4 bits × 2 or 8 bits × 1 Timer/event counter: (16-bit) Timer counter × 1 Pulse output Capture/compare register × 2 • PPG output • Square wave output • One-shot pulse output Pulse output • PWM output • Square wave output Pulse output • PWM output • Square wave output Pulse output • PWM output • Square wave output Pulse output • PWM output • Square wave output Pulse output • PWM output • Square wave output Pulse output • PWM output • Square wave output Pins with additional functionsNote 1 Pins with pull-up resistor LED direct drive output Middle-voltage pin Real-time output port Timer/event counter Timer/event counter 1: Timer counter × 1 (8-bit) Compare register × 1 Timer/event counter 2: Timer counter × 1 (8-bit) Compare register × 1 Timer/event counter 5: Timer counter × 1 (8-bit) Compare register × 1 Timer/event counter 6: Timer counter × 1 (8-bit) Compare register × 1 Timer/event counter 7: Timer counter × 1 (8-bit) Compare register × 1 Timer/event counter 8: Timer counter × 1 (8-bit) Compare register × 1 Serial interface A/D converter D/A converter • UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator) • CSI (3-wire serial I/O, multimaster supporting I2C busNote 2): 1 channel 8-bit resolution × 8 channels 8-bit resolution × 2 channels Notes 1. Pins with additional functions are included with the I/O pins. 2. µPD784216AY/784218AY Subseries only 4 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY OVERVIEW OF FUNCTIONS (2/2) Part Number Item Clock output Buzzer output Watch timer Watchdog timer Standby Interrupt Hardware sources Software sources Non-maskable Maskable µPD784214A, µPD784214AY µPD784215A, µPD784215AY 2 µPD784216A, µPD784216AY 3 4 µPD784217A, µPD784217AY 5 6 7 µPD784218A, µPD784218AY Selectable from fXX, fXX/2, fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXT Selectable from fXX/2 , fXX/2 , fXX/2 , fXX/2 1 channel 1 channel • HALT/STOP/IDLE modes • In low power consumption mode (with subsystem clock): HALT/IDLE modes 29 (internal: 20, external: 9) BRK instruction, BRKCS instruction, operand error Internal: 1, external: 1 Internal: 19, external: 8 • 4 programmable priority levels • 3 service modes: Vectored interrupt/macro service/context switching 10 11 12 13 Supply voltage Package VDD = 1.8 to 5.5 V 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic QFP (14 × 20 mm) Data Sheet U14121EJ2V0DS00 5 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY CONTENTS 1. DIFFERENCES AMONG MODELS IN µPD784216A, 784216AY/784218A, 784218AY SUBSERIES....... 8 2. MAJOR DIFFERENCES FROM µPD78078Y SUBSERIES ................................................................ 9 3. PIN CONFIGURATION (TOP VIEW).................................................................................................. 10 4. BLOCK DIAGRAM ............................................................................................................................... 13 5. PIN 5.1 5.2 5.3 FUNCTIONS .................................................................................................................................. 14 Port Pins ...................................................................................................................................... 14 Non-Port Pins .............................................................................................................................. 16 Pin I/O Circuits and Recommended Connections of Unused Pins ........................................ 18 6. CPU ARCHITECTURE ......................................................................................................................... 22 6.1 Memory Space ............................................................................................................................. 22 6.2 CPU Registers.............................................................................................................................. 29 6.2.1 General-purpose registers ..............................................................................................................29 6.2.2 Control registers..............................................................................................................................30 6.2.3 Special function registers (SFRs)....................................................................................................31 7. PERIPHERAL HARDWARE FUNCTIONS.......................................................................................... 36 7.1 Ports ............................................................................................................................................. 36 7.2 Clock Generator........................................................................................................................... 37 7.3 Real-Time Output Port ................................................................................................................ 39 7.4 Timer/Event Counter ................................................................................................................... 40 7.5 A/D Converter .............................................................................................................................. 42 7.6 D/A Converter .............................................................................................................................. 43 7.7 Serial Interface............................................................................................................................. 44 7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) ..........................................................45 7.7.2 Clocked serial interface (CSI) .........................................................................................................47 7.8 Clock Output Function................................................................................................................ 49 7.9 Buzzer Output Function.............................................................................................................. 49 7.10 Edge Detection Function .......................................................................................................... 50 7.11 Watch Timer ............................................................................................................................... 50 7.12 Watchdog Timer ........................................................................................................................ 51 8. INTERRUPT FUNCTIONS.................................................................................................................... 52 8.1 Interrupt Sources......................................................................................................................... 52 8.2 Vectored Interrupt ....................................................................................................................... 54 8.3 Context Switching ....................................................................................................................... 55 8.4 Macro Service .............................................................................................................................. 56 8.5 Application Example of Macro Service ..................................................................................... 57 6 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 9. LOCAL BUS INTERFACE................................................................................................................. 58 9.1 Memory Expansion ..................................................................................................................... 59 9.2 Programmable Wait .................................................................................................................... 59 10. STANDBY FUNCTION ....................................................................................................................... 60 11. RESET FUNCTION ............................................................................................................................ 62 12. INSTRUCTION SET ........................................................................................................................... 63 13. ELECTRICAL SPECIFICATIONS ...................................................................................................... 68 14. PACKAGE DRAWINGS ..................................................................................................................... 88 15. RECOMMENDED SOLDERING CONDITIONS................................................................................ 90 APPENDIX A. DEVELOPMENT TOOLS ................................................................................................ 92 APPENDIX B. RELATED DOCUMENTS................................................................................................ 95 Data Sheet U14121EJ2V0DS00 7 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 1. DIFFERENCES AMONG MODELS IN µPD784216A, 784216AY/784218A, 784218AY SUBSERIES The only difference among the µPD784214A, 784215A, 784216A, 784217A, and 784218A lies in the internal memory capacity. The µPD784214AY, 784215AY, 784216AY, 784217AY, and 784218AY are models with the addition of an I2C bus control function. The µPD78F4216A, 78F4216AY, 78F4218A, and 78F4218AY are provided with a 128 KB/256 KB flash memory instead of the mask ROM of the above models. These differences are summarized in Table 1-1. Table 1-1. Differences Among Models in µPD784216A, 784216AY/784218A, 784218AY Subseries Part Number Item Internal ROM µPD784214A, µPD784214AY µPD784215A, µPD784215AY µPD784216A, µPD784216AY µPD784217A, µPD784217AY µPD784218A, µPD784218AY µPD78F4216A, µPD78F4216AY µPD78F4218A, µPD78F4218AY 96 KB (Mask ROM) 3,584 bytes 128 KB (Mask ROM) 192 KB (Mask ROM) 12,800 bytes 256 KB (Mask ROM) 128 KB (Flash memory) 5,120 bytes ProvidedNote 256 KB (Flash memory) 12,800 bytes Internal RAM 5,120 bytes 8,192 bytes Internal memory size switching register (IMS) ROM correction Not provided Not provided Provided Not provided Not provided Provided External access status function Supply voltage Electrical specifications Recommended soldering conditions EXA pin Not provided Provided Provided VDD = 1.8 to 5.5 V Refer to the data sheet for each device. VDD = 1.9 to 5.5 V Not provided Provided Not provided Not provided Provided Provided TEST pin VPP pin Provided Not provided Note The internal flash memory capacity and internal RAM capacity can be changed using the internal memory size switching register (IMS). Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (not engineering samples) of the mask ROM version. 8 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 2. MAJOR DIFFERENCES FROM µPD78078Y SUBSERIES Series Name Item CPU Minimum instruction execution time With main system clock With subsystem clock Memory space I/O ports Total CMOS input CMOS I/O N-ch open-drain I/O Pins with additional functionsNote 1 Pins with pull-up resistor LED direct drive output Middle-voltage pin Timer/counter µPD784216A, 784216AY/784218A, 784218AY Subseries 16-bit CPU 160 ns (@12.5 MHz operation) 61 µs (@32.768 kHz operation) 1 MB 86 8 72 6 70 µPD78078Y Subseries 8-bit CPU 400 ns (@5.0 MHz operation) 122 µs (@32.768 kHz operation) 64 KB 88 2 78 8 86 22 16 6 • 16-bit timer/event counter × 1 unit • 8-bit timer/event counter × 6 units • UART/IOE (3-wire serial I/O) × 2 channels • CSI (3-wire serial I/O, multimaster 2 supporting I C busNote 2) × 1 channel 8 • 16-bit timer/event counter × 1 unit • 8-bit timer/event counter × 4 units • UART/IOE (3-wire serial I/O) × 1 channel • CSI (3-wire serial I/O, 2-wire serial 2 I/O, I C bus) × 1 channel • CSI (3-wire serial I/O, 3-wire serial I/O with automatic transmit/receive function) × 1 channel Not provided Not provided Not provided Not provided HALT/STOP modes Serial interface Interrupts NMI pin Macro service Context switching Programmable priority Provided Provided Provided 4 levels • HALT/STOP/IDLE modes • In low power consumption mode: HALT/IDLE modes • 100-pin plastic LQFP (fine pitch) (14 × 14 mm) • 100-pin plastic QFP (14 × 20 mm) Standby function Package • 100-pin plastic LQFP (fine pitch) (14 × 14 mm) • 100-pin plastic QFP (14 × 20 mm) • 100-pin ceramic WQFN (14 × 20 mm) (µPD78P078Y only) Notes 1. Pins with additional functions are included with the I/O pins. 2. µPD784216AY/784218AY Subseries only Data Sheet U14121EJ2V0DS00 9 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 3. PIN CONFIGURATION (TOP VIEW) • 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD784214AGC-×××-8EU, µPD784215AGC-×××-8EU, µPD784216AGC-×××-8EU, µPD784217AGC-×××-8EU, µPD784218AGC-×××-8EU, µPD784214AYGC-×××-8EU, µPD784215AYGC-×××-8EU, µPD784216AYGC-×××-8EU, µPD784217AYGC-×××-8EU, µPD784218AYGC-×××-8EU P30/TO0 P103/TI8/TO8 P102/TI7/TO7 P101/TI6/TO6 P100/TI5/TO5 VDD P37/EXANote 5 P120/RTP0 P121/RTP1 P122/RTP2 P123/RTP3 P124/RTP4 P125/RTP5 P126/RTP6 P127/RTP7 VDD X2 X1 VSS XT2 XT1 RESET P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 AVDDNote 2 AVREF0 P10/ANI0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 1 74 2 73 3 72 4 71 5 70 6 69 7 68 8 67 9 66 10 65 11 64 12 63 13 62 14 61 15 60 16 59 17 58 18 57 19 56 20 55 21 54 22 53 23 52 24 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P67/ASTB P66/WAIT P65/WR P64/RD P63/A19 P90 TESTNote 1 P36/TI01 P35/TI00 P34/TI2 P33/TI1 P32/TO2 P31/TO1 P95 P94 P93 P92 P91 P62/A18 P61/A17 P60/A16 VSS P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P87/A7 P86/A6 P85/A5 P84/A4 P83/A3 P70/RxD2/SI2 P71/TxD2/SO2 P72/ASCK2/SCK2 P20/RxD1/SI1 P21/TxD1/SO1 P22/ASCK1/SCK1 P23/PCL P24/BUZ P25/SI0/SDA0Note 4 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVSSNote 3 P130/ANO0 P131/ANO1 AVREF1 P26/SO0 P27/SCK0/SCL0Note 4 Notes 1. Connect the TEST pin to VSS directly or via a pull-down resistor. For the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 Ω to 10 kΩ. 2. Connect the AVDD pin to VDD. 3. Connect the AVSS pin to VSS. 4. The SCL0 and SDA0 pins are available in µPD784216AY/784218AY Subseries products only. 5. The EXA pin is available in µPD784218A, 784218AY Subseries products only. 10 P11/ANI1 P12/ANI2 Data Sheet U14121EJ2V0DS00 P80/A0 P81/A1 P82/A2 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY • 100-pin plastic QFP (14 × 20 mm) µPD784214AGF-×××-3BA, µPD784215AGF-×××-3BA, µPD784216AGF-×××-3BA, µPD784217AGF-×××-3BA, µPD784218AGF-×××-3BA, µPD784214AYGF-×××-3BA, µPD784215AYGF-×××-3BA, µPD784216AYGF-×××-3BA, µPD784217AYGF-×××-3BA, µPD784218AYGF-×××-3BA VSS P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P87/A7 P86/A6 P85/A5 P60/A16 P61/A17 P62/A18 P63/A19 P64/RD P65/WR P66/WAIT P67/ASTB VDD P100/TI5/TO5 P101/TI6/TO6 P102/TI7/TO7 P103/TI8/TO8 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/TI00 P36/TI01 P37/EXANote 5 TESTNote 1 P90 P91 P92 P93 P94 P95 P120/RTP0 P121/RTP1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P84/A4 P83/A3 P82/A2 P81/A1 P80/A0 P27/SCK0/SCL0Note 4 P26/SO0 P25/SI0/SDA0Note 4 P24/BUZ P23/PCL P22/ASCK1/SCK1 P21/TxD1/SO1 P20/RxD1/SI1 P72/ASCK2/SCK2 P71/TxD2/SO2 P70/RxD2/SI2 AVREF1 P131/ANO1 P130/ANO0 AVSSNote 3 P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVREF0 AVDDNote 2 Notes 1. Connect the TEST pin to VSS directly or via a pull-down resistor. For the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 Ω to 10 kΩ. 2. Connect the AVDD pin to VDD. 3. Connect the AVSS pin to VSS. 4. The SCL0 and SDA0 pins are available in µPD784216AY/784218AY Subseries products only. 5. The EXA pin is available in µPD784218A, 784218AY Subseries products only. P122/RTP2 P123/RTP3 P124/RTP4 P125/RTP5 P126/RTP6 P127/RTP7 VDD X2 X1 VSS XT2 XT1 RESET P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 Data Sheet U14121EJ2V0DS00 11 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY A0 to A19: AD0 to AD7: ANI0 to ANI7: ANO0, ANO1: ASCK1, ASCK2: ASTB: AVDD: AVREF0, AVREF1: AVSS: BUZ: EXA Note 2 Address Bus Address/Data Bus Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Buzzer Clock P120 to P127: P130, P131: PCL: RD: RESET: RTP0 to RTP7: RxD1, RxD2: SCK0 to SCK2: SCL0Note 1: SDA0Note 1: SI0 to SI2: SO0 to SO2: TEST: TI00, TI01, TI1, TI2, TI5 to TI8: TxD1, TxD2: VDD: VSS: WAIT: WR: X1, X2: XT1, XT2: Port 12 Port 13 Programmable Clock Read Strobe Reset Real-time Output Port Receive Data Serial Clock Serial Clock Serial Data Serial Input Serial Output Test Timer Input Transmit Data Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock) : External Access Status Output Interrupt from Peripherals Non-maskable Interrupt Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 INTP0 to INTP6: NMI: P00 to P06: P10 to P17: P20 to P27: P30 to P37: P40 to P47: P50 to P57: P60 to P67: P70 to P72: P80 to P87: P90 to P95: P100 to P103: TO0 to TO2, TO5 to TO8: Timer Output Notes 1. The SCL0 and SDA0 pins are available in µPD784216AY/784218AY Subseries products only. 2. The EXA pin is available in µPD784218A, 784218AY Subseries products only. 12 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 4. BLOCK DIAGRAM INTP2/NMI INTP0, INTP1, INTP3 to INTP6 TI00 TI01 TO0 TI1 TO1 TI2 TO2 Programmable interrupt controller Timer/event counter (16 bits) Timer/event counter 1 (8 bits) Timer/event counter 2 (8 bits) Timer/event counter 5 (8 bits) Timer/event counter 6 (8 bits) Timer/event counter 7 (8 bits) Timer/event counter 8 (8 bits) Watch timer RAM Port 5 Watchdog timer Port 6 Port 7 RTP0 to RTP7 NMI/INTP2 ANO0 ANO1 AVREF1 AVSS P03/INTP3 ANI0 to ANI7 AVREF0 AVDD AVSS PCL Real-time output port Port 8 Port 9 D/A converter Port 10 Port 12 Port 13 A/D converter Clock output control Buzzer output 78K/IV CPU Core Bus I/F UART/IOE1 Baud-rate generator UART/IOE2 Baud-rate generator Clocked serial interfaceNote 1 RxD1/SI1 TxD1/SO1 ASCK1/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 SI0/SDA0 SO0 SCK0/SCL0 AD0 to AD7 A0 to A7 A8 to A15 TI5/TO5 A16 to A19 RD WR WAIT ASTB EXANote 2 Port 0 Port 1 Port 2 Port 3 Port 4 P00 to P06 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P72 P80 to P87 P90 to P95 P100 to P103 P120 to P127 P130, P131 RESET X1 System control X2 XT1 BUZ XT2 VDD VSS TEST 2 Notes 1. This function supports the I C bus interface and is available in µPD784216AY/784218AY Subseries TI6/TO6 ROM TI7/TO7 TI8/TO8 products only. 2. The EXA pin is available in µPD784218A, 784218AY Subseries products only. Remark The internal ROM and RAM capacities differ depending on the product. Data Sheet U14121EJ2V0DS00 13 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 5. PIN FUNCTIONS 5.1 Port Pins (1/2) Pin Name P00 P01 P02 P03 P04 P05 P06 P10 to P17 Input I/O I/O Alternate Function INTP0 INTP1 INTP2/NMI INTP3 INTP4 INTP5 INTP6 ANI0 to ANI7 Port 1 (P1): • 8-bit input only port Port 2 (P2): • 8-bit I/O port • Input/output can be specified in 1-bit units. • Whether specifying input mode or output mode, use of an on-chip pull-up resistor can be specified in 1-bit units by means of software. Function Port 0 (P0): • 7-bit I/O port • Input/output can be specified in 1-bit units. • Whether specifying input mode or output mode, use of an on-chip pull-up resistor can be specified in 1-bit units by means of software. P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47 I/O RxD1/SI1 TxD1/SO1 ASCK1/SCK1 PCL BUZ SI0/SDA0Note 1 SO0 SCK0/SCL0Note 1 I/O TO0 TO1 TO2 TI1 TI2 TI00 TI01 EXANote 2 Port 3 (P3): • 8-bit I/O port • Input/output can be specified in 1-bit units. • Whether specifying input mode or output mode, use of an on-chip pull-up resistor can be specified in 1-bit units by means of software. I/O AD0 to AD7 Port 4 (P4): • 8-bit I/O port • Input/output can be specified in 1-bit units. • All pins set in input mode can be connected to on-chip pull-up resistors by means of software. • LEDs can be driven directly. Port 5 (P5): • 8-bit I/O port • Input/output can be specified in 1-bit units. • All pins set in input mode can be connected to on-chip pull-up resistors by means of software. • LEDs can be driven directly. P50 to P57 I/O A8 to A15 Notes 1. This function is available in µPD784216AY/784218AY Subseries products only. 2. This function is available in µPD784218A, 784218AY Subseries products only. 14 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 5.1 Port Pins (2/2) Pin Name P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 I/O I/O I/O Alternate Function A16 A17 A18 A19 RD WR WAIT ASTB RxD2/SI2 TxD2/SO2 ASCK2/SCK2 Port 7 (P7): • 3-bit I/O port • Input/output can be specified in 1-bit units. • Whether specifying input mode or output mode, use of an on-chip pull-up resistor can be specified in 1-bit units by means of software. Port 8 (P8): • 8-bit I/O port • Input/output can be specified in 1-bit units. • Whether specifying input mode or output mode, use of an on-chip pull-up resistor can be specified in 1-bit units by means of software. • The interrupt control flag (KRIF) is set to 1 when a falling edge is detected at a pin of this port. − Port 9 (P9): • N-ch open-drain middle-voltage I/O port • 6-bit I/O port • Input/output can be specified in 1-bit units. • LEDs can be driven directly. Port 10 (P10): • 4-bit I/O port • Input/output can be specified in 1-bit units. • Whether specifying input mode or output mode, use of an on-chip pull-up resistor can be specified in 1-bit units by means of software. Port 12 (P12): • 8-bit I/O port • Input/output can be specified in 1-bit units. • Whether specifying input mode or output mode, use of an on-chip pull-up resistor can be specified in 1-bit units by means of software. Port 13 (P13): • 2-bit I/O port • Input/output can be specified in 1-bit units. Function Port 6 (P6): • 8-bit I/O port • Input/output can be specified in 1-bit units. • All pins set in input mode can be connected to on-chip pull-up resistors by means of software. P80 to P87 I/O A0 to A7 P90 to P95 I/O P100 P101 P102 P103 P120 to P127 I/O TI5/TO5 TI6/TO6 TI7/TO7 TI8/TO8 I/O RTP0 to RTP7 P130, P131 I/O ANO0, ANO1 Data Sheet U14121EJ2V0DS00 15 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 5.2 Non-Port Pins (1/2) Pin Name TI00 TI01 TI1 TI2 TI5 TI6 TI7 TI8 TO0 TO1 TO2 TO5 TO6 TO7 TO8 RxD1 RxD2 TxD1 TxD2 ASCK1 ASCK2 SI0 SI1 SI2 SO0 SO1 SO2 SDA0 SCK0 SCK1 SCK2 SCL0 NMI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 Input I/O Output Input Input Output Input Output I/O Input Alternate Function P35 P36 P33 P34 P100/TO5 P101/TO6 P102/TO7 P103/TO8 P30 P31 P32 P100/TI5 P101/TI6 P102/TI7 P103/TI8 P20/SI1 P70/SI2 P21/SO1 P71/SO2 P22/SCK1 P72/SCK2 P25/SDA0 P20/RxD1 P70/RxD2 P26 P21/TxD1 P71/TxD2 P25/SI0 P27/SCL0Note P22/ASCK1 P72/ASCK2 P27/SCK0 P02/INTP2 P00 P01 P02/NMI P03 P04 P05 P06 Note Function External count clock input to 16-bit timer counter Capture trigger signal input to capture/compare register 00 External count clock input to 8-bit timer counter 1 External count clock input to 8-bit timer counter 2 External count clock input to 8-bit timer counter 5 External count clock input to 8-bit timer counter 6 External count clock input to 8-bit timer counter 7 External count clock input to 8-bit timer counter 8 16-bit timer output (shared by 14-bit PWM output) 8-bit timer output (shared by 8-bit PWM output) Serial data input (UART1) Serial data input (UART2) Serial data output (UART1) Serial data output (UART2) Baud rate clock input (UART1) Baud rate clock input (UART2) Serial data input (3-wire serial I/O 0) Serial data input (3-wire serial I/O 1) Serial data input (3-wire serial I/O 2) Serial data output (3-wire serial I/O 0) Serial data output (3-wire serial I/O 1) Serial data output (3-wire serial I/O 2) Serial data input/output (I C bus) Serial clock input/output (3-wire serial I/O 0) Serial clock input/output (3-wire serial I/O 1) Serial clock input/output (3-wire serial I/O 2) Serial clock input/output (I C bus) Non-maskable interrupt request input External interrupt request input 2 2 Note This function is available in µPD784216AY/784218AY Subseries products only. 16 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 5.2 Non-Port Pins (2/2) Pin Name PCL BUZ RTP0 to RTP7 AD0 to AD7 A0 to A7 A8 to A15 A16 to A19 RD WR WAIT ASTB EXANote RESET X1 X2 XT1 XT2 ANI0 to ANI7 ANO0, ANO1 AVREF0 AVREF1 AVDD AVSS VDD VSS TEST Input Output Output Input Input − Input − Input Output − P10 to P17 P130, P131 − A/D converter analog input D/A converter analog output A/D converter reference voltage input D/A converter reference voltage input A/D converter positive power supply. Connect to VDD. GND for A/D converter and D/A converter. Connect to VSS. Positive power supply GND Connect this pin to VSS directly or via a pull-down resistor. For the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 Ω to 10 kΩ (this pin is for IC test). − Connecting crystal resonator for subsystem clock oscillation Output I/O Output Output Output I/O Output Alternate Function P23 P24 P120 to P127 P40 to P47 P80 to P87 P50 to P57 P60 to P63 P64 P65 P66 P67 P37 − − Function Clock output (for trimming main system clock and subsystem clock) Buzzer output Real-time output port that outputs data in synchronization with trigger Lower address/data bus for expanding memory externally Lower address bus for expanding memory externally Middle address bus for expanding memory externally Higher address bus for expanding memory externally Strobe signal output for reading from external memory Strobe signal output for writing to external memory Wait insertion at external memory access Strobe output that externally latches address information output to ports 4 through 6 and 8 to access external memory Status signal output at external memory access System reset input Connecting crystal resonator for main system clock oscillation Note This function is available in µPD784218A, 784218AY Subseries products only. Data Sheet U14121EJ2V0DS00 17 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 5.3 Pin I/O Circuits and Recommended Connections of Unused Pins The input/output circuit type of each pin and recommended connections of unused pins are shown in Table 5-1. For each type of input/output circuit, refer to Figure 5-1. Table 5-1. Types of Pin Input/Output Circuits and Recommended Connection of Unused Pins (1/2) Pin Name P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 to P06/INTP6 P10/ANI0 to P17/ANI7 P20/RxD1/SI1 P21/TxD1/SO1 P22/ASCK1/SCK1 P23/PCL P24/BUZ P25/SI0/SDA0Note 1 P26/SO0 P27/SCK0/SCL0 Note 1 I/O Circuit Type 8-N I/O I/O Recommended Connection of Unused Pins Input: Independently connect to VSS via a resistor Output: Leave open 9 10-K 10-L 10-K 10-L Input I/O Connect to VSS or VDD Input: Independently connect to VSS via a resistor Output: Leave open 10-K 10-L 10-K 12-E 8-N 10-M 12-E 5-A P30/TO0 to P32/TO2 P33/TI1, P34/TI2 P35/TI00, P36/TI01 P37/EXA Note 2 P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60/A16 to P63/A19 P64/RD P65/WR P66/WAIT P67/ASTB P70/RxD2/SI2 P71/TxD2/SO2 P72/ASCK2/SCK2 P80/A0 to P87/A7 P90 to P95 P100/TI5/TO5 P101/TI6/TO6 P102/TI7/TO7 P103/TI8/TO8 P120/RTP0 to P127/RTP7 P130/ANO0, P131/ANO1 8-N 10-M 8-N 12-E 13-D 8-N 12-E 12-F Notes 1. This function is available in µPD784216AY/784218AY Subseries products only. 2. This function is available in µPD784218A, 784218AY Subseries products only. 18 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Table 5-1. Types of Pin Input/Output Circuits and Recommended Connection of Unused Pins (2/2) Pin Name RESET XT1 XT2 AVREF0 AVREF1 AVDD AVSS TEST Connect to VSS Connect this pin to VSS directly or via a pull-down resistor. For the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 Ω to 10 kΩ. − I/O Circuit Type 2-G 16 − I/O Input Connect to VSS Leave open Connect to VSS Connect to VDD Recommended Connection of Unused Pins − Remark Because the circuit type numbers are standardized among the 78K Series products, they are not sequential in some models (i.e., some circuits are not provided). Data Sheet U14121EJ2V0DS00 19 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Figure 5-1. Types of Pin I/O Circuits (1/2) Type 2-G Type 10-K VDD Pullup enable IN Data VDD P-ch P-ch IN/OUT Open drain Output disable Schmitt-triggered input with hysteresis characteristics N-ch Type 5-A VDD Type 10-L VDD Pullup enable VDD Data P-ch P-ch Pullup enable VDD Data IN/OUT P-ch P-ch IN/OUT Open drain Output disable VSS N-ch Output disable N-ch Input enable Type 8-N VDD Type 10-M VDD Pullup enable VDD Data P-ch P-ch Pullup enable VDD Data IN/OUT P-ch P-ch IN/OUT Output disable VSS N-ch Output disable N-ch Type 9 Type 12-E VDD IN P-ch N-ch Comparator + – Pullup enable VDD Data P-ch P-ch IN/OUT (Threshold voltage) Output disable Input enable Input enable P-ch Analog output voltage N-ch N-ch 20 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Figure 5-1. Types of Pin I/O Circuits (2/2) Type 12-F VDD Data P-ch IN/OUT Output disable Input enable N-ch VSS P-ch N-ch VSS Type 16 Feedback cut-off P-ch Analog output voltage XT1 XT2 Type 13-D IN/OUT Data Output disable N-ch VDD RD P-ch Middle-voltage input buffer Data Sheet U14121EJ2V0DS00 21 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 6. CPU ARCHITECTURE 6.1 Memory Space A memory space of 1 MB can be accessed. Mapping of the internal data area (special function registers and internal RAM) can be specified by the LOCATION instruction. The LOCATION instruction must always be executed after reset cancellation, and must not be used more than once. (1) When LOCATION 0H instruction is executed • Internal memory The internal data area and internal ROM area are mapped as follows. Part Number Internal Data Area 0F100H to 0FFFFH 0EB00H to 0FFFFH 0DF00H to 0FFFFH 0CD00H to 0FFFFH Internal ROM Area 00000H to 0F0FFH 10000H to 17FFFH 00000H to 0EAFFH 10000H to 1FFFFH 00000H to 0DEFFH 10000H to 1FFFFH 00000H to 0CCFFH 10000H to 2FFFFH 00000H to 0CCFFH 10000H to 3FFFFH µPD784214A, µPD784214AY µPD784215A, µPD784215AY µPD784216A, µPD784216AY µPD784217A, µPD784217AY µPD784218A, µPD784218AY Caution The following areas that overlap the internal data area of the internal ROM cannot be used when the LOCATION 0H instruction is executed. Part Number Unusable Area 0F100H to 0FFFFH (3,840 bytes) 0EB00H to 0FFFFH (5,376 bytes) 0DF00H to 0FFFFH (8,448 bytes) 0CD00H to 0FFFFH (13,056 bytes) µPD784214A, µPD784214AY µPD784215A, µPD784215AY µPD784216A, µPD784216AY µPD784217A, µPD784217AY µPD784218A, µPD784218AY • External memory The external memory is accessed in external memory expansion mode. 22 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (2) When LOCATION 0FH instruction is executed • Internal memory The internal data area and internal ROM area are mapped as follows. Part Number Internal Data Area FF100H to FFFFFH FEB00H to FFFFFH FDF00H to FFFFFH FCD00H to FFFFFH Internal ROM Area 00000H to 17FFFH 00000H to 1FFFFH 00000H to 1FFFFH 00000H to 2FFFFH 00000H to 3FFFFH µPD784214A, µPD784214AY µPD784215A, µPD784215AY µPD784216A, µPD784216AY µPD784217A, µPD784217AY µPD784218A, µPD784218AY • External memory The external memory is accessed in external memory expansion mode. Data Sheet U14121EJ2V0DS00 23 www.DataSheet4U.com 24 On execution of LOCATION 0H instruction F F F F FH Figure 6-1. Memory Map of µPD784214A, 784214AY On execution of LOCATION 0FH instruction F F F F F H Special F F FDFH Note 1 F F FD0H FFF 0 0H F FEF FH function registers (SFR) (256 bytes) µ µ µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY µ 0 FEF FH F FEF FH External memory (928 KB) 1 8 0 0 0H 1 7 F F FH Note 1 General-purpose registers (128 bytes) 0 FE8 0H 0 FE 7 FH FFE8 0H F FE 7 FH FF 1 0 0H F F 0 F FH Internal RAM (3,584 bytes) Internal ROM 0 F E 3 BH (32,768 bytes) 1 0 0 0 0H 0 F F F FH Special function registers 0 F FDFH Note 1 0 F FD0H (256 bytes) 0 FF 0 0H 0 FEF FH Internal RAM (3,584 bytes) 0 F 1 0 0H 0 F 0 F FH (SFR) 0 FE0 6H Macro service control word area (54 bytes) Data area (512 bytes) F F E 3 BH FFE0 6H Data Sheet U14121EJ2V0DS00 0 FD0 0H 0 FCF FH F FD0 0H F FCF FH Program/data area (3,072 bytes) 0 F 1 0 0H FF 1 0 0H External memory (980,736 bytes) Note 1 1 7 F F FH 1 0 0 0 0H 1 7 F F FH Note 2 0 F 0 F FH Note 4 0 1 0 0 0H 0 0 F F FH Program/data area CALLF entry area (2 KB) 0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH 0 0 0 4 0H 0 0 0 3 FH Note 3 Internal ROM (61,696 bytes) 1 8 0 0 0H 1 7 F F FH CALLT table area (64 bytes) Vector table area (64 bytes) Internal ROM (96 KB) Note 4 0 0 0 0 0H 0 0 0 0 0H 0 0 0 0 0H Notes 1. Accessed in external memory expansion mode. 2. This 3,840-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. On execution of LOCATION 0H instruction: 94,464 bytes, on execution of LOCATION 0FH instruction: 98,304 bytes 4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area. www.DataSheet4U.com Figure 6-2. Memory Map of µPD784215A, 784215AY On execution of LOCATION 0H instruction F F F F FH On execution of LOCATION 0FH instruction F F F F F H Special F F FDFH Note 1 F F FD0H FFF 0 0H F FEF FH µ µ µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY µ function registers (SFR) (256 bytes) External memory (896 KB) Note 1 0 FEF FH F FEF FH General-purpose registers (128 bytes) 0 FE8 0H 0 FE 7 FH FFE8 0H F FE 7 FH FEB 0 0H FEAF FH Internal RAM (5,120 bytes) 2 0 0 0 0H 1 F F F FH 1 0 0 0 0H 0 F F F FH Special 0 F FDFH Note 1 0 F FD0H 0 FF 0 0H 0 FEF FH Internal ROM (65,536 bytes) function registers (SFR) (256 bytes) 0 F E 3 BH 0 FE0 6H Macro service control word area (54 bytes) Data area (512 bytes) F F E 3 BH FFE0 6H Data Sheet U14121EJ2V0DS00 Internal RAM (5,120 bytes) 0 EB 0 0H 0 EAF FH 0 FD0 0H 0 FCF FH F FD0 0H F FCF FH Program/data area (4,608 bytes) 0 EB 0 0H FEB 0 0H 1 F F F FH External memory (912,128 bytes) Note 1 1 F F F FH 1 0 0 0 0H Note 2 0 EAF FH Note 4 0 1 0 0 0H 0 0 F F FH Program/data area Note 3 Internal ROM (60,160 bytes) 0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH 0 0 0 4 0H 0 0 0 3 FH 0 0 0 0 0H 0 0 0 0 0H CALLF entry area (2 KB) 2 0 0 0 0H 1 F F F FH CALLT table area (64 bytes) Vector table area (64 bytes) Internal ROM (128 KB) Note 4 0 0 0 0 0H Notes 1. Accessed in external memory expansion mode. 2. This 5,376-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. On execution of LOCATION 0H instruction: 125,696 bytes, on execution of LOCATION 0FH instruction: 131,072 bytes 4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area. 25 www.DataSheet4U.com 26 On execution of LOCATION 0H instruction F F F F FH Figure 6-3. Memory Map of µPD784216A, 784216AY On execution of LOCATION 0FH instruction F F F F F H Special F F FDFH Note 1 F F FD0H FFF 0 0H F FEF FH function registers (SFR) (256 bytes) µ µ µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY µ External memory (896 KB) Note 1 0 FEF FH F FEF FH General-purpose registers (128 bytes) 0 FE8 0H 0 FE 7 FH FFE8 0H F FE 7 FH FDF 0 0H FDE F FH Internal RAM (8,192 bytes) 2 0 0 0 0H 1 F F F FH 1 0 0 0 0H 0 F F F FH Special 0 F FDFH Note 1 0 F FD0H 0 FF 0 0H 0 FEF FH Internal ROM (65,536 bytes) function registers (SFR) (256 bytes) 0 F E 3 BH 0 FE0 6H Macro service control word area (54 bytes) Data area (512 bytes) F F E 3 BH FFE0 6H Data Sheet U14121EJ2V0DS00 Internal RAM (8,192 bytes) 0DF 0 0H 0 DE F FH 0 FD0 0H 0 FCF FH F FD0 0H F FCF FH Program/data area (7,680 bytes) 0DF 0 0H FDF 0 0H 1 F F F FH External memory (909,056 bytes) Note 1 1 F F F FH 1 0 0 0 0H Note 2 0 DE F FH Note 4 0 1 0 0 0H 0 0 F F FH Program/data area Note 3 Internal ROM (57,088 bytes) 0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH 0 0 0 4 0H 0 0 0 3 FH 0 0 0 0 0H 0 0 0 0 0H CALLF entry area (2 KB) 2 0 0 0 0H 1 F F F FH CALLT table area (64 bytes) Vector table area (64 bytes) Internal ROM (128 KB) Note 4 0 0 0 0 0H Notes 1. Accessed in external memory expansion mode. 2. This 8,448-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. On execution of LOCATION 0H instruction: 122,624 bytes, on execution of LOCATION 0FH instruction: 131,072 bytes 4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area. www.DataSheet4U.com Figure 6- 4. Memory Map of µPD784217A, 784217AY On execution of LOCATION 0H instruction F F F F FH On execution of LOCATION 0FH instruction F F F F F H Special F F FDFH Note 1 F F FD0H FFF 0 0H F FEF FH µ µ µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY µ function registers (SFR) (256 bytes) 0 FEF FH F FEF FH External memory (928 KB) 1 8 0 0 0H 1 7 F F FH Note 1 General-purpose registers (128 bytes) 0 FE8 0H 0 FE 7 FH FFE8 0H F FE 7 FH F CD 0 0 H F CC F F H Internal RAM (12,800 bytes) Internal ROM 0 F E 3 BH (32,768 bytes) 1 0 0 0 0H 0 F F F FH Special function registers 0 F FDFH Note 1 0 F FD0H (256 bytes) 0 FF 0 0H 0 FEF FH Internal RAM (12,800 bytes) 0 CD 0 0 H 0 CC F F H (SFR) 0 FE0 6H Macro service control word area (54 bytes) Data area (512 bytes) F F E 3 BH FFE0 6H Data Sheet U14121EJ2V0DS00 0 FD0 0H 0 FCF FH F FD0 0H F FCF FH Program/data area (12,288 bytes) 0 CD 0 0 H F CD 0 0 H External memory (838,912 bytes) Note 1 2 F F F FH 1 0 0 0 0H 1 7 F F FH Note 2 0 F 0 F FH Note 4 0 1 0 0 0H 0 0 F F FH Program/data area CALLF entry area (2 KB) 0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH 0 0 0 4 0H 0 0 0 3 FH Note 3 Internal ROM (52,480 bytes) 3 0 0 0 0H 2 F F F FH CALLT table area (64 bytes) Vector table area (64 bytes) Internal ROM (192 KB) Note 4 0 0 0 0 0H 0 0 0 0 0H 0 0 0 0 0H Notes 1. Accessed in external memory expansion mode. 2. This 13,056-byte area can be used as internal ROM only when the LOCATION 0FH instruction is executed. 3. On execution of LOCATION 0H instruction: 183,552 bytes, on execution of LOCATION 0FH instruction: 196,608 bytes 4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area. 27 www.DataSheet4U.com 28 F F F F FH Figure 6-5. Memory Map of µPD784218A, 784218AY On execution of LOCATION 0H instruction On execution of LOCATION 0FH instruction F F F F F H Special F F FDFH Note 1 F F FD0H FFF 0 0H F FEF FH function registers (SFR) (256 bytes) µ µ µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY µ External memory (768 KB) Note 1 0 FEF FH F FEF FH General-purpose registers (128 bytes) 0 FE8 0H 0 FE 7 FH FFE8 0H F FE 7 FH F CD 0 0 H F CC F F H Internal RAM (12,800 bytes) 4 0 0 0 0H 3 F F F FH 1 0 0 0 0H 0 F F F FH Special 0 F FDFH Note 1 0 F FD0H 0 FF 0 0H 0 FEF FH Internal ROM (196,608 bytes) function registers (SFR) (256 bytes) 0 F E 3 BH 0 FE0 6H Macro service control word area (54 bytes) Data area (512 bytes) F F E 3 BH FFE0 6H Data Sheet U14121EJ2V0DS00 Internal RAM (12,800 bytes) 0 CD 0 0 H 0 CC F F H 0 FD0 0H 0 FCF FH F FD0 0H F FCF FH Program/data area (12,288 bytes) 0 CD 0 0 H F CD 0 0 H 3 F F F FH External memory (773,376 bytes) Note 1 3 F F F FH 1 0 0 0 0H Note 2 0 CC F F H Note 4 0 1 0 0 0H 0 0 F F FH Program/data area Note 3 Internal ROM (52,480 bytes) 0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH 0 0 0 4 0H 0 0 0 3 FH 0 0 0 0 0H 0 0 0 0 0H CALLF entry area (2 KB) 4 0 0 0 0H 3 F F F FH CALLT table area (64 bytes) Vector table area (64 bytes) Internal ROM (256 KB) Note 4 0 0 0 0 0H Notes 1. Accessed in external memory expansion mode. 2. This 13,056-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. On execution of LOCATION 0H instruction: 249,088 bytes, on execution of LOCATION 0FH instruction: 262,144 bytes 4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area. www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 6.2 CPU Registers 6.2.1 General-purpose registers Sixteen 8-bit general-purpose registers are available. Two 8-bit registers can also be used in pairs as a 16-bit register. Of the 16-bit registers, four can be used in combination with an 8-bit register for address expansion as 24bit address specification registers. Eight banks of these register sets are available and can be selected by using software or the context switching function. The general-purpose registers except the V, U, T, and W registers for address expansion are mapped to the internal RAM. Figure 6-6. General-Purpose Register Format A (R1) AX (RP0) B (R3) BC (RP1) R5 RP2 R7 RP3 V VVP (RG4) U R11 R9 VP (RP4) X (R0) C (R2) R4 R6 R8 R10 T UP (RP5) UUP (RG5) D (R13) E (R12) DE (RP6) TDE (RG6) H (R15) L (R14) 8 banks WHL (RG7) HL (RP7) W Names in parentheses indicate absolute names. Caution Registers R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C, B, AX, and BC registers, respectively, by setting the RSS bit of the PSW to 1. recycling the program of the 78K/III Series. However, use this function only for Data Sheet U14121EJ2V0DS00 29 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 6.2.2 Control registers (1) Program counter (PC) The program counter is a 20-bit register whose contents are automatically updated when the program is executed. Figure 6-7. Format of Program Counter (PC) 19 PC 0 (2) Program status word (PSW) This register holds the statuses of the CPU. Its contents are automatically updated when the program is executed. Figure 6-8. Format of Program Status Word (PSW) 15 PSWH PSW 7 PSWL S UF 14 RBS2 13 RBS1 12 RBS0 11 – 10 – 9 – 8 – 6 Z 5 RSS Note 4 AC 3 IE 2 P/V 1 0 0 CY Note This flag is provided to maintain compatibility with the 78K/III Series. Be sure to clear this flag to 0, except when the software for the 78K/III Series is used. (3) Stack pointer (SP) This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the higher 4 bits of this pointer. Figure 6-9. Format of Stack Pointer (SP) 23 SP 0 0 0 20 0 0 30 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 6.2.3 Special function registers (SFRs) The special function registers, such as the mode registers and control registers of the internal peripheral hardware, are registers to which special functions are assigned. These registers are mapped to the 256-byte space of addresses 0FF00H to 0FFFFHNote. Note On execution of the LOCATION 0H instruction. FFF00H to FFFFFH on execution of the LOCATION 0FH instruction. Caution Do not access an address in this area to which no SFR is assigned. If such an address is accessed by mistake, the µPD784218A may enter a deadlocked state. This deadlock state can be cleared only by inputting the RESET signal. Table 6-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows. • Symbol ................................ Symbol indicating an SFR. in the C compiler (CC78K4). • R/W ..................................... Indicates whether the SFR is read-only, write-only, or read/write. R/W: Read/write R: W: Read-only Write-only This symbol is reserved for NEC's assembler (RA78K4). It can be used as an sfr variable by means of the #pragma sfr command • Bit units for manipulation ..... Bit units in which the value of the SFR can be manipulated. SFRs that can be manipulated in 16-bit units can be described as the operand sfrp of an instruction. To specify the address of this SFR, describe an even address. SFRs that can be manipulated in 1-bit units can be described as the operand of a bit manipulation instruction. • After reset............................ Indicates the status of the register when the RESET signal has been input. Data Sheet U14121EJ2V0DS00 31 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Table 6-1. Special Function Register (SFR) List (1/4) AddressNote 1 Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 Bit 0FF00H 0FF01H 0FF02H 0FF03H 0FF04H 0FF05H 0FF06H 0FF07H 0FF08H 0FF09H 0FF0AH 0FF0CH 0FF0DH 0FF10H 0FF11H 0FF12H 0FF13H 0FF14H 0FF15H 0FF16H 0FF18H 0FF1AH 0FF1CH 0FF20H 0FF22H 0FF23H 0FF24H 0FF25H 0FF26H 0FF27H 0FF28H 0FF29H 0FF2AH 0FF2CH 0FF2DH Capture/compare register 00 (16-bit timer/event counter) Capture/compare register 01 (16-bit timer/event counter) Capture/compare control register 0 16-bit timer mode control register 16-bit timer output control register Prescaler mode register 0 Port 0 mode register Port 2 mode register Port 3 mode register Port 4 mode register Port 5 mode register Port 6 mode register Port 7 mode register Port 8 mode register Port 9 mode register Port 10 mode register Port 12 mode register Port 13 mode register CR00 R/W − − √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ − − √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ − − − − − − − − − − − − − − − − FFH Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 12 Port 13 16-bit timer counter P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P12 P13 TM0 R R/W R R/W √ √ √ √ √ √ √ √ √ √ √ √ √ − 8 Bits √ √ √ √ √ √ √ √ √ √ √ √ √ − 16 Bits − − − − − − − − − − − − − √ 0000H 00HNote 2 After Reset CR01 CRC0 TMC0 TOC0 PRM0 PM0 PM2 PM3 PM4 PM5 PM6 PM7 PM8 PM9 PM10 PM12 PM13 00H Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH instruction is executed. 2. Because each port is initialized to input mode after reset, "00H" is not actually read. The output latch is initialized to "0". 32 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Table 6-1. Special Function Register (SFR) List (2/4) AddressNote Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 Bit 0FF30H 0FF32H 0FF33H 0FF37H 0FF38H 0FF3AH 0FF3CH 0FF40H 0FF42H 0FF4EH 0FF50H 0FF51H 0FF52H 0FF53H 0FF54H 0FF55H 0FF56H 0FF57H 0FF60H 0FF61H 0FF62H 0FF63H 0FF64H 0FF65H 0FF66H 0FF67H 0FF68H 0FF69H 0FF6AH 0FF6BH 0FF6CH 0FF6DH 0FF6EH 0FF6FH 0FF70H 0FF71H 0FF72H 0FF73H Pull-up resistor option register 0 Pull-up resistor option register 2 Pull-up resistor option register 3 Pull-up resistor option register 7 Pull-up resistor option register 8 Pull-up resistor option register 10 Pull-up resistor option register 12 Clock output control register Port function control register Pull-up resistor option register 8-bit timer counter 1 8-bit timer counter 2 PU0 PU2 PU3 PU7 PU8 PU10 PU12 CKS PF2 PUO TM1 TM2 R/W TM1W R R/W √ √ √ √ √ √ √ √ √ √ − − − − √ √ √ √ TM5W R − − TM7W − − R/W − − − − √ √ √ √ √ √ √ √ √ √ R √ √ 8 Bits √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ − − − − 00H √ √ √ √ √ √ √ √ √ √ √ 16 Bits − − − − − − − − − − √ 0000H 00H After Reset Compare register 10 (8-bit timer/event counter 1) CR10 CR1W Compare register 20 (8-bit timer/event counter 2) CR20 8-bit timer mode control register 1 8-bit timer mode control register 2 Prescaler mode register 1 Prescaler mode register 2 8-bit timer counter 5 8-bit timer counter 6 8-bit timer counter 7 8-bit timer counter 8 TMC1 TMC1W TMC2 PRM1 PRM1W PRM2 TM5 TM6 TM7 TM8 Compare register 50 (8-bit timer/event counter 5) CR50 CR5W Compare register 60 (8-bit timer/event counter 6) CR60 Compare register 70 (8-bit timer/event counter 7) CR70 CR7W Compare register 80 (8-bit timer/event counter 8) CR80 8-bit timer mode control register 5 8-bit timer mode control register 6 8-bit timer mode control register 7 8-bit timer mode control register 8 Prescaler mode register 5 Prescaler mode register 6 Prescaler mode register 7 Prescaler mode register 8 Asynchronous serial interface mode register 1 Asynchronous serial interface mode register 2 Asynchronous serial interface status register 1 Asynchronous serial interface status register 2 TMC5 TMC5W TMC6 TMC7 TMC7W TMC8 PRM5 PRM5W PRM6 PRM7 PRM7W PRM8 ASIM1 ASIM2 ASIS1 ASIS2 Note When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH instruction is executed. Data Sheet U14121EJ2V0DS00 33 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Table 6-1. Special Function Register (SFR) List (3/4) AddressNote 1 Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 Bit 0FF74H Transmit shift register 1 Receive buffer register 1 0FF75H Transmit shift register 2 Receive buffer register 2 0FF76H 0FF77H 0FF7AH 0FF80H 0FF81H 0FF83H 0FF84H 0FF85H 0FF86H 0FF87H 0FF8CH 0FF90H 0FF91H 0FF92H 0FF94H 0FF95H 0FF96H 0FF98H 0FF99H 0FF9AH 0FF9BH 0FF9CH 0FFA0H 0FFA2H 0FFA8H 0FFA9H 0FFAAH 0FFACH 0FFADH 0FFAEH 0FFAFH 0FFB0H 0FFB2H 0FFB4H Baud rate generator control register 1 Baud rate generator control register 2 Oscillation mode select register A/D converter mode register A/D converter input select register A/D conversion result register D/A conversion value setting register 0 D/A conversion value setting register 1 D/A converter mode register 0 D/A converter mode register 1 External bus type select register Serial operation mode register 0 Serial operation mode register 1 Serial operation mode register 2 Serial I/O shift register 0 Serial I/O shift register 1 Serial I/O shift register 2 Real-time output buffer register L Real-time output buffer register H Real-time output port mode register Real-time output port control register Watch timer mode control register External interrupt rising edge enable register External interrupt falling edge enable register In-service priority register Interrupt select control register Interrupt mode control register Interrupt mask flag register 0L Interrupt mask flag register 0H Interrupt mask flag register 1L Interrupt mask flag register 1H I2C bus control registerNote 2 Prescaler mode register for serial clock Slave address register TXS1 RXB1 TXS2 RXB2 BRGC1 BRGC2 CC ADM ADIS ADCR DACS0 DACS1 DAM0 DAM1 EBTS CSIM0 CSIM1 CSIM2 SIO0 SIO1 SIO2 RTBL RTBH RTPM RTPC WTM EGP0 EGN0 ISPR SNMI IMC MK0L MK0H MK1L MK1H IICC0 SPRM0 SVA0 MK1 MK0 R R/W R R/W W R W R R/W − − − − √ √ √ √ √ − √ √ √ √ √ √ √ √ − − − − − √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ 8 Bits √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ − − − 00H √ 16 Bits − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − √ 80H FFFFH Undefined 00H 00H FFH After Reset Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH instruction is executed. 2. µPD784216AY/784218AY Subseries only 34 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Table 6-1. Special Function Register (SFR) List (4/4) AddressNote 1 Special Function Register (SFR) Name I2C bus status registerNote 2 Serial shift register Standby control register Watchdog timer mode register Memory expansion mode register Programmable wait control register 1 Clock status register Oscillation stabilization time specification register External SFR area Interrupt control register (INTWDTM) Interrupt control register (INTP0) Interrupt control register (INTP1) Interrupt control register (INTP2) Interrupt control register (INTP3) Interrupt control register (INTP4) Interrupt control register (INTP5) Interrupt control register (INTP6) Interrupt control register (INTIIC0/INTCSI0) Interrupt control register (INTSER1) Interrupt control register (INTSR1/INTCSI1) Interrupt control register (INTST1) Interrupt control register (INTSER2) Interrupt control register (INTSR2/INTCSI2) Interrupt control register (INTST2) Interrupt control register (INTTM3) Interrupt control register (INTTM00) Interrupt control register (INTTM01) Interrupt control register (INTTM1) Interrupt control register (INTTM2) Interrupt control register (INTAD) Interrupt control register (INTTM5) Interrupt control register (INTTM6) Interrupt control register (INTTM7) Interrupt control register (INTTM8) Interrupt control register (INTWT) Interrupt control register (INTKR) Symbol R/W Bit Units for Manipulation 1 Bit 0FFB6H 0FFB8H 0FFC0H 0FFC2H 0FFC4H 0FFC7H 0FFCEH 0FFCFH 0FFD0H to 0FFDFH 0FFE0H 0FFE1H 0FFE2H 0FFE3H 0FFE4H 0FFE5H 0FFE6H 0FFE7H 0FFE8H 0FFE9H 0FFEAH 0FFEBH 0FFECH 0FFEDH 0FFEEH 0FFEFH 0FFF0H 0FFF1H 0FFF2H 0FFF3H 0FFF4H 0FFF5H 0FFF6H 0FFF7H 0FFF8H 0FFF9H 0FFFAH IICS0 IIC0 STBC WDM MM PWC1 PCS OSTS − WDTIC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 CSIIC0 SERIC1 SRIC1 STIC1 SERIC2 SRIC2 STIC2 TMIC3 TMIC00 TMIC01 TMIC1 TMIC2 ADIC TMIC5 TMIC6 TMIC7 TMIC8 WTIC KRIC R R/W R R/W √ √ − − √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ 8 Bits √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ 16 Bits − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − 43H 30H 00H 20H AAH 32H 00H − 00H After Reset Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH instruction is executed. 2. µPD784216AY/784218AY Subseries only Data Sheet U14121EJ2V0DS00 35 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 7. PERIPHERAL HARDWARE FUNCTIONS 7.1 Ports The ports shown in Figure 7-1 are provided to make various control operations possible. Table 7-1 shows the function of each port. Ports 0, 2 through 8, 10, and 12 can be connected to on-chip pull-up resistors by means of software when in input mode. Figure 7-1. Port Configuration Port 7                               P70 P72 P80 P00 Pprt 8 P06     Port 0    P87 P90 P10 to P17 8 Port 1 Port 9 P20 P95 P100 P103 P120 Port 10 P27 P30     Port 2        Port 3        Port 4        Port 5        Port 6    Port 12 P127 P130 P131 P37 P40 Port 13 P47 P50 P57 P60 P67 36 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Table 7-1. Port Functions Port Name Pin Name Function • Input/output can be specified in 1-bit units • Input port • Input/output can be specified in 1-bit units • Input/output can be specified in 1-bit units • Input/output can be specified in 1-bit units • LEDs can be driven directly • Input/output can be specified in 1-bit units • LEDs can be driven directly • Input/output can be specified in 1-bit units • Input/output can be specified in 1-bit units • Input/output can be specified in 1-bit units • N-ch open-drain I/O port • Input/output can be specified in 1-bit units • LEDs can be driven directly • Input/output can be specified in 1-bit units • Input/output can be specified in 1-bit units • Input/output can be specified in 1-bit units Specification of Pull-up Resistor Connection by Software Can be specified in 1-bit units − Can be specified in 1-bit units Can be specified in 1-bit units Can be specified in 1-port units Port 0 Port 1 Port 2 Port 3 Port 4 P00 to P06 P10 to P17 P20 to P27 P30 to P37 P40 to P47 Port 5 P50 to P57 Can be specified in 1-port units Port 6 Port 7 Port 8 Port 9 P60 to P67 P70 to P72 P80 to P87 P90 to P95 Can be specified in 1-port units Can be specified in 1-bit units Can be specified in 1-bit units − Port 10 Port 12 Port 13 P100 to P103 P120 to P127 P130, P131 Can be specified in 1-bit units Can be specified in 1-bit units − 7.2 Clock Generator An on-chip clock generator necessary for operation is provided. This clock generator has a frequency divider. If high-speed operation is not necessary, the internal operating frequency can be lowered by the frequency divider to reduce the current consumption. Figure 7-2. Block Diagram of Clock Generator XT1 XT2 Subsystem fXT clock oscillator Prescaler Main system clock oscillator IDLE controller Watch timer, clock output function fX Frequency divider fX Selector X1 X2 fXX fXX 2 Prescaler Clock to peripheral hardware 2 STOP or bit 2 (MCK) of the standby control register (STBC) is set to 1 when the subclock is selected as the CPU clock fXX 22 fXX 23 Selector STOP, IDLE controller HALT controller CPU clock (fCPU) Internal system clock (fCLK) Data Sheet U14121EJ2V0DS00 37 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Figure 7-3. Example of Using Main System Clock Oscillator (1) Crystal/ceramic oscillation (2) External clock X2 X2 X1 VSS Crystal resonator or ceramic resonator External clock µ PD74HCU04 X1 Figure 7-4. Example of Using Subsystem Clock Oscillator (1) Crystal oscillation (2) External clock 32.768 kHz VSS XT2 External clock XT2 XT1 XT1 µPD74HCU04 Caution When using the main system clock and subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in Figures 7-3 and 7-4 to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. Note that the subsystem clock oscillator has a low amplification factor to reduce the current consumption. 38 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 7.3 Real-Time Output Port The real-time output function is to transfer data set in advance to the real-time output buffer register to the output latch as soon as the timer interrupt or external interrupt has occurred in order to output the data to an external device. The pins that output the data to the external device constitute a port called a real-time output port. Because the real-time output port can output signals without jitter, it is ideal for controlling a stepper motor. Figure 7-5. Block Diagram of Real-Time Output Port Internal bus Real-time output port control register (RTPC) RTPOE BYTE EXTR INTP2TRG INTTM1 INTTM2 Output trigger Controller High-order 4 bits of real-time output buffer register (RTBH) Low-order 4 bits of real-time output buffer register (RTBL) Real-time output port mode register (RTPM) Port 12 output latch Real-time output port output latch P127······································ P120 RTP7······································ RTP0 RTPOE bit P12n/RTPn pin output (n = 0 to 7) P127/ P120/ RTP7······································ RTP0 Data Sheet U14121EJ2V0DS00 39 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 7.4 Timer/Event Counter One unit of 16-bit timer/event counter and six 8-bit timer/event counters are provided. Because a total of eight interrupt requests are supported, these timer/event counters can be used as eight timer/counters. Table 7-2. Operations of Timers Name 8-Bit 8-Bit 8-Bit 8-Bit 8-Bit 8-Bit 16-Bit Timer/ Timer/ Timer/ Timer/ Timer/ Timer/ Timer/ Event Event Event Event Event Event Event Counter Counter 1 Counter 2 Counter 5 Counter 6 Counter 7 Counter 8 − √ 1 ch √ 1 ch √ − √ √ 2 inputs 2 1 ch √ 1 ch − √ √ − − 1 √ √ 1 ch √ 1 ch − √ √ − − 1 1 ch √ 1 ch − √ √ − − 1 √ √ √ 1 ch √ 1 ch − √ √ − − 1 1 ch √ 1 ch − √ √ − − 1 √ √ √ 1 ch √ 1 ch − √ √ − − 1 √ Item Count width 8 bits 16 bits Operation mode Interval timer External event counter Function Timer output PPG output PWM output Square wave output One-shot pulse output Pulse width measurement Number of interrupt requests 40 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Figure 7-6. Block Diagram of Timer/Event Counters 16-bit timer/event counter fXX/4 fXX/16 INTTM3 Clear Selector 16-bit timer counter (TM0) 16 Selector TI01 Edge detector INTTM00 16 INTTM01 TI00 Edge detector 16-bit capture/compare register 01 (CR01) Output controller 16-bit capture/compare register 00 (CR00) TO0 8-bit timer/event counter 1, 5, 7 fXX/22 fXX/23 Clear Selector fXX/24 fXX/25 fXX/27 fXX/29 TIn Edge detector 8-bit timer counter n (TMn) 8 OVF Output controller TOn 8-bit compare register n0 (CRn0) INTTMn + 1 Selector INTTMn Remarks 1. n = 1, 5, 7 2. OVF: Overflow flag 8-bit timer/event counter 2, 6, 8 TMn – 1 fXX/22 fXX/23 fXX/24 fXX/2 fXX/2 5 7 Clear Selector 8-bit timer counter n (TMn) 8 OVF Output controller TOn fXX/29 TIn Edge detector 8-bit compare register n0 (CRn0) INTTMn Remarks 1. n = 2, 6, 8 2. OVF: Overflow flag Data Sheet U14121EJ2V0DS00 41 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 7.5 A/D Converter An A/D converter converts an analog signal input into a digital signal. This microcontroller is provided with an A/D converter with a resolution of 8 bits and eight channels (ANI0 to ANI7). This A/D converter is of successive approximation type and the result of conversion is stored in an 8-bit A/D conversion result register (ADCR). The A/D converter can be started in the following two ways: • Hardware start Conversion is started by trigger input (P03). • Software start Conversion is started by setting the A/D converter mode register (ADM). One analog input channel is selected from ANI0 to ANI7 for A/D conversion. When A/D conversion is started by means of hardware start, conversion is stopped after it has been completed. When conversion is started by means of software start, A/D conversion is repeatedly executed. Each time conversion has been completed, an interrupt request (INTAD) is generated. Figure 7-7. Block Diagram of A/D Converter Series resistor string ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 AVSS Successive approximation register (SAR) Selector AVDD AVREF0 Sample & hold circuit Voltage comparator Tap selector INTP3/P03 Edge detector Controller INTAD Edge detector A/D conversion result register (ADCR) INTP3 Internal bus 42 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 7.6 D/A Converter A D/A converter converts a digital signal input into an analog signal. This microcontroller is provided with a voltage output type D/A converter with a resolution of 8 bits and two channels. The conversion method is of R-2R resistor ladder type. D/A conversion is started by setting DACE0 of D/A converter mode register 0 (DAM0) and DACE1 of D/A converter mode register 1 (DAM1). The D/A converter operates in the following two modes: • Normal mode The converter outputs an analog voltage immediately after it has completed D/A conversion. • Real-time output mode The converter outputs an analog voltage in synchronization with an output trigger after it has completed D/A conversion. Figure 7-8. Block Diagram of D/A Converter DACS0 8 2R ANO0 AVREF1 2R R Selector R 2R DACS1 2R 8 2R ANO1 2R R Selector R 2R AVSS 2R Data Sheet U14121EJ2V0DS00 43 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 7.7 Serial Interface Three independent serial interface channels are provided. • Asynchronous serial interface (UART)/3-wire serial I/O (IOE) × 2 • Clocked serial interface (CSI) × 1 • 3-wire serial I/O (IOE) • I2C bus interface (I2C) (µPD784216AY/784218AY Subseries only) Therefore, communication with an external system and local communication within the system can be simultaneously executed (refer to Figure 7-9). Figure 7-9. Example of Serial Interface (a) UART + I2C µPD784218AY (master) µ PD4711A [UART] RS-232-C driver/receiver RxD1 TxD1   Port  (b) VDD VDD µPD780078Y (slave) SDA SCL SDA0 SCL0 [I2C] µPD780308Y (slave) SDA LCD µ PD4711A [UART] RxD2 RS-232-C driver/receiver TxD2   Port  SCL (b) UART + 3-wire serial I/O µPD784218AY (master) µ PD4711A [UART] RxD2 RS-232-C driver/receiver TxD2    µ PD753106 (slave) [3-wire serial I/O] SI SO SCK Note Port INT SO1 SI1 SCK1 INTPm Port Port Note Handshake line 44 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) Two channels of serial interfaces for which an asynchronous serial interface mode and a 3-wire serial I/O mode can be selected are provided. (1) Asynchronous serial interface mode In this mode, data of 1 byte following the start bit is transmitted or received. Because an on-chip baud rate generator is provided, a wide range of baud rates can be set. Moreover, the clock input to the ASCK pin can be divided to define a baud rate. When the baud rate generator is used, a baud rate conforming to the MIDI standard (31.25 kbps) can also be obtained. Figure 7-10. Block Diagram in Asynchronous Serial Interface Mode Internal bus 8 Receive buffer register 1, 2 (RXB1, RXB2) 8 RxD1, RxD2 TxD1, TxD2 Receive control parity check Baud rate generator 5-bit counter × 2 transmit/ receive clock generation ASCK1, ASCK2 INTSR1, INTSR2 Transmit control parity addition INTST1, INTST2 Receive shift register 1, 2 (RX1, RX2) Transmit shift register 1, 2 (TXS1, TXS2) 8 Selector fXX to fXX/25 Data Sheet U14121EJ2V0DS00 45 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (2) 3-wire serial I/O mode In this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in synchronization with this clock. This mode is used to communicate with a device having a conventional clocked serial interface. Basically, communication is established by using three lines: serial clocks (SCK1 and SCK2), serial data inputs (SI1 and SI2), and serial data outputs (SO1 and SO2). necessary. Figure 7-11. Block Diagram in 3-Wire Serial I/O Mode To connect two or more devices, a handshake line is Internal bus 8 SI1, SI2 Serial I/O shift register 1, 2 (SIO1, SIO2) SO1, SO2 SCK1, SCK2 Serial clock counter Serial clock controller Interrupt generator INTCSI1, INTCSI2 TO2 fXX/8 fXX/16 Selector 46 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 7.7.2 Clocked serial interface (CSI) In this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in synchronization with this clock. (1) 3-wire serial I/O mode This mode is to communicate with devices having a conventional clocked serial interface. Basically, communication is established in this mode with three lines: serial clock (SCK0) serial data input (SI0), and serial data output (SO0) lines. Generally, a handshake line is necessary to check the reception status. Figure 7-12. Block Diagram in 3-Wire Serial I/O Mode Internal bus 8 SI0 Serial I/O shift register 0 (SIO0) SO0 SCK0 Serial clock counter Serial clock controller Interrupt generator INTCSI0 Selector TO2 fXX/8 fXX/16 Data Sheet U14121EJ2V0DS00 47 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (2) I2C bus (Inter IC) bus mode (supporting multimaster) (µPD784216AY/784218AY Subseries only) This mode is for communication with devices conforming to the I2C bus format. This mode is for transferring 8-bit data between two or more devices by using two lines: serial clock (SCL0) and serial data bus (SDA0) lines. During transmission, a “start condition”, “data”, and “stop condition” can be output onto the serial data bus. During reception, these data are automatically detected by hardware. Figure 7-13. Block Diagram of I2C Bus Mode Internal bus 8 Direction controller 8 SDA0 Serial I/O shift register 0 (SIO0) Output latch 8 Slave address register (SVA0) Wake-up controller Acknowledge generator Start condition/acknowledge detector Stop condition detector SCL0 Serial clock counter Serial clock controller TO2/18 to TO2/68 fXX/24 to fXX/178 Interrupt generator INTIIC0 Selector 48 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 7.8 Clock Output Function Clocks of the following frequencies can be output as clock output. • 97.7 kHz/195 kHz/391 kHz/781 kHz/1.56 MHz/3.13 MHz/6.25 MHz/12.5 MHz (@12.5 MHz operation with main system clock) • 32.768 kHz (@32.768 kHz operation with subsystem clock) Figure 7-14. Block Diagram of Clock Output Function fXX fXX/2 fXX/22 fXX/24 fXX/25 fXX/2 6 Selector fXX/23 Synchronization circuit Output controller PCL fXX/27 fXT 7.9 Buzzer Output Function Clocks of the following frequencies can be output as buzzer output. • 1.5 kHz/3.1 kHz/6.1 kHz/12.2 kHz (@12.5 MHz operation with main system clock) Figure 7-15. Block Diagram of Buzzer Output Function Selector fXX/210 fXX/211 fXX/212 fXX/213 Output controller BUZ Data Sheet U14121EJ2V0DS00 49 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 7.10 Edge Detection Function The interrupt input pins (INTP0, INTP1, NMI/INTP2, INTP3 to INTP6) are used not only to input interrupt requests but also to input trigger signals to the internal hardware units. Because these pins operate at an edge of the input signal, they have a function to detect an edge. Moreover, a noise elimination function is also provided to prevent erroneous detection due to noise. Pin Name NMI INTP0 to INTP6 Detectable Edge Either or both of rising and falling edges Noise Elimination By analog delay − 7.11 Watch Timer The watch timer has the following functions: • Watch timer • Interval timer The watch timer and interval timer functions can be used at the same time. (1) Watch timer The watch timer sets the WTIF flag of the interrupt control register (WTIC) at time intervals of 0.5 seconds by using the 32.768 kHz subsystem clock. (2) Interval timer The interval timer generates an interrupt request (INTTM3) at predetermined time intervals. Figure 7-16. Block Diagram of Watch Timer fW 214 Selector fW Prescaler fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 Selector fXX/27 fXT Selector 5-bit counter INTWT fW 25 Selector INTTM3 To 16-bit timer/counter 50 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 7.12 Watchdog Timer A watchdog timer is provided to detect a CPU runaway. This watchdog timer generates a non-maskable or maskable interrupt unless it is cleared by software within a specified interval time. Once enabled to operate, the watchdog timer cannot be stopped by software. Whether the interrupt by the watchdog timer or the interrupt input from the NMI pin takes precedence can be specified. Figure 7-17. Block Diagram of Watchdog Timer fCLK Timer fCLK/221 fCLK/220 RUNNote HALT IDLE STOP Selector fCLK/219 fCLK/217 INTWDT Note Write “+” to bit 7 (RUN) of the watchdog timer (WDM) Remark fCLK: Internal system clock (fXX to fXX/8) Data Sheet U14121EJ2V0DS00 51 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 8. INTERRUPT FUNCTIONS The three types of interrupt request servicing shown in Table 8-1 can be selected by program. Table 8-1. Servicing of Interrupt Request Servicing Mode Vectored interrupt Context switching Entity of Servicing Software Servicing Branches and executes servicing routine (servicing is arbitrary) Automatically switches register bank, branches and executes servicing routine (servicing is arbitrary) Firmware Executes data transfer between memory and I/O (servicing is fixed) Contents of PC and PSW Saves to and restores from stack Saves to or restores from fixed area in register bank Retained Macro service 8.1 Interrupt Sources Table 8-2 shows the interrupt sources available. As shown, interrupts are generated by 29 types of sources, execution of the BRK instruction, BRKCS instruction, or an operand error. The priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt servicing and so that which of the two or more interrupts that simultaneously occur should be serviced first can be determined. When the macro service function is used, however, nesting always proceeds. The default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having the same priority, are simultaneously generated (refer to Table 8-2). Table 8-2. Interrupt Sources (1/2) Type Default Priority − Source Name BRK instruction BRKCS instruction Operand error Trigger Instruction execution Instruction execution If result of exclusive OR between operands byte and byte is not FFH when “MOV STBC, #byte” instruction, “MOV WDM, #byte” instruction, or LOCATION instruction is executed Pin input edge detection Overflow of watchdog timer Overflow of watchdog timer Pin input edge detection External Internal Internal External √ − Internal/ External − Macro Service − Software Non-maskable − NMI INTWDT Maskable 0 (highest) 1 2 3 4 5 6 7 8 INTWDTM INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTIIC0 INTCSI0 End of I C bus transfer by CSI0 End of 3-wire transfer by CSI0 Occurrence of UART reception error in ASI1 2 Internal 9 INTSER1 52 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Table 8-2. Interrupt Sources (2/2) Type Default Priority 10 Source Name INTSR1 INTCSI1 11 12 13 INTST1 INTSER2 INTSR2 INTCSI2 14 15 16 17 18 19 20 21 22 23 24 25 26 (lowest) INTST2 INTTM3 INTTM00 INTTM01 INTTM1 INTTM2 INTAD INTTM5 INTTM6 INTTM7 INTTM8 INTWT INTKR Trigger End of UART reception by ASI1 End of 3-wire transfer by CSI1 End of UART transmission by ASI1 Occurrence of UART reception error in ASI2 End of UART reception by ASI2 End of 3-wire transfer by CSI2 End of UART transmission by ASI2 Reference time interval signal from watch timer Signal indicating match between 16-bit timer counter and capture/compare register (CR00) Signal indicating match between 16-bit timer counter and capture/compare register (CR01) Occurrence of match signal of 8-bit timer/event counter 1 Occurrence of match signal of 8-bit timer/event counter 2 End of conversion by A/D converter Occurrence of match signal of 8-bit timer/event counter 5 Occurrence of match signal of 8-bit timer/event counter 6 Occurrence of match signal of 8-bit timer/event counter 7 Occurrence of match signal of 8-bit timer/event counter 8 Overflow of watch timer Detection of falling edge of port 8 External Internal/ External Internal Macro Service √ Maskable Remarks 1. ASI: Asynchronous Serial Interface CSI: Clocked Serial Interface 2. There are two interrupt sources for the watchdog timer: non-maskable interrupts (INTWDT) and maskable interrupts (INTWDTM). Either one (but not both) should be selected for actual use. Data Sheet U14121EJ2V0DS00 53 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 8.2 Vectored Interrupt Execution branches to a servicing routine by using the memory contents of a vector table address corresponding to the interrupt source as the address of the branch destination. So that the CPU performs interrupt servicing, the following operations are performed: • On branching: Saves the status of the CPU (contents of PC and PSW) to stack • On returning: Restores the status of the CPU (contents of PC and PSW) from stack To return to the main routine from an interrupt service routine, the RETI instruction is used. The branch destination address is in a range of 0 to FFFFH. Table 8-3. Vector Table Address Interrupt Source BRK instruction TRAP0 (operand error) NMI INTWDT (non-maskable) INTWDTM (maskable) INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTIIC0 INTCSI0 INTSER1 INTSR1 INTCSI1 0018H 001AH Vector Table Address 003EH 003CH 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H Interrupt Source INTST1 INTSER2 INSR2 INTCSI2 INTST2 INTTM3 INTTM00 INTTM01 INTTM1 INTTM2 INTAD INTTM5 INTTM6 INTTM7 INTTM8 INTWT INTKR 0022H 0024H 0026H 0028H 002AH 002CH 002EH 0030H 0032H 0034H 0036H 0038H 003AH Vector Table Address 001CH 001EH 0020H 54 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 8.3 Context Switching When an interrupt request is generated or when the BRKCS instruction is executed, a predetermined register bank is selected by hardware. Context switching is a function that branches execution to a vector address stored in advance in the register bank, while at the same time stacking the current contents of the program counter (PC) and program status word (PSW) to the register bank. The branch address is in a range of 0 to FFFFH. Figure 8-1. Context Switching Operation When Interrupt Request Is Generated 0000B Transfer Register bank n (n = 0 to 7) PC19-16 PC15-0 A B Save (Bits 8 to 11 of temporary register) Exchange R5 R7 Save V U Temporary register Save T W D H VP UP E L X C R4 R6 Register bank (0 to 7) Switching of register bank (RBS0 to RBS2 ← n) RSS ← 0 IE ← 0 PSW Data Sheet U14121EJ2V0DS00 55 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 8.4 Macro Service This function is to transfer data between memory and a special function register (SFR) without intervention by the CPU. A macro service controller accesses the memory and SFR in the same transfer cycle and directly transfers data without loading it. Because this function does not save or restore the status of the CPU, or load data, data can be transferred at high speeds. Figure 8-2. Macro Service Read CPU Memory Write Macro service controller Write SFR Read Internal bus 56 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 8.5 Application Example of Macro Service (1) Serial interface transmission Transmit data storage buffer (memory) Data n Data n – 1 Data 2 Data 1 Internal bus TxD1, TxD2 Transmit shift register TXS1, TXS2 (SFR) Transmit control INTST1, INTST2 Each time macro service requests INTST1 and INTST2 are generated, the next transmit data is transferred from memory to TXS1 and TXS2. When data n (last byte) has been transferred to TXS1 and TXS2 (when the transmit data storage buffer has become empty), vectored interrupt requests INTST1 and INTST2 are generated. (2) Serial interface reception Receive data storage buffer (memory) Data n Data n – 1 Data 2 Data 1 Internal bus Receive buffer register RXB1, RXB2 (SFR) RxD1, RxD2 Receive shift register Receive control INTSR1, INTSR2 Each time macro service requests INTSR1 and INTSR2 are generated, the receive data is transferred from RXB1 and RXB2 to memory. When data n (last byte) has been transferred to memory (when the receive data storage buffer has become full), vectored interrupt requests INTSR1 and INTSR2 are generated. Data Sheet U14121EJ2V0DS00 57 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 9. LOCAL BUS INTERFACE The local bus interface can connect an external memory or I/O (memory mapped I/O) and support a memory space of 1 MB (refer to Figure 9-1). Figure 9-1. Example of Local Bus Interface (a) Multiplexed bus mode µ PD784218A VDD SRAM CS Data bus OE WE I/O1 to I/O8 Address bus A0 to A19 Address latch RD WR A8 to A19 ASTB LE Q0 to Q7 D0 to D7 OE AD0 to AD7 (b) Separate bus mode VDD µ PD784218A SRAM CS RD WR Address bus A0 to A19 OE WE I/O1 to I/O8 A0 to A19 Data bus AD0 to AD7 58 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 9.1 Memory Expansion External program memory and data memory can be connected in two stages: 256 KB and 1 MB. To connect the external memory, ports 4 through 6 and port 8 are used. The external memory can be connected in the following two modes: • Multiplexed bus mode: The external memory is connected by using a time-division address/data bus. The number of ports used when the external memory is connected can be reduced in this mode. • Separate bus mode: The external memory is connected by using an address bus and data bus independent of each other. Because an external latch circuit is not necessary, this mode is useful for reducing the number of components and mounting area on the printed wiring board. 9.2 Programmable Wait Wait state(s) can be inserted to the memory space (00000H to FFFFFH) while the RD and WR signals are active. In addition, there is an address wait function that extends the active period of the ASTB signal to gain the address decode time. Data Sheet U14121EJ2V0DS00 59 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 10. STANDBY FUNCTION This function is to reduce the power consumption of the chip, and can be used in the following modes: • HALT mode: Stops supply of the operating clock to the CPU. This mode is used in combination with the normal operation mode for intermittent operation to reduce the average power consumption. • IDLE mode: Stops the entire system except for the oscillator, which continues operating. The power consumption in this mode is close to that in the STOP mode. However, the time required to restore the normal program operation from this mode is almost the same as that from the HALT mode. • STOP mode: Stops the main system clock and thereby stops all the internal operations of the chip. • Low power consumption mode: Consequently, the power consumption is minimized with only leakage current flowing. The main system clock is stopped and the subsystem clock is used as the system clock. The CPU can operate on the subsystem clock to reduce the current consumption. • Low power consumption HALT mode: This is a standby function in the low power consumption mode and stops the operation clock of the CPU, to reduce the power consumption of the entire system. • Low power consumption IDLE mode: This is a standby function in the low power consumption mode and stops the entire system except the oscillator, to reduce the power consumption of the entire system. These modes are programmable. The macro service can be started from the HALT mode or low power consumption HALT mode. After macro service processing is executed, the system returns to the HALT mode again. The transition of the standby status is shown in Figure 10-1. 60 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Figure 10-1. Standby Function State Transitions Macro service On e-t Ma ime cro pro ce se ss r vi ing ce req en ue ds st t es qu s re end ice sing s rv se ces nd ro pro e e ac ime rvic M se e-t On cro a M Low power consumption Low Low power consumption HALT mode set Low power IDLE mode set Low power power consumption consumption NMI, INTP0 to INTP6 input, mode consumption Note 2 IDLE mode (Subsystem HALT mode INTWT, key return interrupt Interrupt requestNote 1 clock operation) (Standby) (Standby) Interrupt request for masked interrupt Low con pow sum er ptio Retu nm rn to ode norm set al o pera tion RE SE Ti t npu Interrupt request for masked interrupt NM ke I, I ID y r NT LE etu P0 se rn to t int IN er TP ru 6i pt No n te pu 2 t, I NT RESET inpu W t T , se ro ac M STOP (Standby) Interrupt request for masked interrupt IDLE (Standby) Interrupt request for masked interrupt Interrupt request for masked interrupt HALT (Standby) NM RE SE INT I, IN Ti TP WT np , k 0 to ut ey INT ret urn P6 i int npu err t, up N t ote RE S ET in pu t 2 Wait for stable oscillation Notes 1. Only unmasked interrupt requests 2. Only unmasked INTP0 to INTP6, INTWT, key return interrupt (P80 to P87) Remark NMI is valid only for an external input. The watchdog timer cannot be used for the release of standby (HALT mode/STOP mode/IDLE mode). On e- tim e pr O ST P se t rv ice re oc es que sin st g en ds ET ES R in pu t RE SE T in t pu Normal operation (Main system clock operation) Macro service request One-time processing ends Macro service ends Macro service Data Sheet U14121EJ2V0DS00 t es qu re t pt npu ru er ET i t Int S se RE ALT H 61 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 11. RESET FUNCTION When a low-level signal is input to the RESET pin, the system is reset, and each hardware unit is initialized (reset). During the reset period, oscillation of the main system clock is unconditionally stopped. Consequently, the current consumption of the entire system can be reduced. When the RESET signal goes high, the reset status is cleared. And after the oscillation stabilization time (84.0 ms at 12.5 MHz operation) elapses, the contents of the reset vector table are set to the program counter (PC), execution branches to an address set to the PC, and program execution is started from that branch address. Therefore, the program can be reset and started from any address. Figure 11-1. Oscillation of Main System Clock During Reset Period Main system clock oscillator Oscillation is unconditionally stopped during reset period fCLK RESET input Oscillation stabilization time The RESET input pin has an analog delay noise eliminator to prevent malfunctioning due to noise. Figure 11-2. Acknowledgement of Reset Signal Time until clock starts oscillating Analog delay Oscillation stabilization time Analog delay Analog delay RESET input Internal reset signal Internal clock 62 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 12. INSTRUCTION SET (1) 8-bit instructions (instructions in parentheses are combinations realized by describing A as r) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC Table 12-1. Instruction List by 8-Bit Addressing Second Operand #byte A r r' First Operand A (MOV) ADD Note 1 saddr saddr' sfr !addr16 !!addr24 mem [saddrp] [%saddrg] r3 PSWL PSWH MOV [WHL+] [WHL−] n None Note 2 (MOV) (XCH) (ADD) Note 1 MOV XCH (ADD) MOV XCH ADD Note 1 Note 1 (MOV) (XCH) (ADD) MOV XCH ADD Note 6 MOV (XCH) (ADD) MOV XCH ADD Note 1 Note 1 (MOV) (XCH) ADD Note 1 MOV XCH ADD Note 1 (MOV) (XCH) (ADD) Note 1 Note 6 Notes 1, 6 r MOV ADD Note 1 (MOV) (XCH) (ADD) Note 1 MOV XCH ROR Note 3 MULU DIVUW INC DEC Note 1 saddr MOV ADD Note 1 (MOV) (ADD) Note 6 MOV ADD Note 1 MOV XCH ADD Note 1 INC DEC DBNZ PUSH POP Note 1 sfr MOV ADD Note 1 MOV (ADD) Note 1 MOV ADD Note 1 !addr16 !!addr24 mem [saddrp] [%saddrg] mem3 MOV (MOV) ADD Note 1 MOV MOV ADD Note 1 ROR4 ROL4 r3 PSWL PSWH B, C STBC, WDM [TDE+] [TDE−] MOV MOV DBNZ MOV (MOV) (ADD) Note 6 MOVBK Note 5 Note 1 Note 4 MOVM Notes 1. The operands of ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as that of ADD. 2. Either the second operand is not used, or the second operand is not an operand address. 3. The operands of ROL, RORC, ROLC, SHR, and SHL are the same as that of ROR. 4. The operands of XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as that of MOVM. 5. The operands of XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as that of MOVBK. 6. The code length of some instructions having saddr2 as saddr in this combination is short. Data Sheet U14121EJ2V0DS00 63 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (2) 16-bit instructions (instructions in parentheses are combinations realized by describing AX as rp) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 12-2. Instruction List by 16-Bit Addressing Second Operand #word AX rp rp' First Operand AX (MOVW) ADDW Note 1 saddrp saddrp' sfrp !addr16 mem [WHL+] byte n None Note 2 !!addr24 [saddrp] [%saddrg] (MOVW) (XCHW) (ADD) Note 1 (MOVW) (XCHW) (ADDW) MOVW XCHW ADDW Note 1 Note 1 (MOVW) (XCHW) (ADDW) MOVW XCHW ADDW Note 3 MOVW (XCHW) (ADDW) MOVW XCHW ADDW Note 1 Note 1 (MOVW) MOVW XCHW XCHW (MOVW) (XCHW) Note 3 Notes 1, 3 rp MOVW ADDW Note 1 (MOVW) (XCHW) (ADDW) Note 1 MOVW SHRW SHLW MULU INCW Note 4 Note 1 DECW INCW DECW saddrp MOVW ADDW Note 1 (MOVW) (ADDW) Note 3 MOVW ADDW Note 1 MOVW XCHW ADDW Note 1 Note 1 sfrp MOVW ADDW Note 1 MOVW (ADDW) Note 1 MOVW ADDW Note 1 PUSH POP MOVTBLW !addr16 !!addr24 mem [saddrp] [%saddrg] PSW MOVW (MOVW) MOVW MOVW PUSH POP SP ADDWG SUBWG post PUSH POP PUSHU POPU [TDE+] byte (MOVW) SACW MACW MACSW Notes 1. The operands of SUBW and CMPW are the same as that of ADDW. 2. Either the second operand is not used, or the second operand is not an operand address. 3. The code length of some instructions having saddrp2 as saddrp in this combination is short. 4. The operands of MULUW and DIVUX are the same as that of MULW. 64 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (3) 24-bit instructions (instructions in parentheses are combinations realized by describing WHL as rg) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 12-3. Instruction List by 24-Bit Addressing Second Operand #imm24 WHL rg rg' First Operand WHL (MOVG) (ADDG) (SUBG) rg MOVG ADDG SUBG (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) ADDG SUBG MOVG MOVG INCG DECG PUSH POP saddrg !!addr24 mem1 [%saddrg] SP MOVG (MOVG) (MOVG) MOVG MOVG MOVG INCG DECG MOVG MOVG (MOVG) MOVG MOVG MOVG saddrg !!addr24 mem1 [%saddrg] SP None Note Note Either the second operand is not used, or the second operand is not an operand address. Data Sheet U14121EJ2V0DS00 65 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET Table 12-4. Instruction List by Bit Manipulation Instruction Addressing Second Operand CY saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit First Operand CY !addr16.bit !!addr24.bit MOV1 AND1 OR1 XOR1 saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit MOV1 NOT1 SET1 CLR1 BF BT BTCLR BFSET /saddr.bit /sfr. bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit AND1 OR1 NOT1 SET1 CLR1 None Note Note Either the second operand is not used, or the second operand is not an operand address. 66 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (5) Call and return/branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Table 12-5. Instruction List by Call and Return/Branch Instruction Addressing Operand of Instruction Address Basic instruction BC BR Note $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn None CALL BR CALL BR RETCS RETCSB CALL BR CALL BR CALL BR CALL BR CALL BR CALLF CALLF BRKCS BRK RET RETI RETB Compound instruction BF BT BTCLR BFSET DBNZ Note The operands of BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as that of BC. (6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS Data Sheet U14121EJ2V0DS00 67 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 13. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol VDD AVDD AVSS AVREF0 AVREF1 Input voltage VI1 VI2 Analog input voltage Output voltage Output current, low VAN VO IOL Per pin Total of P2, P4 to P8 Total of P0, P3, P9, P10, P12, P13 Total of all pins Output current, high IOH Per pin Total of all pins Operating ambient temperature Storage temperature TA A/D converter reference voltage input D/A converter reference voltage input Other than P90 to P95 P90 to P95 Analog input pin N-ch open drain Conditions Ratings −0.3 to +6.5 −0.3 to VDD + 0.3 −0.3 to VSS + 0.3 −0.3 to VDD + 0.3 −0.3 to VDD + 0.3 −0.3 to VDD + 0.3 −0.3 to +12 AVSS − 0.3 to AVREF0 + 0.3 −0.3 to VDD + 0.3 15 75 75 100 −10 −50 −40 to +85 −65 to +150 Unit V V V V V V V V V mA mA mA mA mA mA °C °C Tstg Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 68 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Operating Conditions • Operating ambient temperature (TA): −40 to +85°C • Power supply voltage and clock cycle time: See Figure 13-1 • Power supply voltage with subsystem clock operation: VDD = 1.8 to 5.5 V Figure 13-1. Power Supply Voltage and Clock Cycle Time (CPU Clock Frequency: fCPU) 10,000 8,000 500 Clock cycle time tCYK [ns] 400 Guaranteed operating range 320 300 200 160 100 80 0 0 1 1.8 2 2.7 3 Supply voltage [V] 4 4.5 5 5.5 6 Capacitance (TA = 25°C, VDD = VSS = 0 V) Parameter Input capacitance Symbol CI f = 1 MHz Unmeasured pins returned to 0 V. Conditions Other than Port 9 Port 9 Other than Port 9 Port 9 I/O capacitance CIO Other than Port 9 Port 9 MIN. TYP. MAX. 15 20 15 20 15 20 Unit pF pF pF pF pF pF Output capacitance CO Data Sheet U14121EJ2V0DS00 69 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Main System Clock Oscillator Characteristics (TA = −40 to +85°C) Resonator Ceramic resonator or crystal resonator Recommended Circuit X2 X1 VSS Parameter Oscillation frequency (fX) Conditions 4.5 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD < 4.5 V 2.0 V ≤ VDD < 2.7 V 1.8 V ≤ VDD < 2.0 V MIN. 2 2 2 2 TYP. MAX. 12.5 6.25 3.125 2 Unit MHz External clock X1 input frequency (fX) 4.5 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD < 4.5 V 2.0 V ≤ VDD < 2.7 V 2 2 2 2 15 12.5 6.25 3.125 2 250 MHz X2 X1 1.8 V ≤ VDD < 2.0 V X1 input high-/lowlevel width (tWXH, tWXL) X1 input rising/falling time (tXR, tXF) 4.5 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD < 4.5 V 2.0 V ≤ VDD < 2.7 V 1.8 V ≤ VDD < 2.0 V ns µ PD74HCU04 0 0 0 0 5 10 20 30 ns Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched back to the main system clock after the oscillation stabilization time is secured by the program. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 70 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Subsystem Clock Oscillator Characteristics (TA = −40 to +85°C) Resonator Crystal resonator Recommended Circuit VSS XT2 XT1 Parameter Oscillation frequency (fXT) Oscillation stabilization timeNote Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz 4.5 V ≤ VDD ≤ 5.5 V 1.8 V ≤ VDD < 4.5 V 1.2 2 10 s External clock XT2 XT1 XT1 input frequency (fXT) XT1 input high-/lowlevel width (tXTH, tXTL) 32 35 kHz µ PD74HCU04 14.3 15.6 µs Note Time required to stabilize oscillation after applying supply voltage (VDD). Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Data Sheet U14121EJ2V0DS00 71 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY DC Characteristics (TA = −40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) (1/3) Parameter Input voltage, low Symbol VIL1 Note 1 Conditions 2.2 V ≤ VDD ≤ 5.5 V 1.8 V ≤ VDD < 2.2 V VIL2 P00 to P06, P20, P22, P33, 2.2 V ≤ VDD ≤ 5.5 V P34, P70, P72, 1.8 V ≤ VDD < 2.2 V P100 to P103, RESET P90 to P95 (N-ch open drain) P10 to P17, P130, P131 2.2 V ≤ VDD ≤ 5.5 V 1.8 V ≤ VDD < 2.2 V 2.2 V ≤ VDD ≤ 5.5 V 1.8 V ≤ VDD < 2.2 V VIL5 X1, X2, XT1, XT2 2.2 V ≤ VDD ≤ 5.5 V 1.8 V ≤ VDD < 2.2 V VIL6 P25, P27 2.2 V ≤ VDD ≤ 5.5 V 1.8 V ≤ VDD < 2.2 V Input voltage, high VIH1 Note 1 2.2 V ≤ VDD ≤ 5.5 V 1.8 V ≤ VDD < 2.2 V VIH2 P00 to P06, P20, P22, P33, 2.2 V ≤ VDD ≤ 5.5 V P34, P70, P72, 1.8 V ≤ VDD < 2.2 V P100 to P103, RESET P90 to P95 (N-ch open drain) P10 to P17, P130, P131 2.2 V ≤ VDD ≤ 5.5 V 1.8 V ≤ VDD < 2.2 V 2.2 V ≤ VDD ≤ 5.5 V 1.8 V ≤ VDD < 2.2 V VIH5 X1, X2, XT1, XT2 2.2 V ≤ VDD ≤ 5.5 V 1.8 V ≤ VDD < 2.2 V VIH6 P25, P27 2.2 V ≤ VDD ≤ 5.5 V 1.8 V ≤ VDD < 2.2 V Output voltage, low VOL1 For pins other than P40 to P47, P50 to P57, Note 1 P90 to P95 IOL = 1.6 mA P40 to P47, P50 to P57 Note 2 IOL = 8 mA P90 to P95 IOL = 15 mA VOL2 Output voltage, high VOH1 IOL = 400 µA IOH = −1 mA Note 2 Note 2 Note 2 MIN. 0 0 0 0 0 0 0 0 0 0 0 0 0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD 0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD TYP. MAX. 0.3VDD 0.2VDD 0.2VDD 0.15VDD 0.3VDD 0.2VDD 0.3VDD 0.2VDD 0.2VDD 0.1VDD 0.3VDD 0.2VDD VDD VDD VDD VDD 12 VDD VDD VDD VDD VDD VDD VDD 0.4 Unit V V VIL3 V VIL4 V V V V V VIH3 V VIH4 V V V 4.5 V ≤ VDD ≤ 5.5 V V 4.5 V ≤ VDD ≤ 5.5 V 4.5 V ≤ VDD ≤ 5.5 V 4.5 V ≤ VDD ≤ 5.5 V VDD − 1.0 VDD − 0.5 Except X1, X2, XT1, XT2 X1, X2, XT1, XT2 0.8 1.0 2.0 0.5 V V V V V IOL = −100 µA Input leakage current, low ILIL1 ILIL2 Input leakage current, high ILIH1 ILIH2 ILIH3 Output leakage current, low Output leakage current, high ILOL1 ILOH1 VIN = VDD VIN = 0 V Note 2 −3 −20 3 20 20 −3 3 µA µA µA µA µA µA µA Except X1, X2, XT1, XT2 X1, X2, XT1, XT2 VIN = 12 V (N-ch open drain) P90 to P95 VOUT = 0 V VOUT = VDD Notes 1. P21, P23, P24, P26, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P60 to P67, P71, P80 to P87, P120 to P127 2. Per pin 72 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY DC Characteristics (TA = −40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) (2/3) (1) µPD784214A, 784215A, 784216A, 784214AY, 784215AY, 784216AY Parameter Supply current Symbol IDD1 Operation mode Conditions fXX = 12.5 MHz, VDD = 5.0 V ±10% fXX = 6 MHz, VDD = 3.0 V ±10% fXX = 2 MHz, VDD = 2.0 V ±10% IDD2 HALT mode fXX = 12.5 MHz, VDD = 5.0 V ±10% fXX = 6 MHz, VDD = 3.0 V ±10% fXX = 2 MHz, VDD = 2.0 V ±10% IDD3 IDLE mode fXX = 12.5 MHz, VDD = 5.0 V ±10% fXX = 6 MHz, VDD = 3.0 V ±10% fXX = 2 MHz, VDD = 2.0 V ±10% IDD4 Operation modeNote fXX = 32 kHz, VDD = 5.0 V ±10% fXX = 32 kHz, VDD = 3.0 V ±10% fXX = 32 kHz, VDD = 2.0 V ±10% IDD5 HALT modeNote fXX = 32 kHz, VDD = 5.0 V ±10% fXX = 32 kHz, VDD = 3.0 V ±10% fXX = 32 kHz, VDD = 2.0 V ±10% IDD6 IDLE modeNote fXX = 32 kHz, VDD = 5.0 V ±10% fXX = 32 kHz, VDD = 3.0 V ±10% fXX = 32 kHz, VDD = 2.0 V ±10% Data retention voltage Data retention current VDDDR IDDDR HALT, IDLE modes STOP mode VDD = 2.0 V ±10% VDD = 5.0 V ±10% Pull-up resistor RL VIN = 0 V 10 1.8 2 10 30 MIN. TYP. 11 3 1 5 2 0.3 1 0.4 0.2 80 60 30 60 20 10 50 15 5 MAX. 40 17 8 20 8 3.5 2.5 1.3 0.9 200 110 100 160 80 70 150 70 60 5.5 10 50 100 Unit mA mA mA mA mA mA mA mA mA µA µA µA µA µA µA µA µA µA V µA µA kΩ Note When main system clock is stopped and subsystem clock is operating. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U14121EJ2V0DS00 73 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY DC Characteristics (TA = −40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) (3/3) (2) µPD784217A, 784218A, 784217AY, 784218AY Parameter Supply current Symbol IDD1 Operation mode Conditions fXX = 12.5 MHz, VDD = 5.0 V ±10% fXX = 6 MHz, VDD = 3.0 V ±10% fXX = 2 MHz, VDD = 2.0 V ±10% IDD2 HALT mode fXX = 12.5 MHz, VDD = 5.0 V ±10% fXX = 6 MHz, VDD = 3.0 V ±10% fXX = 2 MHz, VDD = 2.0 V ±10% IDD3 IDLE mode fXX = 12.5 MHz, VDD = 5.0 V ±10% fXX = 6 MHz, VDD = 3.0 V ±10% fXX = 2 MHz, VDD = 2.0 V ±10% IDD4 Operation modeNote fXX = 32 kHz, VDD = 5.0 V ±10% fXX = 32 kHz, VDD = 3.0 V ±10% fXX = 32 kHz, VDD = 2.0 V ±10% IDD5 HALT modeNote fXX = 32 kHz, VDD = 5.0 V ±10% fXX = 32 kHz, VDD = 3.0 V ±10% fXX = 32 kHz, VDD = 2.0 V ±10% IDD6 IDLE modeNote fXX = 32 kHz, VDD = 5.0 V ±10% fXX = 32 kHz, VDD = 3.0 V ±10% fXX = 32 kHz, VDD = 2.0 V ±10% Data retention voltage Data retention current VDDDR IDDDR HALT, IDLE modes STOP mode VDD = 2.0 V ±10% VDD = 5.0 V ±10% Pull-up resistor RL VIN = 0 V 10 1.8 2 10 30 MIN. TYP. 11 4 1 6 2 0.4 1 0.4 0.2 80 60 30 60 20 10 50 15 5 MAX. 40 17 8 20 8 3.5 2.5 1.3 0.9 200 110 100 160 80 70 150 70 60 5.5 10 50 100 Unit mA mA mA mA mA mA mA mA mA µA µA µA µA µA µA µA µA µA V µA µA kΩ Note When main system clock is stopped and subsystem clock is operating. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 74 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY AC Characteristics (TA = −40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) (1) Read/write operation (1/2) Parameter Cycle time Symbol tCYK Conditions 4.5 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD < 4.5 V 2.0 V ≤ VDD < 2.7 V 1.8 V ≤ VDD < 2.0 V Address setup time (to ASTB↓) tSAST VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Address hold time (from ASTB↓) tHSTLA VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% ASTB high-level width tWSTH VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Address hold time (from RD↑) tHRA VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Delay time from address to RD↓ tDAR VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Address float time (from RD↓) tFAR VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Data input time from address tDAID VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Data input time from ASTB↓ tDSTID VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Data input time from RD↓ tDRID VDD = 5.0 V ±10% VDD = 3.0 V ±10% MIN. 80 160 320 500 (0.5 + a)T − 20 (0.5 + a)T − 40 (0.5 + a)T − 80 0.5T − 19 0.5T − 24 0.5T − 34 (0.5 + a)T − 17 (0.5 + a)T − 40 (0.5 + a)T − 110 0.5T − 14 0.5T − 14 0.5T − 14 (1 + a)T − 24 (1 + a)T − 35 (1 + a)T − 80 0 0 0 (2.5 + a + n)T − 37 (2.5 + a + n)T − 52 (2.5 + a + n)T − 120 (2 + n)T − 35 (2 + n)T − 50 (2 + n)T − 80 (1.5 + n)T − 40 (1.5 + n)T − 50 (1.5 + n)T − 90 0.5T − 9 0.5T − 9 0.5T − 20 0 0 0 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VDD = 2.0 V ±10% Delay time from ASTB↓ to RD↓ tDSTR VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Data hold time (from RD↑) tHRID VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Remark T: tCYK = 1/fXX (fXX: main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of waits (n ≥ 0) Data Sheet U14121EJ2V0DS00 75 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY AC Characteristics (1) Read/write operation (2/2) Parameter Address active time from RD↑ Symbol tDRA Conditions VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Delay time from RD↑ to ASTB↑ tDRST VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% RD low-level width tWRL VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Delay time from address to WR↓ tDAW VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Address hold time (from WR↑) tHRD VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Delay time from ASTB↓ to data tDSTOD output VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Delay time from WR↓ to data tDWOD output VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Delay time from ASTB↓ to WR↓ tDSTW VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Data setup time (to WR↑) tSODWR VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Data hold time (from WR↑) tHWOD VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Delay time from WR↑ to ASTB↑ tDWST VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% WR low-level width tWWL VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% 0.5T − 9 0.5T − 9 0.5T − 20 (1.5 + n)T − 20 (1.5 + n)T − 25 (1.5 + n)T − 70 0.5T − 14 0.5T − 14 0.5T − 50 0.5T − 9 0.5T − 9 0.5T − 30 (1.5 + n)T − 25 (1.5 + n)T − 30 (1.5 + n)T − 30 MIN. 0.5T − 2 0.5T − 12 0.5T − 35 0.5T − 9 0.5T − 9 0.5T − 40 (1.5 + n)T − 25 (1.5 + n)T − 30 (1.5 + n)T − 25 (1 + a)T − 24 (1 + a)T − 34 (1 + a)T − 70 0.5T − 14 0.5T − 14 0.5T − 14 0.5T + 15 0.5T + 30 0.5T + 240 0.5T − 30 0.5T − 30 0.5T − 30 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remark T: tCYK = 1/fXX (fXX: main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n ≥ 0) 76 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY AC Characteristics (2) External wait timing Parameter Input time from address to WAIT↓ Input time from ASTB↓ to WAIT↓ Hold time from ASTB↓ to WAIT Symbol tDAWT Conditions VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% tDSTWT VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% tHSTWT VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Delay time from ASTB↓ to WAIT↑ Input time from RD↓ to WAIT↓ tDRWTL tDSTWTH VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Hold time from RD↓ to WAIT↓ tHRWT VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Delay time from RD↓ to WAIT↑ tDRWTH VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Data input time from WAIT↑ tDWTID VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Delay time from WAIT↑ to RD↑ tDWTR VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Delay time from WAIT↑ to WR↑ tDWTW VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Input time from WR↓ to WAIT↓ tDWWTL VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Hold time from WR↓ to WAIT tHWWT VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% Delay time from WR↓ to WAIT↑ tDWWTH VDD = 5.0 V ±10% VDD = 3.0 V ±10% VDD = 2.0 V ±10% nT + 5 nT + 10 nT + 30 (1 + n)T − 40 (1 + n)T − 60 (1 + n)T − 90 0.5T 0.5T 0.5T + 5 0.5T 0.5T 0.5T + 5 T − 40 T − 60 T − 90 nT + 5 nT + 10 nT + 30 (1 + n)T − 40 (1 + n)T − 60 (1 + n)T − 90 0.5T − 5 0.5T − 10 0.5T − 30 (0.5 + n)T + 5 (0.5 + n)T + 10 (0.5 + n)T + 30 (1.5 + n)T − 40 (1.5 + n)T − 60 (1.5 + n)T − 90 T − 40 T − 60 T − 70 MIN. TYP. MAX. (2 + a)T − 40 (2 + a)T − 60 (2 + a)T − 300 1.5T − 40 1.5T − 60 1.5T − 260 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remark T: tCYK = 1/fXX (fXX: main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n ≥ 0) Data Sheet U14121EJ2V0DS00 77 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Serial Operation (TA = −40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) (a) 3-wire serial I/O mode (SCK: Internal clock output) Parameter SCK cycle time Symbol tKCY1 2.7 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD ≤ 5.5 V Conditions MIN. 800 3,200 SCK high-/low-level width SI setup time (to SCK↑) SI hold time (from SCK↑) SO output delay time (from SCK↓) tKH1, tKL1 tSIK1 350 1,500 10 30 tKSI1 tKSO1 40 30 TYP. MAX. Unit ns ns ns ns ns ns ns ns (b) 3-wire serial I/O mode (SCK: External clock input) Parameter SCK cycle time Symbol tKCY2 2.7 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD ≤ 5.5 V Conditions MIN. 800 3,200 SCK high-/low-level width SI setup time (to SCK↑) SI hold time (from SCK↑) SO output delay time (from SCK↓) tKH2 tKL2 tSIK2 400 1,600 10 30 tKSI2 tKSO2 40 30 TYP. MAX. Unit ns ns ns ns ns ns ns ns (c) UART mode Parameter ASCK cycle time Symbol tKCY3 4.5 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD < 4.5 V 4.5 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD < 4.5 V Conditions MIN. 417 833 1,667 ASCK high-/low-level width tKH3 tKL3 208 416 833 TYP. MAX. Unit ns ns ns ns ns ns 78 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (d) I2C bus mode Parameter Symbol MIN. Standard Mode MAX. 100 − − − − − − − − 1,000 High-Speed Mode MIN. 0 1.3 MAX. 400 − − − − − − 0.9Note 3 − 300 Unit SCL0 clock frequency Bus free time (between stop and start conditions) Hold timeNote1 Low-level width of SCL0 clock High-level width of SCL0 clock Setup time of start/restart conditions Data hold When using CBUStime compatible master When using I C bus Data setup time Rise time of SDA0 and SCL0 signals Fall time of SDA0 and SCL0 signals Setup time of stop condition Pulse width of spike restricted by input filter Load capacitance of each bus line 2 fCLK tBUF 0 4.7 kHz µs µs µs µs µs µs µs ns ns tHD : STA tLOW tHIGH tSU : STA 4.0 4.7 4.0 4.7 0.6 1.3 0.6 0.6 − 0Note 2 100 Note 4 Note 5 tHD : DAT 5.0 0Note 2 tSU : DAT tR 250 − − 20 + 0.1Cb tF 300 − − 20 + 0.1CbNote 5 300 − 50 ns tSU : STO tSP 4.0 − − 0.6 0 − µs ns Cb 400 400 pF Notes 1. For the start condition, the first clock pulse is generated after the hold time. 2. To fill the undefined area of the SCL0 falling edge, it is necessary for the device to provide an internal SDA0 signal (on VIHmin.) with at least 300 ns of hold time. 3. If the device does not extend the SCL0 signal low-level hold time (tLOW), only the maximum data hold time tHD : DAT needs to be satisfied. 4. The high-speed mode I2C bus can be used in a standard mode I2C bus system. In this case, the conditions described below must be satisfied. • If the device does not extend the SCL0 signal low-level hold time tSU : DAT ≥ 250 ns • If the device extends the SCL0 signal low-level hold time Be sure to transmit the data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU : = 1,000 + 250 = 1,250 ns by standard mode I2C bus specification) 5. Cb: Total capacitance per bus line (unit: pF) DAT Data Sheet U14121EJ2V0DS00 79 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Other Operations (TA = −40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) Parameter NMI high-/low-level width Symbol tWNIL tWNIH tWITL tWITH tWRSL tWRSH INTP0 to INTP6 Conditions MIN. 10 TYP. MAX. Unit µs ns INTP input high-/low-level width 100 RESET high-/low-level width 10 µs Clock Output Operation (TA = −40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) Parameter PCL cycle time PCL high-/low-level width Symbol tCYCL tCLL tCLH tCLR tCLF Conditions 4.5 V ≤ VDD ≤ 5.5 V, nT 4.5 V ≤ VDD ≤ 5.5 V, 0.5T − 10 4.5 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD < 4.5 V 1.8 V ≤ VDD < 2.7 V MIN. 80 30 TYP. MAX. 31,250 15,615 Unit ns ns PCL rise/fall time 5 10 20 ns ns ns Remark T: tCYK = 1/fXX (fXX: Main system clock frequency) n: Divided frequency ratio set by software in the CPU • When using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128 • When using the subsystem clock: n = 1 80 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY A/D Converter Characteristics (TA = −40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) Parameter Resolution Overall error Notes 1, 2 Symbol Conditions MIN. 8 TYP. 8 MAX. 8 ±1.2 ±1.6 Unit bits %FSR 2.7 V ≤ VDD ≤ 5.5 V 2.2 V ≤ AVREF0 ≤ VDD 1.8 V ≤ VDD < 2.7 V 1.8 V ≤ AVREF0 ≤ VDD %FSR Conversion time Sampling time Analog input voltage Reference voltage Resistance between AVREF0 and AVSS tCONV tSAMP VIAN AVREF0 RAVREF0 When not A/D converting 14 24/fXX AVSS 1.8 40 144 µs µs AVREF0 AVDD V V kΩ Notes 1. Quantization error (±1/2 LSB) is not included. 2. Overall error is indicated as a ratio to the full-scale value. Remark fXX : Main system clock frequency D/A Converter Characteristics (TA = −40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) Parameter Resolution Overall error Notes 1, 2 Symbol Conditions MIN. 8 TYP. 8 MAX. 8 ±0.6 ±1.2 Unit Bits %FSR R = 10 MΩ, 2.0 V ≤ AVREF1 ≤ VDD, 2.0 V ≤ VDD ≤ 5.5 V R = 10 MΩ, 1.8 V ≤ AVREF1 ≤ VDD, 1.8 V ≤ VDD ≤ 2.0 V %FSR Settling time Load conditions: C = 30 pF 4.5 V ≤ AVREF1 ≤ 5.5 V 2.7 V ≤ AVREF1 < 4.5 V 1.8 V ≤ AVREF1 < 2.7 V 10 15 20 8 1.8 VDD 2.5 µs µs µs kΩ V mA Output resistance Reference voltage AVREF1 current RO AVREF1 AIREF1 DACS0, 1 = 55H For only 1 channel Notes 1. Quantization error (±1/2 LSB) is not included. 2. Overall error is indicated as a ratio to the full-scale value. Data Sheet U14121EJ2V0DS00 81 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Data Retention Characteristics (TA = −40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR STOP mode VDDDR = 5.0 V ±10% VDDDR = 2.0 V ±10% VDD rise time VDD fall time VDD hold time (from STOP mode setting) STOP release signal input time Oscillation stabilization wait time tRVD tFVD tHVD 200 200 0 Conditions MIN. 1.8 10 2 TYP. MAX. 5.5 50 10 Unit V µA µA µs µs ms tDREL tWAIT Crystal resonator Ceramic resonator 0 30 5 0 0.9VDDDR 0.1VDDDR VDDDR ms ms ms V V Low-level input voltage High-level input voltage VIL VIH RESET, P00/INTP0 to P06/INTP6 AC Timing Test Points VDD − 1 V 0.8VDD or 1.8 V Test points 0.8 V 0.8VDD or 1.8 V 0.8 V 0.45 V 82 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Timing Waveforms (1) Read operations (CLK) tCYK A0 to A7 (Output) Lower address Lower address A8 to A19 (Output) tDAID Higher address tHRA tDRA Hi-Z Data (Input) tHRID tFAR Hi-Z Higher address tDSTID AD0 to AD7 (Input/output) Hi-Z Lower address (Output) tSAST ASTB (Output) tHSTLA Lower address (Output) tWSTH tDSTR tDAR tDRID tWRL tDRWTL tDAWT tDRWTH tHRWT tDWTR tDWTID tDRST RD (Output) WAIT (Input) tDSTWT tDSTWTH tHSTWT Remark The signal is output from pins A0 to A7 when P80 to P87 are unused. Data Sheet U14121EJ2V0DS00 83 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (2) Write operation (CLK) tCYK A0 to A7 (Output) Lower address Lower address A8 to A19 (Output) tDAID Higher address tHWA tDAW Hi-Z Data (Output) tHWOD tFAR tSODWR Hi-Z Higher address tDSTOD AD0 to AD7 (Output) Hi-Z Lower address (Output) tSAST ASTB (Output) tHSTLA Lower address (Output) tWSTH tDSTW tDAW tDWOD tWWL tDWWTL tDAWT tDWWTH tHWWT tDWTW tDWTID tDWST WR (Output) WAIT (Input) tDSTWT tDSTWTH tHSTWT Remark The signal is output from pins A0 to A7 when P80 to P87 are unused. 84 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Serial Operation (1) 3-wire serial I/O mode tKCY1, 2 tKH1, 2 tKL1, 2 SCK tKSO1, 2 tKSI1, 2 tSIK1, 2 SI/SO (2) UART mode tKCY3 tKH3 ASCK tKL3 (3) I2C bus mode (µPD784216AY/784218AY Subseries only) tR SCL0 tHD : DAT tHD : STA tF tHIGH tSU : DAT tSU : STA tHD : STA tSP tSU : STO SDA0 tBUF Stop condition Start condition Restart condition Stop condition Data Sheet U14121EJ2V0DS00 85 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Clock Output Timing tCLH tCLL CLKOUT tCLR tCYCL tCLF Interrupt Input Timing tWNIH tWNIL NMI tWITH tWITL INTP0 to INTP6 Reset Input Timing tWRSH tWRSL RESET 86 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Clock Timing tWXH tWXL X1 tXR 1/fX tXF tXTH tXTL XT1 1/fXT Data Retention Characteristics STOP mode setting VDD tHVD tFVD VDDDR tRVD tDREL tWAIT RESET NMI (Cleared by falling edge) NMI (Cleared by rising edge) Data Sheet U14121EJ2V0DS00 87 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 14. PACKAGE DRAWINGS 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) A B 75 76 51 50 detail of lead end S CD Q R 100 1 26 25 F G P H I M J K S N S L M NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 16.00 ± 0.20 14.00 ± 0.20 14.00 ± 0.20 16.00 ± 0.20 1.00 1.00 0.22 + 0.05 − 0.04 0.08 0.50 (T.P.) 1.00 ± 0.20 0.50 ± 0.20 0.17 + 0.03 − 0.07 0.08 1.40 ± 0.05 0.10 ± 0.05 +7° 3°−3° 1.60 MAX. S100GC-50-8EU, 8EA-2 Remark The external dimensions and material of the ES version are the same as those of the mass-produced version. 88 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 100-PIN PLASTIC QFP (14x20) A B 80 81 51 50 detail of lead end S CD Q R 100 1 31 30 F G H I M J P K S N S L M NOTE Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.6 ± 0.4 20.0 ± 0.2 14.0 ± 0.2 17.6 ± 0.4 0.8 0.6 0.30 ± 0.10 0.15 0.65 (T.P.) 1.8 ± 0.2 0.8 ± 0.2 0.15+ 0.10 − 0.05 0.10 2.7 ± 0.1 0.1 ± 0.1 5 °± 5 ° 3.0 MAX. P100GF-65-3BA1-4 Remark The external dimensions and material of the ES version are the same as those of the mass-produced version. Data Sheet U14121EJ2V0DS00 89 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 15. RECOMMENDED SOLDERING CONDITIONS The µPD784218A should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 15-1. Surface Mounting Type Soldering Conditions (1/2) (1) µPD784214AGC-×××-8EU:100-pin plastic LQFP(fine pitch) (14 × 14 mm) µPD784215AGC-×××-8EU:100-pin plastic LQFP(fine pitch) (14 × 14 mm) µPD784216AGC-×××-8EU:100-pin plastic LQFP(fine pitch) (14 × 14 mm) µPD784217AGC-×××-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD784218AGC-×××-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD784214AYGC-×××-8EU:100-pin plastic LQFP(fine pitch) (14 × 14 mm) µPD784215AYGC-×××-8EU:100-pin plastic LQFP(fine pitch) (14 × 14 mm) µPD784216AYGC-×××-8EU:100-pin plastic LQFP(fine pitch) (14 × 14 mm) µPD784217AYGC-×××-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD784218AYGC-×××-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm) Soldering Method Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Note Count: Two times or less, Exposure limit: 7 days (after that, prebake at 125°C for 10 hours) VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Note Count: Two times or less, Exposure limit: 7 days (after that, prebake at 125°C for 10 hours) Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) − VP15-107-2 Recommended Condition Symbol IR35-107-2 Infrared reflow Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). 90 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Table 15-1. Surface Mounting Type Soldering Conditions (2/2) (2) µPD784214AGF-×××-3BA:100-pin plastic QFP(14 × 20 mm) µPD784215AGF-×××-3BA:100-pin plastic QFP(14 × 20 mm) µPD784216AGF-×××-3BA:100-pin plastic QFP(14 × 20 mm) µPD784217AGF-×××-3BA: 100-pin plastic QFP (14 × 20 mm) µPD784218AGF-×××-3BA: 100-pin plastic QFP (14 × 20 mm) µPD784214AYGF-×××-3BA:100-pin plastic QFP(14 × 20 mm) µPD784215AYGF-×××-3BA:100-pin plastic QFP(14 × 20 mm) µPD784216AYGF-×××-3BA:100-pin plastic QFP(14 × 20 mm) µPD784217AYGF-×××-3BA: 100-pin plastic QFP (14 × 20 mm) µPD784218AYGF-×××-3BA: 100-pin plastic QFP (14 × 20 mm) Soldering Method Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: Two times or less Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Count: Two times or less Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120°C max. (package surface temperature) Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) Recommended Condition Symbol IR35-00-2 Infrared reflow VPS VP15-00-2 Wave soldering WS60-00-1 − Partial heating Caution Do not use different soldering methods together (except for partial heating). Data Sheet U14121EJ2V0DS00 91 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using the µPD784218A. Also refer to (5) Cautions on using development tools. (1) Language processing software RA78K4 CC78K4 DF784218 CC78K4-L Assembler package common to 78K/IV Series C compiler package common to 78K/IV Series Device file common to µPD784216A, 784216AY, 784218A, 784218AY Subseries C compiler library source file common to 78K/IV Series (2) Flash memory writing tools Dedicated flash programmer for microcontroller incorporating flash memory Flashpro II (Model number: FL-PR2), Flashpro III (Model number: FL-PR3, PG-FP3) FA-100GF FA-100GC Flashpro II controller, Flashpro III controller Adapter for writing 100-pin plastic QFP (GF-3BA type) flash memory. Connection must be performed in accordance with the target product. Adapter for writing 100-pin plastic LQFP (GC-8EU type) flash memory. Connection must be performed in accordance with the target product. Control program that runs on a personal computer and is attached to Flashpro II, Flashpro III. TM Operates on Windows 95, etc. (3) Debugging tools • When IE-78K4-NS in-circuit emulator is used IE-78K4-NS IE-70000-MC-PS-B IE-70000-98-IF-C IE-70000-CD-IF-A IE-70000-PC-IF-C IE-70000-PCI-IF IE-784225-NS-EM1 NP-100GF NP-100GC EV-9200GF-100 TGC-100SDW ID78K4-NS SM78K4 DF784218 In-circuit emulator common to 78K/IV Series Power supply unit for IE-78K4-NS Interface adapter required when PC-9800 series PC (except notebook type) is used as host machine (C bus supported) PC card and cable when PC-9800 series notebook PC is used as host machine (PCMCIA socket supported) Interface adapter required when using IBM PC/AT supported) TM compatibles as host machine (ISA bus Interface adapter required when using PC that incorporates PCI bus as host machine Emulation board to emulate µPD784216A, 784216AY, 784218A, 784218AY Subseries Emulation probe for 100-pin plastic QFP (GF-3BA type) Emulation probe for 100-pin plastic LQFP (GC-8EU type) Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) Conversion adapter to connect the NP-100GC and a target system board on which a 100-pin plastic LQFP (GC-8EU type) can be mounted Integrated debugger for IE-78K4-NS System simulator common to 78K/IV Series Device file common to µPD784216A, 784216AY, 784218A, 784218AY Subseries 92 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY • When IE-784000-R in-circuit emulator is used IE-784000-R IE-70000-98-IF-C IE-70000-PC-IF-C IE-70000-PCI-IF IE-78000-R-SV3 IE-784225-NS-EM1 IE-784000-R-EM IE-78K4-R-EX3 EP-784218GF-R EP-78064GC-R EV-9200GF-100 TGC-100SDW ID78K4 SM78K4 DF784218 In-circuit emulator common to 78K/IV Series Interface adapter required when PC-9800 series PC (except notebook type) is used as host machine (C bus supported) Interface adapter required when using IBM PC/AT and compatibles as host machine (ISA bus supported) Interface adapter required when using PC that incorporates PCI bus as host machine Interface adapter and cable required when EWS is used as host machine Emulation board to emulate µPD784216A, 784216AY, 784218A, 784218AY Subseries Emulation board common to 78K/IV Series Emulation probe conversion board required when using IE-784225-NS-EM1 on IE-784000-R. Emulation probe for 100-pin plastic QFP (GF-3BA type) Emulation probe for 100-pin plastic LQFP (GC-8EU type) Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) Conversion adapter to connect the EP-78064GC-R and a target system board on which a 100-pin plastic LQFP (GC-8EU type) can be mounted Integrated debugger for IE-784000-R System simulator common to 78K/IV Series Device file common to µPD784216A, 784216AY, 784218A, 784218AY Subseries (4) Real-time OS RX78K/IV MX78K4 Real-time OS for 78K/IV Series OS for 78K/IV Series Data Sheet U14121EJ2V0DS00 93 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (5) Cautions on using development tools • The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784218. • The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784218. • The FL-PR2, FL-PR3, FA-100GF, FA-100GC, NP-100GF, and NP-100GC are products made by Naito Densei Machida Mfg. Co., Ltd. (TEL: +81-44-822-3813). • The TGC-100SDW is a product made by TOKYO ELETECH CORPORATION. For further information, contact Daimaru Kogyo, Ltd. Tokyo Electronic Division (TEL: +81-3-3820-7112) Osaka Electronic Division (TEL: +81-6-6244-6672) • For third party development tools, see the Single-Chip Microcontroller Development Tool Selection Guide (U11069E). • The host machine and OS suitable for each software are as follows: Host Machine [OS] Software RA78K4 CC78K4 ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4 √ PC PC-9800 series [Windows] IBM PC/AT and compatibles [Japanese/English Windows] √Note √ Note EWS HP9000 Series 700 [HP-UX ] TM TM TM SPARCstation [SunOS , Solaris ] TM TM NEWS (RISC) [NEWS-OS ] √ √ − √ − √ √ TM TM √ √ √ Note √Note Note DOS-based software 94 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY APPENDIX B. RELATED DOCUMENTS Documents related to devices Document Name Document No. English Japanese U14121J µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Data Sheet µPD78F4216A, 78F4216AY, 78F4218A, 78F4218AY Data Sheet µPD784216A, 784216AY Subseries User’s Manual Hardware µPD784218A, 784218AY Subseries User’s Manual Hardware 78K/IV Series User’s Manual Instructions 78K/IV Series Instruction Table 78K/IV Series Instruction Set 78K/IV Series Application Note Software Basics This document To be prepared U13570E U12970E U10905E − − − To be prepared U13570J U12970J U10905J U10594J U10595J U10095J Documents related to development tools (user’s manuals) Document Name Document No. English RA78K4 Assembler Package Language Operation RA78K Structured Assembler Preprocessor CC78K4 C Compiler Language Operation IE-78K4-NS IE-784000-R IE-784218-R-EM1 IE-784225-NS-EM1 EP-78064 SM78K4 System Simulator Windows Based SM78K Series System Simulator Reference External Part User Open Interface Specifications Reference Reference Reference U11162E U11334E U11743E U11571E U11572E U13356E U12903E U12155E U13742E EEU-1469 U10093E U10092E Japanese U11162J U11334J U11743J U11571J U11572J U13356J U12903J U12155J U13742J EEU-934 U10093J U10092J ID78K4-NS Integrated Debugger PC Based ID78K4 Integrated Debugger Windows Based ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS based U12796E U10440E U11960E U12796J U10440J U11960J Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. Data Sheet U14121EJ2V0DS00 95 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Documents related to embedded software (user’s manuals) Document Name Document No. English 78K/IV Series Real-Time OS Fundamental Installation Debugger 78K/IV Series OS MX78K4 Fundamental U10603E U10604E − − Japanese U10603J U10604J U10364J U11779J Other documents Document Name Document No. English SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Microcomputer-Related Products by Third Party X13769X C10535E C11531E C10983E C11892E − C10535J C11531J C10983J C11892J U11416J Japanese Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 96 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet U14121EJ2V0DS00 97 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • • • • • Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements • In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829 J00.7 98 Data Sheet U14121EJ2V0DS00 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY IEBus is a trademark of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. Data Sheet U14121EJ2V0DS00 99 www.DataSheet4U.com µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. 2 2 2 2 The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information in this document is current as of August, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4